@@ -54,7 +54,7 @@ module i2c_master (
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output wire m_axis_data_tvalid,
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input wire m_axis_data_tready,
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output wire m_axis_data_tlast,
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-
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+
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/*
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* I2C interface
@@ -69,16 +69,16 @@ module i2c_master (
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/*
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* Status
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*/
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- output wire busy,
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- output wire bus_control,
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- output wire bus_active,
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- output wire missed_ack,
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- output wire value_has_been_written,// triggers on last value
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+ output wire busy,
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+ output wire bus_control,
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+ output wire bus_active,
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+ output wire missed_ack,
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+ output wire value_has_been_written, // triggers on last value
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/*
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* Configuration
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*/
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- input wire [15 :0 ] prescale,
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- input wire stop_on_idle
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+ input wire [15 :0 ] prescale,
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+ input wire stop_on_idle
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);
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/*
@@ -248,7 +248,7 @@ I/O pin. This would prevent devices from stretching the clock period.
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reg [7 :0 ] m_axis_data_tdata_reg = 8'd0 , m_axis_data_tdata_next;
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reg m_axis_data_tvalid_reg = 1'b0 , m_axis_data_tvalid_next;
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reg m_axis_data_tlast_reg = 1'b0 , m_axis_data_tlast_next;
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- reg value_has_been_written_reg = 1'b0 ;
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+ reg value_has_been_written_reg = 1'b0 ;
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reg scl_i_reg = 1'b1 ;
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reg sda_i_reg = 1'b1 ;
@@ -265,7 +265,7 @@ I/O pin. This would prevent devices from stretching the clock period.
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wire phy_busy;
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// reg bus_control_reg = 1'b0, bus_control_next;
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reg missed_ack_reg = 1'b0 , missed_ack_next;
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- assign value_has_been_written = value_has_been_written_reg;
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+ assign value_has_been_written = value_has_been_written_reg;
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assign s_axis_cmd_ready = s_axis_cmd_ready_reg;
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assign s_axis_data_tready = s_axis_data_tready_reg;
@@ -319,6 +319,7 @@ assign value_has_been_written = value_has_been_written_reg;
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m_axis_data_tdata_next = m_axis_data_tdata_reg;
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m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~ m_axis_data_tready;
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m_axis_data_tlast_next = m_axis_data_tlast_reg;
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+ value_has_been_written_reg = 1'b0 ;
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missed_ack_next = 1'b0 ;
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@@ -393,7 +394,8 @@ assign value_has_been_written = value_has_been_written_reg;
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end else if (s_axis_cmd_stop && ! (s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
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// stop command
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phy_stop_bit = 1'b1 ;
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- state_next = STATE_IDLE;
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+ $display ("from active write to idle? why?" );
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+ state_next = STATE_IDLE;
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end else begin
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// invalid or unspecified - ignore
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state_next = STATE_ACTIVE_WRITE;
@@ -524,17 +526,20 @@ assign value_has_been_written = value_has_been_written_reg;
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missed_ack_next = phy_rx_data_reg;
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if (missed_ack_next) begin
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$display ("got NACK" );
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- end else $display ("got ACK" );
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-
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- if (mode_read_reg) begin
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- // start read
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- bit_count_next = 4'd8 ;
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- data_next = 8'b0 ;
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- state_next = STATE_READ;
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+ state_next = STATE_STOP;
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end else begin
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- // start write
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- s_axis_data_tready_next = 1'b1 ;
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- state_next = STATE_WRITE_1;
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+ $display ("got ACK" );
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+
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+ if (mode_read_reg) begin
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+ // start read
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+ bit_count_next = 4'd8 ;
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+ data_next = 8'b0 ;
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+ state_next = STATE_READ;
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+ end else begin
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+ // start write
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+ s_axis_data_tready_next = 1'b1 ;
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+ state_next = STATE_WRITE_1;
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+ end
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end
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end
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STATE_WRITE_1: begin
@@ -569,18 +574,25 @@ assign value_has_been_written = value_has_been_written_reg;
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STATE_WRITE_3: begin
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// read ack bit
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missed_ack_next = phy_rx_data_reg;
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- value_has_been_written_reg= 1 ;
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-
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- if (mode_write_multiple_reg && ! last_reg) begin
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- // more to write
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- state_next = STATE_WRITE_1;
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- end else if (mode_stop_reg) begin
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- // last cycle and stop selected
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- phy_stop_bit = 1'b1 ;
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- state_next = STATE_IDLE;
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+ if (missed_ack_next) begin
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+ $display ("got NACK on write" );
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+ state_next = STATE_STOP;
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end else begin
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- // otherwise, return to bus active state
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- state_next = STATE_ACTIVE_WRITE;
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+ $display ("got ACK on write %d" , $time );
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+
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+ value_has_been_written_reg = 1 ; // only if successful!
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+
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+ if (mode_write_multiple_reg && ! last_reg) begin
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+ // more to write
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+ state_next = STATE_WRITE_1;
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+ end else if (mode_stop_reg) begin
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+ // last cycle and stop selected
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+ phy_stop_bit = 1'b1 ;
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+ state_next = STATE_IDLE;
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+ end else begin
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+ // otherwise, return to bus active state
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+ state_next = STATE_ACTIVE_WRITE;
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+ end
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end
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end
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STATE_READ: begin
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