Skip to content

Commit e9e408a

Browse files
committed
changing testbenches, on NACK simply stop.. no need to go further...
1 parent 019a642 commit e9e408a

File tree

4 files changed

+132
-62
lines changed

4 files changed

+132
-62
lines changed

rtl/i2c_master.v

Lines changed: 44 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ module i2c_master (
5454
output wire m_axis_data_tvalid,
5555
input wire m_axis_data_tready,
5656
output wire m_axis_data_tlast,
57-
57+
5858

5959
/*
6060
* I2C interface
@@ -69,16 +69,16 @@ module i2c_master (
6969
/*
7070
* Status
7171
*/
72-
output wire busy,
73-
output wire bus_control,
74-
output wire bus_active,
75-
output wire missed_ack,
76-
output wire value_has_been_written,//triggers on last value
72+
output wire busy,
73+
output wire bus_control,
74+
output wire bus_active,
75+
output wire missed_ack,
76+
output wire value_has_been_written, //triggers on last value
7777
/*
7878
* Configuration
7979
*/
80-
input wire [15:0] prescale,
81-
input wire stop_on_idle
80+
input wire [15:0] prescale,
81+
input wire stop_on_idle
8282
);
8383

8484
/*
@@ -248,7 +248,7 @@ I/O pin. This would prevent devices from stretching the clock period.
248248
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
249249
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
250250
reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
251-
reg value_has_been_written_reg =1'b0;
251+
reg value_has_been_written_reg = 1'b0;
252252

253253
reg scl_i_reg = 1'b1;
254254
reg sda_i_reg = 1'b1;
@@ -265,7 +265,7 @@ I/O pin. This would prevent devices from stretching the clock period.
265265
wire phy_busy;
266266
//reg bus_control_reg = 1'b0, bus_control_next;
267267
reg missed_ack_reg = 1'b0, missed_ack_next;
268-
assign value_has_been_written = value_has_been_written_reg;
268+
assign value_has_been_written = value_has_been_written_reg;
269269
assign s_axis_cmd_ready = s_axis_cmd_ready_reg;
270270

271271
assign s_axis_data_tready = s_axis_data_tready_reg;
@@ -319,6 +319,7 @@ assign value_has_been_written = value_has_been_written_reg;
319319
m_axis_data_tdata_next = m_axis_data_tdata_reg;
320320
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
321321
m_axis_data_tlast_next = m_axis_data_tlast_reg;
322+
value_has_been_written_reg = 1'b0;
322323

323324
missed_ack_next = 1'b0;
324325

@@ -393,7 +394,8 @@ assign value_has_been_written = value_has_been_written_reg;
393394
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
394395
// stop command
395396
phy_stop_bit = 1'b1;
396-
state_next = STATE_IDLE;
397+
$display("from active write to idle? why?");
398+
state_next = STATE_IDLE;
397399
end else begin
398400
// invalid or unspecified - ignore
399401
state_next = STATE_ACTIVE_WRITE;
@@ -524,17 +526,20 @@ assign value_has_been_written = value_has_been_written_reg;
524526
missed_ack_next = phy_rx_data_reg;
525527
if (missed_ack_next) begin
526528
$display("got NACK");
527-
end else $display("got ACK");
528-
529-
if (mode_read_reg) begin
530-
// start read
531-
bit_count_next = 4'd8;
532-
data_next = 8'b0;
533-
state_next = STATE_READ;
529+
state_next = STATE_STOP;
534530
end else begin
535-
// start write
536-
s_axis_data_tready_next = 1'b1;
537-
state_next = STATE_WRITE_1;
531+
$display("got ACK");
532+
533+
if (mode_read_reg) begin
534+
// start read
535+
bit_count_next = 4'd8;
536+
data_next = 8'b0;
537+
state_next = STATE_READ;
538+
end else begin
539+
// start write
540+
s_axis_data_tready_next = 1'b1;
541+
state_next = STATE_WRITE_1;
542+
end
538543
end
539544
end
540545
STATE_WRITE_1: begin
@@ -569,18 +574,25 @@ assign value_has_been_written = value_has_been_written_reg;
569574
STATE_WRITE_3: begin
570575
// read ack bit
571576
missed_ack_next = phy_rx_data_reg;
572-
value_has_been_written_reg=1;
573-
574-
if (mode_write_multiple_reg && !last_reg) begin
575-
// more to write
576-
state_next = STATE_WRITE_1;
577-
end else if (mode_stop_reg) begin
578-
// last cycle and stop selected
579-
phy_stop_bit = 1'b1;
580-
state_next = STATE_IDLE;
577+
if (missed_ack_next) begin
578+
$display("got NACK on write");
579+
state_next = STATE_STOP;
581580
end else begin
582-
// otherwise, return to bus active state
583-
state_next = STATE_ACTIVE_WRITE;
581+
$display("got ACK on write %d", $time);
582+
583+
value_has_been_written_reg = 1; //only if successful!
584+
585+
if (mode_write_multiple_reg && !last_reg) begin
586+
// more to write
587+
state_next = STATE_WRITE_1;
588+
end else if (mode_stop_reg) begin
589+
// last cycle and stop selected
590+
phy_stop_bit = 1'b1;
591+
state_next = STATE_IDLE;
592+
end else begin
593+
// otherwise, return to bus active state
594+
state_next = STATE_ACTIVE_WRITE;
595+
end
584596
end
585597
end
586598
STATE_READ: begin

rtl/i2c_phy.v

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -51,24 +51,24 @@ module i2c_phy (
5151

5252
// Internal registers
5353

54-
reg scl_o_reg;
55-
reg scl_i_reg;
56-
reg sda_i_reg;
57-
reg sda_o_reg;
54+
reg scl_o_reg = 1;
55+
reg scl_i_reg = 1;
56+
reg sda_i_reg = 1;
57+
reg sda_o_reg = 1;
5858

5959

60-
reg phy_rx_data_next;
60+
reg phy_rx_data_next = 0;
6161

6262
reg [4:0] phy_state_next;
6363

6464
reg [16:0] delay_reg = 17'd0, delay_next;
6565
reg delay_scl_reg = 1'b0, delay_scl_next;
6666
reg delay_sda_reg = 1'b0, delay_sda_next;
6767

68-
reg scl_o_next;
69-
reg sda_o_next;
68+
reg scl_o_next = 1;
69+
reg sda_o_next = 1;
7070

71-
reg bus_control_next;
71+
reg bus_control_next = 0;
7272

7373
assign scl_o = scl_o_reg;
7474
assign scl_t = scl_o_reg;

rtl/i2c_slave.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,8 +201,8 @@ I/O pin. This would prevent devices from stretching the clock period.
201201
reg scl_i_reg = 1'b1;
202202
reg sda_i_reg = 1'b1;
203203

204-
reg scl_o_reg = 1'b1, scl_o_next;
205-
reg sda_o_reg = 1'b1, sda_o_next;
204+
reg scl_o_reg = 1'b1, scl_o_next = 1;
205+
reg sda_o_reg = 1'b1, sda_o_next = 1;
206206

207207
reg last_scl_i_reg = 1'b1;
208208
reg last_sda_i_reg = 1'b1;

0 commit comments

Comments
 (0)