workflows: test fix for modules names in trace file

Author: magancarz

.github/workflows/static-power-analysis-flow.yml

@@ -48,8 +48,7 @@ jobs:
       - name: Fetch Verilator
         run: |
           git clone https://github.com/verilator/verilator
-          # UDP changes commit
-          cd verilator && git checkout d0c4cc393869b5570e51ead2420dcc2ce60fe1b5
+          cd verilator && git fetch && git checkout mgan/module-names-debugging
 
       - name: Build Verilator
         run: |
@@ -124,8 +123,7 @@ jobs:
       - name: Fetch Verilator
         run: |
           git clone https://github.com/verilator/verilator
-          # UDP changes commit
-          cd verilator && git checkout d0c4cc393869b5570e51ead2420dcc2ce60fe1b5
+          cd verilator && git fetch && git checkout mgan/module-names-debugging
 
       - name: Build Verilator
         run: |
@@ -222,8 +220,7 @@ jobs:
       - name: Fetch Verilator
         run: |
           git clone https://github.com/verilator/verilator
-          # UDP changes commit
-          cd verilator && git checkout d0c4cc393869b5570e51ead2420dcc2ce60fe1b5
+          cd verilator && git fetch && git checkout mgan/module-names-debugging
 
       - name: Build Verilator
         run: |