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hujun260hujun260
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arch: use raw_spin_[un]lock to replace spin_[un]lock, fix regression b69111d of #14578
reason: Due to the addition of sched_lock in the spinlock, using a spinlock in the *cpustart file during the boot phase is quite special. CPU0 waits for CPU1 to start up, using a spinlock as a multi-core synchronization strategy. However, the matching calls are not made within the same task, resulting in a mismatch in the scheduler lock count and preventing the system from booting. The sequence is: CPU0 spin_lock, spin_lock, spin_unlock; CPU1 spin_unlock. CPU0 and CPU1 are running different tasks. Signed-off-by: hujun5 <[email protected]>
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8 files changed

+32
-32
lines changed

8 files changed

+32
-32
lines changed

‎arch/arm/src/cxd56xx/cxd56_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ static void appdsp_boot(void)
122122
irq_attach(CXD56_IRQ_SMP_CALL, cxd56_smp_call_handler, NULL);
123123
up_enable_irq(CXD56_IRQ_SMP_CALL);
124124

125-
spin_unlock(&g_appdsp_boot);
125+
raw_spin_unlock(&g_appdsp_boot);
126126

127127
#ifdef CONFIG_SCHED_INSTRUMENTATION
128128
/* Notify that this CPU has started */
@@ -189,7 +189,7 @@ int up_cpu_start(int cpu)
189189
tcb->adj_stack_size, VECTOR_ISTACK);
190190
putreg32((uint32_t)appdsp_boot, VECTOR_RESETV);
191191

192-
spin_lock(&g_appdsp_boot);
192+
raw_spin_lock(&g_appdsp_boot);
193193

194194
/* See 3.13.4.16.3 ADSP Startup */
195195

@@ -238,11 +238,11 @@ int up_cpu_start(int cpu)
238238
up_enable_irq(CXD56_IRQ_SMP_CALL);
239239
}
240240

241-
spin_lock(&g_appdsp_boot);
241+
raw_spin_lock(&g_appdsp_boot);
242242

243243
/* APP_DSP(cpu) boot done */
244244

245-
spin_unlock(&g_appdsp_boot);
245+
raw_spin_unlock(&g_appdsp_boot);
246246

247247
return 0;
248248
}

‎arch/arm/src/lc823450/lc823450_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ static void cpu1_boot(void)
112112
up_enable_irq(LC823450_IRQ_SMP_CALL_01);
113113
}
114114

115-
spin_unlock(&g_cpu_wait[0]);
115+
raw_spin_unlock(&g_cpu_wait[0]);
116116

117117
#ifdef CONFIG_SCHED_INSTRUMENTATION
118118
/* Notify that this CPU has started */
@@ -177,7 +177,7 @@ int up_cpu_start(int cpu)
177177
tcb->adj_stack_size, CPU1_VECTOR_ISTACK);
178178
putreg32((uint32_t)cpu1_boot, CPU1_VECTOR_RESETV);
179179

180-
spin_lock(&g_cpu_wait[0]);
180+
raw_spin_lock(&g_cpu_wait[0]);
181181

182182
#ifdef CONFIG_SCHED_INSTRUMENTATION
183183
/* Notify of the start event */
@@ -198,7 +198,7 @@ int up_cpu_start(int cpu)
198198
irq_attach(LC823450_IRQ_SMP_CALL_11, lc823450_smp_call_handler, NULL);
199199
up_enable_irq(LC823450_IRQ_SMP_CALL_11);
200200

201-
spin_lock(&g_cpu_wait[0]);
201+
raw_spin_lock(&g_cpu_wait[0]);
202202

203203
/* CPU1 boot done */
204204

@@ -208,7 +208,7 @@ int up_cpu_start(int cpu)
208208
putreg32(backup[1], CPU1_VECTOR_RESETV);
209209
putreg32(0x0, REMAP); /* remap disable */
210210

211-
spin_unlock(&g_cpu_wait[0]);
211+
raw_spin_unlock(&g_cpu_wait[0]);
212212

213213
return 0;
214214
}

‎arch/arm/src/rp2040/rp2040_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ static void core1_boot(void)
156156
irq_attach(RP2040_SMP_CALL_PROC1, rp2040_smp_call_handler, NULL);
157157
up_enable_irq(RP2040_SMP_CALL_PROC1);
158158

159-
spin_unlock(&g_core1_boot);
159+
raw_spin_unlock(&g_core1_boot);
160160

161161
#ifdef CONFIG_SCHED_INSTRUMENTATION
162162
/* Notify that this CPU has started */
@@ -221,7 +221,7 @@ int up_cpu_start(int cpu)
221221
;
222222
clrbits_reg32(RP2040_PSM_PROC1, RP2040_PSM_FRCE_OFF);
223223

224-
spin_lock(&g_core1_boot);
224+
raw_spin_lock(&g_core1_boot);
225225

226226
/* Send initial VTOR, MSP, PC for Core 1 boot */
227227

@@ -252,11 +252,11 @@ int up_cpu_start(int cpu)
252252
irq_attach(RP2040_SMP_CALL_PROC0, rp2040_smp_call_handler, NULL);
253253
up_enable_irq(RP2040_SMP_CALL_PROC0);
254254

255-
spin_lock(&g_core1_boot);
255+
raw_spin_lock(&g_core1_boot);
256256

257257
/* CPU Core 1 boot done */
258258

259-
spin_unlock(&g_core1_boot);
259+
raw_spin_unlock(&g_core1_boot);
260260

261261
return 0;
262262
}

‎arch/arm/src/rp23xx/rp23xx_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ static void core1_boot(void)
156156
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
157157
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
158158

159-
spin_unlock(&g_core1_boot);
159+
raw_spin_unlock(&g_core1_boot);
160160

161161
#ifdef CONFIG_SCHED_INSTRUMENTATION
162162
/* Notify that this CPU has started */
@@ -221,7 +221,7 @@ int up_cpu_start(int cpu)
221221
;
222222
clrbits_reg32(RP23XX_PSM_PROC1, RP23XX_PSM_FRCE_OFF);
223223

224-
spin_lock(&g_core1_boot);
224+
raw_spin_lock(&g_core1_boot);
225225

226226
/* Send initial VTOR, MSP, PC for Core 1 boot */
227227

@@ -252,11 +252,11 @@ int up_cpu_start(int cpu)
252252
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
253253
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
254254

255-
spin_lock(&g_core1_boot);
255+
raw_spin_lock(&g_core1_boot);
256256

257257
/* CPU Core 1 boot done */
258258

259-
spin_unlock(&g_core1_boot);
259+
raw_spin_unlock(&g_core1_boot);
260260

261261
return 0;
262262
}

‎arch/arm/src/sam34/sam4cm_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ static void cpu1_boot(void)
114114
up_enable_irq(SAM_IRQ_SMP_CALL1);
115115
}
116116

117-
spin_unlock(&g_cpu1_boot);
117+
raw_spin_unlock(&g_cpu1_boot);
118118

119119
#ifdef CONFIG_SCHED_INSTRUMENTATION
120120
/* Notify that this CPU has started */
@@ -209,7 +209,7 @@ int up_cpu_start(int cpu)
209209
tcb->adj_stack_size, CPU1_VECTOR_ISTACK);
210210
putreg32((uint32_t)cpu1_boot, CPU1_VECTOR_RESETV);
211211

212-
spin_lock(&g_cpu1_boot);
212+
raw_spin_lock(&g_cpu1_boot);
213213

214214
/* Unreset coprocessor */
215215

@@ -223,11 +223,11 @@ int up_cpu_start(int cpu)
223223
irq_attach(SAM_IRQ_SMP_CALL0, sam4cm_smp_call_handler, NULL);
224224
up_enable_irq(SAM_IRQ_SMP_CALL0);
225225

226-
spin_lock(&g_cpu1_boot);
226+
raw_spin_lock(&g_cpu1_boot);
227227

228228
/* CPU1 boot done */
229229

230-
spin_unlock(&g_cpu1_boot);
230+
raw_spin_unlock(&g_cpu1_boot);
231231

232232
return 0;
233233
}

‎arch/sparc/src/s698pm/s698pm_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ void s698pm_cpu_boot(void)
7979

8080
s698pm_cpuint_initialize();
8181

82-
spin_unlock(&g_cpu_boot);
82+
raw_spin_unlock(&g_cpu_boot);
8383

8484
#ifdef CONFIG_SCHED_INSTRUMENTATION
8585
/* Notify that this CPU has started */
@@ -150,17 +150,17 @@ int up_cpu_start(int cpu)
150150
regaddr = S698PM_DSU_BASE + (0x1000000 * cpu) + S698PM_DSU_NPC_OFFSET;
151151
putreg32(0x40001004, regaddr);
152152

153-
spin_lock(&g_cpu_boot);
153+
raw_spin_lock(&g_cpu_boot);
154154

155155
/* set 1 to bit n of multiprocessor status register to active cpu n */
156156

157157
putreg32(1 << cpu, S698PM_IRQREG_MPSTATUS);
158158

159-
spin_lock(&g_cpu_boot);
159+
raw_spin_lock(&g_cpu_boot);
160160

161161
/* prev cpu boot done */
162162

163-
spin_unlock(&g_cpu_boot);
163+
raw_spin_unlock(&g_cpu_boot);
164164

165165
return 0;
166166
}

‎arch/xtensa/src/esp32/esp32_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ void IRAM_ATTR xtensa_appcpu_start(void)
133133
*/
134134

135135
g_appcpu_started = true;
136-
spin_unlock(&g_appcpu_interlock);
136+
raw_spin_unlock(&g_appcpu_interlock);
137137

138138
/* Reset scheduler parameters */
139139

@@ -242,7 +242,7 @@ int up_cpu_start(int cpu)
242242
*/
243243

244244
spin_lock_init(&g_appcpu_interlock);
245-
spin_lock(&g_appcpu_interlock);
245+
raw_spin_lock(&g_appcpu_interlock);
246246

247247
/* Unstall the APP CPU */
248248

@@ -288,11 +288,11 @@ int up_cpu_start(int cpu)
288288

289289
/* And wait until the APP CPU starts and releases the spinlock. */
290290

291-
spin_lock(&g_appcpu_interlock);
291+
raw_spin_lock(&g_appcpu_interlock);
292292

293293
/* prev cpu boot done */
294294

295-
spin_unlock(&g_appcpu_interlock);
295+
raw_spin_unlock(&g_appcpu_interlock);
296296
DEBUGASSERT(g_appcpu_started);
297297
}
298298

‎arch/xtensa/src/esp32s3/esp32s3_cpustart.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ void xtensa_appcpu_start(void)
132132
*/
133133

134134
g_appcpu_started = true;
135-
spin_unlock(&g_appcpu_interlock);
135+
raw_spin_unlock(&g_appcpu_interlock);
136136

137137
/* Reset scheduler parameters */
138138

@@ -227,7 +227,7 @@ int up_cpu_start(int cpu)
227227
*/
228228

229229
spin_lock_init(&g_appcpu_interlock);
230-
spin_lock(&g_appcpu_interlock);
230+
raw_spin_lock(&g_appcpu_interlock);
231231

232232
/* OpenOCD might have already enabled clock gating and taken APP CPU
233233
* out of reset. Don't reset the APP CPU if that's the case as this
@@ -272,11 +272,11 @@ int up_cpu_start(int cpu)
272272

273273
/* And wait until the APP CPU starts and releases the spinlock. */
274274

275-
spin_lock(&g_appcpu_interlock);
275+
raw_spin_lock(&g_appcpu_interlock);
276276

277277
/* prev cpu boot done */
278278

279-
spin_unlock(&g_appcpu_interlock);
279+
raw_spin_unlock(&g_appcpu_interlock);
280280
DEBUGASSERT(g_appcpu_started);
281281
}
282282

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