Added RISC-V V extension intrinsics for LLVM

Author: fzi-peccia

include/tvm/meta_schedule/postproc.h

@@ -167,6 +167,8 @@ class Postproc : public runtime::ObjectRef {
   TVM_DLL static Array<Postproc, void> DefaultLLVM();
   /*! \brief Create default postprocessors for x86 (AVX512 and VNNI) */
   TVM_DLL static Array<Postproc, void> DefaultCPUTensorization();
+  /*! \brief Create default postprocessors for RISCV */
+  TVM_DLL static Array<Postproc, void> DefaultRISCV();
   /*! \brief Create default postprocessors for CUDA */
   TVM_DLL static Array<Postproc, void> DefaultCUDA();
   /*! \brief Create default postprocessors for CUDA with TensorCore */

include/tvm/meta_schedule/schedule_rule.h

@@ -302,6 +302,8 @@ class ScheduleRule : public runtime::ObjectRef {
   TVM_DLL static Array<ScheduleRule, void> DefaultHexagon();
   /*! \brief Create default schedule rules for ARM CPU (NEON and DOTPROD) */
   TVM_DLL static Array<ScheduleRule, void> DefaultARM(const String& type);
+  /*! \brief Create default schedule rules for RISCV CPU (RVV) */
+  TVM_DLL static Array<ScheduleRule, void> DefaultRISCV(int vlen);
 
   TVM_DEFINE_MUTABLE_OBJECT_REF_METHODS(ScheduleRule, ObjectRef, ScheduleRuleNode);
 };

python/tvm/meta_schedule/tune_context.py

@@ -117,6 +117,14 @@ def __init__(
         if target is not None:
             if not isinstance(target, Target):
                 target = Target(target)
+            if "riscv_cpu" in target.keys:
+                base_features = str(target.attrs["march"]).split("_")[0].replace("rv", "")
+                if "v" in base_features:
+                    # Because the RVV intrinsics depend on the target, we register them here
+                    # pylint: disable=import-outside-toplevel
+                    from tvm.tir.tensor_intrin.riscv_cpu import register_riscv_tensor_intrinsics
+
+                    register_riscv_tensor_intrinsics(target)
         if space_generator is not None:
             if not isinstance(space_generator, SpaceGenerator):
                 space_generator = SpaceGenerator.create(space_generator)

python/tvm/target/target.py

@@ -637,6 +637,18 @@ def riscv_cpu(model="sifive-u54", options=None):
             "-mabi=lp64d",
             # cc: riscv64-unknown-linux-gnu-g++ -march=rv64gc -mabi=lp64d -mcpu=sifive-u74
         ],
+        "bpi-f3": [
+            # "-model=sifive-u74",
+            "-mtriple=riscv64-unknown-linux-gnu",
+            "-mcpu=generic",
+            # "-march=rv64gcv_zvl256b",
+            # "-mcpu=generic-rv64",
+            "-mfloat-abi=hard",
+            "-num-cores=8",
+            "-mabi=lp64d",
+            "-mattr=+v,+zvl256b",
+            # cc: riscv64-unknown-linux-gnu-g++ -march=rv64gc -mabi=lp64d -mcpu=generic -mattr=+v
+        ],
     }
     pre_defined_opt = trans_table.get(model, ["-model=%s" % model])
 

python/tvm/tir/tensor_intrin/__init__.py

@@ -20,4 +20,4 @@
 from . import cuda
 
 if enabled("llvm"):
-    from . import arm_cpu, x86, rocm, hexagon
+    from . import arm_cpu, x86, rocm, hexagon, riscv_cpu