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AArch64: factorize and increase coverage
Signed-off-by: Paul Guyot <[email protected]>
1 parent 69d5f92 commit eb582ff

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+77
-37
lines changed

2 files changed

+77
-37
lines changed

‎libs/jit/src/jit_aarch64.erl‎

Lines changed: 21 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -824,24 +824,16 @@ if_block_cond(
824824
) when ?IS_GPR(Reg) ->
825825
% AND with mask
826826
OffsetBefore = StreamModule:offset(Stream0),
827-
Stream1 =
828-
try
829-
I = jit_aarch64_asm:and_(Temp, Reg, Mask),
830-
StreamModule:append(Stream0, I)
831-
catch
832-
error:{unencodable_immediate, Val} ->
833-
MoveI = jit_aarch64_asm:mov(Temp, Mask),
834-
AndI = jit_aarch64_asm:and_(Temp, Reg, Temp),
835-
StreamModule:append(Stream0, <<MoveI/binary, AndI/binary>>)
836-
end,
827+
State1 = op_imm(State0, and_, Temp, Reg, Mask),
828+
Stream1 = State1#state.stream,
837829
% Compare with value
838830
I2 = jit_aarch64_asm:cmp(Temp, Val),
839831
Stream2 = StreamModule:append(Stream1, I2),
840832
OffsetAfter = StreamModule:offset(Stream2),
841833
I3 = jit_aarch64_asm:bcc(eq, 0),
842834
Stream3 = StreamModule:append(Stream2, I3),
843-
State1 = State0#state{stream = Stream3},
844-
{State1, eq, OffsetAfter - OffsetBefore};
835+
State2 = State1#state{stream = Stream3},
836+
{State2, eq, OffsetAfter - OffsetBefore};
845837
if_block_cond(
846838
#state{
847839
stream_module = StreamModule,
@@ -1728,47 +1720,40 @@ get_module_index(
17281720
Reg
17291721
}.
17301722

1731-
and_(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Val) ->
1723+
op_imm(#state{stream_module = StreamModule, stream = Stream0} = State, Op, Reg, Reg, Val) ->
17321724
Stream1 =
17331725
try
1734-
I = jit_aarch64_asm:and_(Reg, Reg, Val),
1726+
I = jit_aarch64_asm:Op(Reg, Reg, Val),
17351727
StreamModule:append(Stream0, I)
17361728
catch
17371729
error:{unencodable_immediate, Val} ->
17381730
[Temp | _] = State#state.available_regs,
17391731
I1 = jit_aarch64_asm:mov(Temp, Val),
1740-
I2 = jit_aarch64_asm:and_(Reg, Reg, Temp),
1732+
I2 = jit_aarch64_asm:Op(Reg, Reg, Temp),
17411733
StreamModule:append(Stream0, <<I1/binary, I2/binary>>)
17421734
end,
1743-
State#state{stream = Stream1}.
1744-
1745-
or_(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Val) ->
1735+
State#state{stream = Stream1};
1736+
op_imm(#state{stream_module = StreamModule, stream = Stream0} = State, Op, RegA, RegB, Val) ->
17461737
Stream1 =
17471738
try
1748-
I = jit_aarch64_asm:orr(Reg, Reg, Val),
1739+
I = jit_aarch64_asm:Op(RegA, RegB, Val),
17491740
StreamModule:append(Stream0, I)
17501741
catch
17511742
error:{unencodable_immediate, Val} ->
1752-
[Temp | _] = State#state.available_regs,
1753-
I1 = jit_aarch64_asm:mov(Temp, Val),
1754-
I2 = jit_aarch64_asm:orr(Reg, Reg, Temp),
1755-
StreamModule:append(Stream0, <<I1/binary, I2/binary>>)
1743+
MoveI = jit_aarch64_asm:mov(RegA, Val),
1744+
AndI = jit_aarch64_asm:Op(RegA, RegB, RegA),
1745+
StreamModule:append(Stream0, <<MoveI/binary, AndI/binary>>)
17561746
end,
17571747
State#state{stream = Stream1}.
17581748

1759-
add(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Val) ->
1760-
Stream1 =
1761-
try
1762-
I = jit_aarch64_asm:add(Reg, Reg, Val),
1763-
StreamModule:append(Stream0, I)
1764-
catch
1765-
error:{unencodable_immediate, Val} ->
1766-
[Temp | _] = State#state.available_regs,
1767-
I1 = jit_aarch64_asm:mov(Temp, Val),
1768-
I2 = jit_aarch64_asm:add(Reg, Reg, Temp),
1769-
StreamModule:append(Stream0, <<I1/binary, I2/binary>>)
1770-
end,
1771-
State#state{stream = Stream1}.
1749+
and_(State, Reg, Val) ->
1750+
op_imm(State, and_, Reg, Reg, Val).
1751+
1752+
or_(State, Reg, Val) ->
1753+
op_imm(State, orr, Reg, Reg, Val).
1754+
1755+
add(State, Reg, Val) ->
1756+
op_imm(State, add, Reg, Reg, Val).
17721757

17731758
sub(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Val) ->
17741759
I1 = jit_aarch64_asm:sub(Reg, Reg, Val),

‎tests/libs/jit/jit_aarch64_asm_tests.erl‎

Lines changed: 56 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,62 @@ bcc_test_() ->
331331
?_assertEqual(<<16#54000000:32/little>>, jit_aarch64_asm:bcc(eq, 0)),
332332
?_assertEqual(<<16#54000001:32/little>>, jit_aarch64_asm:bcc(ne, 0)),
333333
?_assertEqual(<<16#54fffe01:32/little>>, jit_aarch64_asm:bcc(ne, -64)),
334-
?_assertEqual(<<16#54000400:32/little>>, jit_aarch64_asm:bcc(eq, 128))
334+
?_assertEqual(
335+
asm(<<16#54000400:32/little>>, "b.eq 128"),
336+
jit_aarch64_asm:bcc(eq, 128)
337+
),
338+
?_assertEqual(
339+
asm(<<16#54000402:32/little>>, "b.cs 128"),
340+
jit_aarch64_asm:bcc(cs, 128)
341+
),
342+
?_assertEqual(
343+
asm(<<16#54000403:32/little>>, "b.cc 128"),
344+
jit_aarch64_asm:bcc(cc, 128)
345+
),
346+
?_assertEqual(
347+
asm(<<16#54000404:32/little>>, "b.mi 128"),
348+
jit_aarch64_asm:bcc(mi, 128)
349+
),
350+
?_assertEqual(
351+
asm(<<16#54000405:32/little>>, "b.pl 128"),
352+
jit_aarch64_asm:bcc(pl, 128)
353+
),
354+
?_assertEqual(
355+
asm(<<16#54000406:32/little>>, "b.vs 128"),
356+
jit_aarch64_asm:bcc(vs, 128)
357+
),
358+
?_assertEqual(
359+
asm(<<16#54000408:32/little>>, "b.hi 128"),
360+
jit_aarch64_asm:bcc(hi, 128)
361+
),
362+
?_assertEqual(
363+
asm(<<16#54000409:32/little>>, "b.ls 128"),
364+
jit_aarch64_asm:bcc(ls, 128)
365+
),
366+
?_assertEqual(
367+
asm(<<16#5400040a:32/little>>, "b.ge 128"),
368+
jit_aarch64_asm:bcc(ge, 128)
369+
),
370+
?_assertEqual(
371+
asm(<<16#5400040b:32/little>>, "b.lt 128"),
372+
jit_aarch64_asm:bcc(lt, 128)
373+
),
374+
?_assertEqual(
375+
asm(<<16#5400040c:32/little>>, "b.gt 128"),
376+
jit_aarch64_asm:bcc(gt, 128)
377+
),
378+
?_assertEqual(
379+
asm(<<16#5400040d:32/little>>, "b.le 128"),
380+
jit_aarch64_asm:bcc(le, 128)
381+
),
382+
?_assertEqual(
383+
asm(<<16#5400040e:32/little>>, "b.al 128"),
384+
jit_aarch64_asm:bcc(al, 128)
385+
),
386+
?_assertEqual(
387+
asm(<<16#5400040f:32/little>>, "b.nv 128"),
388+
jit_aarch64_asm:bcc(nv, 128)
389+
)
335390
].
336391

337392
stp_test_() ->

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