fix Python build failure

Author: moste00

bindings/python/capstone/__init__.py

@@ -106,7 +106,25 @@
     'CS_MODE_BPF_EXTENDED',
     'CS_MODE_RISCV32',
     'CS_MODE_RISCV64',
-    'CS_MODE_RISCVC',
+   	'CS_MODE_RISCV_C',
+	'CS_MODE_RISCV_FD',
+	'CS_MODE_RISCV_V',
+	'CS_MODE_RISCV_ZFINX',
+	'CS_MODE_RISCV_ZCMP_ZCMT_ZCE',
+	'CS_MODE_RISCV_ZICFISS',
+	'CS_MODE_RISCV_E',
+	'CS_MODE_RISCV_A',
+	'CS_MODE_RISCV_COREV',
+	'CS_MODE_RISCV_THEAD',
+	'CS_MODE_RISCV_SIFIVE',
+	'CS_MODE_RISCV_BITMANIP',
+	'CS_MODE_RISCV_ZBA',
+	'CS_MODE_RISCV_ZBB',
+	'CS_MODE_RISCV_ZBC',
+	'CS_MODE_RISCV_ZBKB',
+	'CS_MODE_RISCV_ZBKC',
+	'CS_MODE_RISCV_ZBKX',
+	'CS_MODE_RISCV_ZBS',
     'CS_MODE_MOS65XX_6502',
     'CS_MODE_MOS65XX_65C02',
     'CS_MODE_MOS65XX_W65C02',
@@ -159,6 +177,7 @@
     'CS_OPT_SYNTAX_MOTOROLA',
     'CS_OPT_SYNTAX_CS_REG_ALIAS',
     'CS_OPT_SYNTAX_NO_DOLLAR',
+    'CS_OPT_SYNTAX_NO_ALIAS_TEXT',
 
     'CS_OPT_DETAIL',
     'CS_OPT_DETAIL_REAL',
@@ -332,7 +351,7 @@
 CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support
 CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support
 CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support
-CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips 
+CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
 CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1
 CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200
 CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops
@@ -353,7 +372,25 @@
 CS_MODE_BPF_EXTENDED = (1 << 0)  # Extended BPF mode
 CS_MODE_RISCV32 = (1 << 0)       # RISCV32 mode
 CS_MODE_RISCV64 = (1 << 1)       # RISCV64 mode
-CS_MODE_RISCVC  = (1 << 2)       # RISCV compressed mode
+CS_MODE_RISCV_C = 1 << 2,        # RISCV compressed instructure mode
+CS_MODE_RISCV_FD = 1 << 3,
+CS_MODE_RISCV_V  = 1 << 4,
+CS_MODE_RISCV_ZFINX         = 1 << 5,
+CS_MODE_RISCV_ZCMP_ZCMT_ZCE = 1 << 6,
+CS_MODE_RISCV_ZICFISS = 1 << 7,
+CS_MODE_RISCV_E       = 1 << 8,
+CS_MODE_RISCV_A       = 1 << 9,
+CS_MODE_RISCV_COREV   = 1 << 10,
+CS_MODE_RISCV_THEAD   = 1 << 11,
+CS_MODE_RISCV_SIFIVE  = 1 << 12,
+CS_MODE_RISCV_BITMANIP = 1 << 13,
+CS_MODE_RISCV_ZBA  = 1 << 14,
+CS_MODE_RISCV_ZBB  = 1 << 15,
+CS_MODE_RISCV_ZBC  = 1 << 16,
+CS_MODE_RISCV_ZBKB = 1 << 17,
+CS_MODE_RISCV_ZBKC = 1 << 18,
+CS_MODE_RISCV_ZBKX = 1 << 19,
+CS_MODE_RISCV_ZBS  = 1 << 20,
 CS_MODE_MOS65XX_6502 = (1 << 1) # MOS65XXX MOS 6502
 CS_MODE_MOS65XX_65C02 = (1 << 2) # MOS65XXX WDC 65c02
 CS_MODE_MOS65XX_W65C02 = (1 << 3) # MOS65XXX WDC W65c02
@@ -461,6 +498,7 @@
 CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7)  # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
 CS_OPT_SYNTAX_PERCENT = (1 << 8)  # Prints the % in front of PPC registers.
 CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips, LoongArch registers.
+CS_OPT_SYNTAX_NO_ALIAS_TEXT = (1 << 10) # Does not print an instruction's alias test if the instruction is an alias
 CS_OPT_DETAIL_REAL = (1 << 1)  # If enabled, always sets the real instruction detail.Even if the instruction is an alias.
 
 # Capstone error type
@@ -1468,7 +1506,7 @@ def debug():
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
         'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
-        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA, 
+        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
         'arc': CS_ARCH_ARC
     }
 

bindings/python/capstone/riscv.py

@@ -1,34 +1,44 @@
 # Capstone Python bindings, by Nguyen Anh Quynnh <[email protected]>
 
 import ctypes
+
 from . import copy_ctypes_list
 from .riscv_const import *
 
+
 # define the API
 class RISCVOpMem(ctypes.Structure):
     _fields_ = (
-        ('base', ctypes.c_uint),
-        ('disp', ctypes.c_int64),
+        ("base", ctypes.c_uint),
+        ("disp", ctypes.c_int64),
     )
 
+
 class RISCVOpValue(ctypes.Union):
     _fields_ = (
-        ('reg', ctypes.c_uint),
-        ('imm', ctypes.c_int64),
-        ('mem', RISCVOpMem),
+        ("reg", ctypes.c_uint),
+        ("imm", ctypes.c_int64),
+        ("dimm", ctypes.c_double),
+        ("mem", RISCVOpMem),
+        ("csr", ctypes.c_uint16),
     )
 
+
 class RISCVOp(ctypes.Structure):
     _fields_ = (
-        ('type', ctypes.c_uint),
-        ('value', RISCVOpValue),
-        ('access', ctypes.c_uint),
+        ("type", ctypes.c_uint),
+        ("value", RISCVOpValue),
+        ("access", ctypes.c_uint),
     )
 
     @property
     def imm(self):
         return self.value.imm
 
+    @property
+    def dimm(self):
+        return self.value.dimm
+
     @property
     def reg(self):
         return self.value.reg
@@ -37,14 +47,18 @@ def reg(self):
     def mem(self):
         return self.value.mem
 
+    @property
+    def csr(self):
+        return self.value.csr
+
 
 class CsRISCV(ctypes.Structure):
     _fields_ = (
-        ('need_effective_addr', ctypes.c_bool),
-        ('op_count',            ctypes.c_uint8),
-        ('operands',            RISCVOp * 8),
+        ("need_effective_addr", ctypes.c_bool),
+        ("op_count", ctypes.c_uint8),
+        ("operands", RISCVOp * 8),
     )
 
-def get_arch_info(a):
-    return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))
 
+def get_arch_info(a):
+    return (a.need_effective_addr, copy_ctypes_list(a.operands[: a.op_count]))