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fix Python build failure
1 parent 6e3587d commit f99aa52

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7 files changed

+3187
-425
lines changed

7 files changed

+3187
-425
lines changed

‎bindings/python/capstone/__init__.py‎

Lines changed: 104 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,56 @@
106106
'CS_MODE_BPF_EXTENDED',
107107
'CS_MODE_RISCV32',
108108
'CS_MODE_RISCV64',
109-
'CS_MODE_RISCVC',
109+
'CS_MODE_RISCV_C',
110+
'CS_MODE_RISCV_FD',
111+
'CS_MODE_RISCV_F',
112+
'CS_MODE_RISCV_D',
113+
'CS_MODE_RISCV_V',
114+
'CS_MODE_RISCV_ZFINX',
115+
'CS_MODE_RISCV_ZDINX',
116+
'CS_MODE_RISCV_ZHINX',
117+
'CS_MODE_RISCV_ZHINXMIN',
118+
'CS_MODE_RISCV_ZCMP_ZCMT_ZCE',
119+
'CS_MODE_RISCV_ZCE',
120+
'CS_MODE_RISCV_ZCMP',
121+
'CS_MODE_RISCV_ZCMT',
122+
'CS_MODE_RISCV_ZICFISS',
123+
'CS_MODE_RISCV_EXPERIMENTAL_ZICFISS',
124+
'CS_MODE_RISCV_E',
125+
'CS_MODE_RISCV_A',
126+
'CS_MODE_RISCV_COREV',
127+
'CS_MODE_RISCV_XCVALU',
128+
'CS_MODE_RISCV_XCVBI',
129+
'CS_MODE_RISCV_XCVBITMANIP',
130+
'CS_MODE_RISCV_XCVELW',
131+
'CS_MODE_RISCV_XCVMAC',
132+
'CS_MODE_RISCV_XCVMEM',
133+
'CS_MODE_RISCV_XCVSIMD',
134+
'CS_MODE_RISCV_THEAD',
135+
'CS_MODE_RISCV_XTHEADBA',
136+
'CS_MODE_RISCV_XTHEADBS',
137+
'CS_MODE_RISCV_XTHEADCMO',
138+
'CS_MODE_RISCV_XTHEADCONDMOV',
139+
'CS_MODE_RISCV_XTHEADFMEMIDX',
140+
'CS_MODE_RISCV_XTHEADMAC',
141+
'CS_MODE_RISCV_XTHEADMEMIDX',
142+
'CS_MODE_RISCV_XTHEADMEMPAIR',
143+
'CS_MODE_RISCV_XTHEADSYNC',
144+
'CS_MODE_RISCV_XTHEADVDOT',
145+
'CS_MODE_RISCV_SIFIVE',
146+
'CS_MODE_RISCV_XSFVCP',
147+
'CS_MODE_RISCV_XSFVFNRCLIPXFQF',
148+
'CS_MODE_RISCV_XSFVFWMACCQQQ',
149+
'CS_MODE_RISCV_XSFVQMACCDOD',
150+
'CS_MODE_RISCV_XSFVQMACCQOQ',
151+
'CS_MODE_RISCV_BITMANIP',
152+
'CS_MODE_RISCV_ZBA',
153+
'CS_MODE_RISCV_ZBB',
154+
'CS_MODE_RISCV_ZBC',
155+
'CS_MODE_RISCV_ZBKB',
156+
'CS_MODE_RISCV_ZBKC',
157+
'CS_MODE_RISCV_ZBKX',
158+
'CS_MODE_RISCV_ZBS',
110159
'CS_MODE_MOS65XX_6502',
111160
'CS_MODE_MOS65XX_65C02',
112161
'CS_MODE_MOS65XX_W65C02',
@@ -159,6 +208,7 @@
159208
'CS_OPT_SYNTAX_MOTOROLA',
160209
'CS_OPT_SYNTAX_CS_REG_ALIAS',
161210
'CS_OPT_SYNTAX_NO_DOLLAR',
211+
'CS_OPT_SYNTAX_NO_ALIAS_TEXT',
162212

163213
'CS_OPT_DETAIL',
164214
'CS_OPT_DETAIL_REAL',
@@ -332,7 +382,7 @@
332382
CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support
333383
CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support
334384
CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support
335-
CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
385+
CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
336386
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1
337387
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200
338388
CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops
@@ -353,7 +403,56 @@
353403
CS_MODE_BPF_EXTENDED = (1 << 0) # Extended BPF mode
354404
CS_MODE_RISCV32 = (1 << 0) # RISCV32 mode
355405
CS_MODE_RISCV64 = (1 << 1) # RISCV64 mode
356-
CS_MODE_RISCVC = (1 << 2) # RISCV compressed mode
406+
CS_MODE_RISCV_C = 1 << 2 # RISCV compressed instructure mode
407+
CS_MODE_RISCV_FD = 1 << 3
408+
CS_MODE_RISCV_F = CS_MODE_RISCV_FD
409+
CS_MODE_RISCV_D = CS_MODE_RISCV_FD
410+
CS_MODE_RISCV_V = 1 << 4
411+
CS_MODE_RISCV_ZFINX = 1 << 5
412+
CS_MODE_RISCV_ZDINX = CS_MODE_RISCV_ZFINX
413+
CS_MODE_RISCV_ZHINX = CS_MODE_RISCV_ZFINX
414+
CS_MODE_RISCV_ZHINXMIN = CS_MODE_RISCV_ZFINX
415+
CS_MODE_RISCV_ZCMP_ZCMT_ZCE = 1 << 6
416+
CS_MODE_RISCV_ZCE = CS_MODE_RISCV_ZCMP_ZCMT_ZCE
417+
CS_MODE_RISCV_ZCMP =CS_MODE_RISCV_ZCMP_ZCMT_ZCE
418+
CS_MODE_RISCV_ZCMT = CS_MODE_RISCV_ZCMP_ZCMT_ZCE
419+
CS_MODE_RISCV_ZICFISS = 1 << 7
420+
CS_MODE_RISCV_EXPERIMENTAL_ZICFISS = CS_MODE_RISCV_ZICFISS
421+
CS_MODE_RISCV_E = 1 << 8
422+
CS_MODE_RISCV_A = 1 << 9
423+
CS_MODE_RISCV_COREV = 1 << 10
424+
CS_MODE_RISCV_XCVALU = CS_MODE_RISCV_COREV
425+
CS_MODE_RISCV_XCVBI = CS_MODE_RISCV_COREV
426+
CS_MODE_RISCV_XCVBITMANIP = CS_MODE_RISCV_COREV
427+
CS_MODE_RISCV_XCVELW = CS_MODE_RISCV_COREV
428+
CS_MODE_RISCV_XCVMAC = CS_MODE_RISCV_COREV
429+
CS_MODE_RISCV_XCVMEM = CS_MODE_RISCV_COREV
430+
CS_MODE_RISCV_XCVSIMD = CS_MODE_RISCV_COREV
431+
CS_MODE_RISCV_THEAD = 1 << 11
432+
CS_MODE_RISCV_XTHEADBA = CS_MODE_RISCV_THEAD
433+
CS_MODE_RISCV_XTHEADBS = CS_MODE_RISCV_THEAD
434+
CS_MODE_RISCV_XTHEADCMO = CS_MODE_RISCV_THEAD
435+
CS_MODE_RISCV_XTHEADCONDMOV = CS_MODE_RISCV_THEAD
436+
CS_MODE_RISCV_XTHEADFMEMIDX = CS_MODE_RISCV_THEAD
437+
CS_MODE_RISCV_XTHEADMAC = CS_MODE_RISCV_THEAD
438+
CS_MODE_RISCV_XTHEADMEMIDX = CS_MODE_RISCV_THEAD
439+
CS_MODE_RISCV_XTHEADMEMPAIR = CS_MODE_RISCV_THEAD
440+
CS_MODE_RISCV_XTHEADSYNC = CS_MODE_RISCV_THEAD
441+
CS_MODE_RISCV_XTHEADVDOT = CS_MODE_RISCV_THEAD
442+
CS_MODE_RISCV_SIFIVE = 1 << 12
443+
CS_MODE_RISCV_XSFVCP = CS_MODE_RISCV_SIFIVE
444+
CS_MODE_RISCV_XSFVFNRCLIPXFQF = CS_MODE_RISCV_SIFIVE
445+
CS_MODE_RISCV_XSFVFWMACCQQQ = CS_MODE_RISCV_SIFIVE
446+
CS_MODE_RISCV_XSFVQMACCDOD = CS_MODE_RISCV_SIFIVE
447+
CS_MODE_RISCV_XSFVQMACCQOQ = CS_MODE_RISCV_SIFIVE
448+
CS_MODE_RISCV_BITMANIP = 1 << 13
449+
CS_MODE_RISCV_ZBA = 1 << 14
450+
CS_MODE_RISCV_ZBB = 1 << 15
451+
CS_MODE_RISCV_ZBC = 1 << 16
452+
CS_MODE_RISCV_ZBKB = 1 << 17
453+
CS_MODE_RISCV_ZBKC = 1 << 18
454+
CS_MODE_RISCV_ZBKX = 1 << 19
455+
CS_MODE_RISCV_ZBS = 1 << 20
357456
CS_MODE_MOS65XX_6502 = (1 << 1) # MOS65XXX MOS 6502
358457
CS_MODE_MOS65XX_65C02 = (1 << 2) # MOS65XXX WDC 65c02
359458
CS_MODE_MOS65XX_W65C02 = (1 << 3) # MOS65XXX WDC W65c02
@@ -461,6 +560,7 @@
461560
CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
462561
CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers.
463562
CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips, LoongArch registers.
563+
CS_OPT_SYNTAX_NO_ALIAS_TEXT = (1 << 10) # Does not print an instruction's alias test if the instruction is an alias
464564
CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias.
465565

466566
# Capstone error type
@@ -1468,7 +1568,7 @@ def debug():
14681568
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
14691569
'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
14701570
'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
1471-
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
1571+
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
14721572
'arc': CS_ARCH_ARC
14731573
}
14741574

‎bindings/python/capstone/riscv.py‎

Lines changed: 27 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,34 +1,44 @@
11
# Capstone Python bindings, by Nguyen Anh Quynnh <[email protected]>
22

33
import ctypes
4+
45
from . import copy_ctypes_list
56
from .riscv_const import *
67

8+
79
# define the API
810
class RISCVOpMem(ctypes.Structure):
911
_fields_ = (
10-
('base', ctypes.c_uint),
11-
('disp', ctypes.c_int64),
12+
("base", ctypes.c_uint),
13+
("disp", ctypes.c_int64),
1214
)
1315

16+
1417
class RISCVOpValue(ctypes.Union):
1518
_fields_ = (
16-
('reg', ctypes.c_uint),
17-
('imm', ctypes.c_int64),
18-
('mem', RISCVOpMem),
19+
("reg", ctypes.c_uint),
20+
("imm", ctypes.c_int64),
21+
("dimm", ctypes.c_double),
22+
("mem", RISCVOpMem),
23+
("csr", ctypes.c_uint16),
1924
)
2025

26+
2127
class RISCVOp(ctypes.Structure):
2228
_fields_ = (
23-
('type', ctypes.c_uint),
24-
('value', RISCVOpValue),
25-
('access', ctypes.c_uint),
29+
("type", ctypes.c_uint),
30+
("value", RISCVOpValue),
31+
("access", ctypes.c_uint),
2632
)
2733

2834
@property
2935
def imm(self):
3036
return self.value.imm
3137

38+
@property
39+
def dimm(self):
40+
return self.value.dimm
41+
3242
@property
3343
def reg(self):
3444
return self.value.reg
@@ -37,14 +47,18 @@ def reg(self):
3747
def mem(self):
3848
return self.value.mem
3949

50+
@property
51+
def csr(self):
52+
return self.value.csr
53+
4054

4155
class CsRISCV(ctypes.Structure):
4256
_fields_ = (
43-
('need_effective_addr', ctypes.c_bool),
44-
('op_count', ctypes.c_uint8),
45-
('operands', RISCVOp * 8),
57+
("need_effective_addr", ctypes.c_bool),
58+
("op_count", ctypes.c_uint8),
59+
("operands", RISCVOp * 8),
4660
)
4761

48-
def get_arch_info(a):
49-
return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))
5062

63+
def get_arch_info(a):
64+
return (a.need_effective_addr, copy_ctypes_list(a.operands[: a.op_count]))

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