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review if the uvm driver is correct with changing the clock polarity and phase  #5

@kassemmkk

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@kassemmkk

Originally created by @M0stafaRady on 2024-05-14T08:38:11Z\n\nI implemented the driver and the monitor to drive the byte with which would be read correctly with the current RTL but I'm not sure of that is the correct protocol for phase and polarity shifting. If is implemented incorrectly in the RTL, the uvm verification will not detect it.

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