From e1f105f29edb9fbf3b59d3e203637b988e85bef2 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 13 Oct 2024 13:12:35 +0300 Subject: [PATCH 1/4] fix pwm_actions_test --- verify/uvm-python/test_lib.py | 8 +++ .../uvm-python/tmr32_agent/tmr32_monitor.py | 17 +++++- .../tmr32_seq_lib/pwm_actions_seq.py | 7 ++- .../uvm-python/tmr32_seq_lib/timer_config.py | 56 ++++++++++++++++--- 4 files changed, 77 insertions(+), 11 deletions(-) diff --git a/verify/uvm-python/test_lib.py b/verify/uvm-python/test_lib.py index 1a006b8..844f415 100644 --- a/verify/uvm-python/test_lib.py +++ b/verify/uvm-python/test_lib.py @@ -121,10 +121,18 @@ def __init__(self, name="pwm_test", parent=None): super().__init__(name, parent) self.tag = name + def end_of_elaboration_phase(self, phase): + super().end_of_elaboration_phase(phase) + self.update_min_checkers(22) + async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED") bus_seq = pwm_actions_seq("pwm_actions_seq") + bus_seq.tr_received0_event = self.top_env.ip_env.ip_agent.monitor.tr_received0_event + bus_seq.tr_start0_event = self.top_env.ip_env.ip_agent.monitor.tr_start0_event + bus_seq.tr_received1_event = self.top_env.ip_env.ip_agent.monitor.tr_received1_event + bus_seq.tr_start1_event = self.top_env.ip_env.ip_agent.monitor.tr_start1_event await bus_seq.start(self.bus_sqr) phase.drop_objection(self, f"{self.__class__.__name__} drop objection") diff --git a/verify/uvm-python/tmr32_agent/tmr32_monitor.py b/verify/uvm-python/tmr32_agent/tmr32_monitor.py index 1ba02da..3e206a5 100644 --- a/verify/uvm-python/tmr32_agent/tmr32_monitor.py +++ b/verify/uvm-python/tmr32_agent/tmr32_monitor.py @@ -22,6 +22,10 @@ class tmr32_monitor(ip_monitor): def __init__(self, name="tmr32_monitor", parent=None): super().__init__(name, parent) + self.tr_received0_event = Event("tr_received0") + self.tr_start0_event = Event("tr_start0") + self.tr_received1_event = Event("tr_received1") + self.tr_start1_event = Event("tr_start1") async def run_phase(self, phase): while True: @@ -36,9 +40,14 @@ async def run_phase(self, phase): sample_pwm1.kill() async def sample_pwm(self, signal, source): - for _ in range(3): - await Edge(signal) while True: + if source == tmr32_pwm_item.pwm0: + await self.tr_start0_event.wait() + self.tr_start0_event.clear() + else: + await self.tr_start1_event.wait() + self.tr_start1_event.clear() + uvm_info(self.tag, f"sample_pwm {source} started", UVM_LOW) await Edge(signal) old_val = signal.value count = 0 @@ -89,6 +98,10 @@ async def sample_pwm(self, signal, source): tr.source = source tr.pattern = extracted_pattern self.monitor_port.write(tr) + if source == tmr32_pwm_item.pwm0: + self.tr_received0_event.set() + else: + self.tr_received1_event.set() uvm_info( self.tag, f"sampled {source} transaction: " + tr.convert2string(), diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py index d0a90fd..6d391c2 100644 --- a/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py +++ b/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py @@ -18,14 +18,16 @@ async def body(self): # get register names/address conversion dict await super().body() await self.pwm0_seq() - await self.pwm_delay() + await self.wait_pwm0_deteced() await self.send_reset() await self.pwm1_seq() + await self.wait_pwm1_deteced() await self.pwm_delay() for _ in range(10): await self.send_reset() await self.pwm_seq() - await self.pwm_delay() + await self.wait_pwm_deteced() + # await self.pwm_delay() async def pwm0_seq(self): await self.config_regs() @@ -46,6 +48,7 @@ async def pwm_seq(self): ) async def config_regs(self): + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.set_timer_pr() await self.set_timer_mode(is_periodic=True) await self.config_timer_regs() diff --git a/verify/uvm-python/tmr32_seq_lib/timer_config.py b/verify/uvm-python/tmr32_seq_lib/timer_config.py index c725f89..10dd266 100644 --- a/verify/uvm-python/tmr32_seq_lib/timer_config.py +++ b/verify/uvm-python/tmr32_seq_lib/timer_config.py @@ -4,10 +4,10 @@ from EF_UVM.bus_env.bus_item import bus_item from uvm.base.uvm_config_db import UVMConfigDb from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base -from cocotb.triggers import Timer +from cocotb.triggers import Timer, Combine from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do import random - +import cocotb class timer_config(bus_seq_base): @@ -19,6 +19,21 @@ async def body(self): await super().body() await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) + async def wait_pwm0_deteced(self): + self.tr_start0_event.set() + await self.tr_received0_event.wait() + self.tr_received0_event.clear() + + async def wait_pwm1_deteced(self): + self.tr_start1_event.set() + await self.tr_received1_event.wait() + self.tr_received1_event.clear() + + async def wait_pwm_deteced(self): + pwm0 = await cocotb.start(self.wait_pwm0_deteced()) + pwm1 = await cocotb.start(self.wait_pwm1_deteced()) + await Combine(pwm0, pwm1) + async def read_timer_val(self): await self.send_req(is_write=False, reg="TMR") @@ -64,14 +79,40 @@ async def set_pwm_actions(self): await self.send_req( is_write=True, reg="PWM0CFG", - data_condition=lambda data: data & 0b11 in [0b10, 0b01], + data_condition=lambda data: data & 0xFFF in [self.generate_pwm_action()], ) # should start with high or low not realistic to start with no change or invert await self.send_req( is_write=True, reg="PWM1CFG", - data_condition=lambda data: data & 0b11 in [0b10, 0b01], + data_condition=lambda data: data & 0xFFF in [self.generate_pwm_action()], ) - + + def generate_pwm_action(self): + E0 = random.randint(1, 0b11) # should start with high or low not realistic to start with no change or invert + E1 = random.randint(0, 0b100) + E2 = random.randint(0, 0b100) + E3 = random.randint(0, 0b100) # better to not be not action + E4 = random.randint(0, 0b100) + E5 = random.randint(0, 0b100) + + seq_vals = [1, 2, 3] + counter = 0 + for i in [E0, E1, E2, E3]: + if i in seq_vals: + counter += 1 + seq_vals.remove(i) + if counter < 2: + return self.generate_pwm_action() + seq_vals = [1, 2, 3] + counter = 0 + for i in [E3, E4, E5]: + if i in seq_vals: + counter += 1 + seq_vals.remove(i) + if counter < 2: + return self.generate_pwm_action() + return int(E0 | E1 << 2 | E2 << 4 | E3 << 6 | E4 << 8 | E5 << 10) + async def set_timer_mode(self, is_periodic=None, dir=None): if is_periodic is None and dir is None: await self.send_req( @@ -85,13 +126,13 @@ async def set_timer_mode(self, is_periodic=None, dir=None): await self.send_req( is_write=True, reg="CFG", - data_condition=lambda data: data >> 2 == is_periodic, + data_condition=lambda data: data >> 2 == is_periodic and data & 0b11 != 0b0, ) else: await self.send_req( is_write=True, reg="CFG", - data_condition=lambda data: data >> 2 == is_periodic + data_condition=lambda data: data >> 2 == is_periodic and data & 0b11 != 0b0 and data & 0b11 == dir, ) @@ -108,6 +149,7 @@ async def stop_timer(self): ) async def config_timer(self): + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.set_timer_pr() await self.set_timer_mode() await self.config_timer_regs() From 595133685ab9033196dd5f38166b0cc3712a43a4 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 13 Oct 2024 13:26:51 +0300 Subject: [PATCH 2/4] fix pwm_pr_test and pwm_tmr_seq --- verify/uvm-python/test_lib.py | 16 ++++++++++++++++ verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py | 3 ++- verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py | 3 ++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/verify/uvm-python/test_lib.py b/verify/uvm-python/test_lib.py index 844f415..83b0f8e 100644 --- a/verify/uvm-python/test_lib.py +++ b/verify/uvm-python/test_lib.py @@ -145,10 +145,18 @@ def __init__(self, name="pwm_test", parent=None): super().__init__(name, parent) self.tag = name + def end_of_elaboration_phase(self, phase): + super().end_of_elaboration_phase(phase) + self.update_min_checkers(14) + async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED") bus_seq = pwm_pr_seq("pwm_pr_seq") + bus_seq.tr_received0_event = self.top_env.ip_env.ip_agent.monitor.tr_received0_event + bus_seq.tr_start0_event = self.top_env.ip_env.ip_agent.monitor.tr_start0_event + bus_seq.tr_received1_event = self.top_env.ip_env.ip_agent.monitor.tr_received1_event + bus_seq.tr_start1_event = self.top_env.ip_env.ip_agent.monitor.tr_start1_event await bus_seq.start(self.bus_sqr) phase.drop_objection(self, f"{self.__class__.__name__} drop objection") @@ -161,10 +169,18 @@ def __init__(self, name="pwm_tmr_test", parent=None): super().__init__(name, parent) self.tag = name + def end_of_elaboration_phase(self, phase): + super().end_of_elaboration_phase(phase) + self.update_min_checkers(14) + async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED") bus_seq = pwm_tmr_seq("pwm_tmr_seq") + bus_seq.tr_received0_event = self.top_env.ip_env.ip_agent.monitor.tr_received0_event + bus_seq.tr_start0_event = self.top_env.ip_env.ip_agent.monitor.tr_start0_event + bus_seq.tr_received1_event = self.top_env.ip_env.ip_agent.monitor.tr_received1_event + bus_seq.tr_start1_event = self.top_env.ip_env.ip_agent.monitor.tr_start1_event await bus_seq.start(self.bus_sqr) phase.drop_objection(self, f"{self.__class__.__name__} drop objection") diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py index 66e8d14..a79fa71 100644 --- a/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py +++ b/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py @@ -28,7 +28,7 @@ async def body(self): for pr_range in pr_ranges: await self.send_reset() await self.pwm_seq(pr_range) - await self.pwm_delay(largest_pr=pr_range[1]) + await self.wait_pwm_deteced() counter += 1 if counter == 7: break @@ -51,6 +51,7 @@ async def pwm_seq(self, pr_range): ) async def config_regs(self, pr_range): + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.set_timer_pr(pr_range) await self.set_timer_mode(is_periodic=True) await self.config_timer_regs() diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py index da84c93..7316f51 100644 --- a/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py +++ b/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py @@ -27,7 +27,7 @@ async def body(self): for reload_val in reload_vals: await self.send_reset() await self.pwm_seq(reload_val) - await self.pwm_delay(relaod_large_val=reload_val) + await self.wait_pwm_deteced() counter += 1 if counter == 7: break @@ -50,6 +50,7 @@ async def pwm_seq(self, largest_reload): ) async def config_regs(self, largest_reload): + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.set_timer_pr() await self.set_timer_mode(is_periodic=True) await self.config_timer_regs(largest_reload) From 75cfe1c838711365f9dcbc6d9f3997ae99423aa8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 13 Oct 2024 13:34:03 +0300 Subject: [PATCH 3/4] correct number of minimum checkers --- verify/uvm-python/test_lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verify/uvm-python/test_lib.py b/verify/uvm-python/test_lib.py index 83b0f8e..cc8559d 100644 --- a/verify/uvm-python/test_lib.py +++ b/verify/uvm-python/test_lib.py @@ -171,7 +171,7 @@ def __init__(self, name="pwm_tmr_test", parent=None): def end_of_elaboration_phase(self, phase): super().end_of_elaboration_phase(phase) - self.update_min_checkers(14) + self.update_min_checkers(12) async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) From eebfbbc22c3983703ded36a6a9b3e30edd74952f Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 13 Oct 2024 13:59:36 +0300 Subject: [PATCH 4/4] correct number of minimum checkers --- verify/uvm-python/test_lib.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verify/uvm-python/test_lib.py b/verify/uvm-python/test_lib.py index cc8559d..11565f2 100644 --- a/verify/uvm-python/test_lib.py +++ b/verify/uvm-python/test_lib.py @@ -147,7 +147,7 @@ def __init__(self, name="pwm_test", parent=None): def end_of_elaboration_phase(self, phase): super().end_of_elaboration_phase(phase) - self.update_min_checkers(14) + self.update_min_checkers(6) async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) @@ -171,7 +171,7 @@ def __init__(self, name="pwm_tmr_test", parent=None): def end_of_elaboration_phase(self, phase): super().end_of_elaboration_phase(phase) - self.update_min_checkers(12) + self.update_min_checkers(6) async def main_phase(self, phase): uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)