From 2c71e6c4124a59666cd13dc4a4ea0f78479092db Mon Sep 17 00:00:00 2001 From: ChipFoundry Automation Date: Tue, 12 May 2026 08:19:55 +0000 Subject: [PATCH] chipfoundry: remote precheck results (1a881034-ef1a-4221-8495-19fbad0c016d) --- .cf/project.json | 869 +++ .../12_MAY_2026___07_45_39/logs/LVS_check.log | 3508 ++++++++++++ .../12_MAY_2026___07_45_39/logs/OEB_check.log | 2361 +++++++++ .../12_MAY_2026___07_45_39/logs/cvc.log | 651 +++ .../12_MAY_2026___07_45_39/logs/cvc.oeb.log | 2580 +++++++++ .../12_MAY_2026___07_45_39/logs/ext.log | 717 +++ .../12_MAY_2026___07_45_39/logs/gds.info | 1 + .../12_MAY_2026___07_45_39/logs/hier.log | 9 + .../logs/klayout_beol_check.log | 1197 +++++ .../logs/klayout_beol_check.total | 1 + .../logs/klayout_feol_check.log | 1397 +++++ .../logs/klayout_feol_check.total | 1 + .../logs/klayout_met_min_ca_density_check.log | 79 + .../klayout_met_min_ca_density_check.total | 1 + .../logs/klayout_offgrid_check.log | 773 +++ .../logs/klayout_offgrid_check.total | 1 + ...bel_purposes_overlapping_drawing_check.log | 29 + ...l_purposes_overlapping_drawing_check.total | 1 + .../logs/klayout_zeroarea_check.log | 6 + .../logs/klayout_zeroarea_check.total | 1 + .../12_MAY_2026___07_45_39/logs/lvs.log | 2549 +++++++++ .../12_MAY_2026___07_45_39/logs/pdks.info | 2 + .../12_MAY_2026___07_45_39/logs/precheck.log | 50 + .../logs/spike_check.log | 14 + .../12_MAY_2026___07_45_39/logs/tools.info | 2 + .../12_MAY_2026___07_45_39/logs/xor_check.log | 378 ++ .../logs/xor_check.total | 1 + .../outputs/reports/cvc.error.gz | Bin 0 -> 319 bytes .../outputs/reports/cvc.oeb.report | 84 + .../outputs/reports/hier.csv | 1 + .../outputs/reports/klayout_beol_check.xml | 574 ++ .../outputs/reports/klayout_feol_check.xml | 622 +++ .../klayout_met_min_ca_density_check.xml | 22 + .../outputs/reports/klayout_offgrid_check.xml | 472 ++ ...bel_purposes_overlapping_drawing_check.xml | 22 + .../reports/klayout_zeroarea_check.xml | 22 + .../outputs/reports/lvs.report | 4707 +++++++++++++++++ .../outputs/reports/lvs.unflattened | 0 .../outputs/reports/spike_check.xml | 15 + .../reports/user_project_wrapper.gds.spice.gz | Bin 0 -> 3145996 bytes .../outputs/user_project_wrapper.xor.gds | Bin 0 -> 106 bytes .../user_project_wrapper_empty_erased.gds | Bin 0 -> 51190 bytes .../outputs/user_project_wrapper_erased.gds | Bin 0 -> 51190 bytes .../user_project_wrapper_no_zero_areas.gds | Bin 0 -> 61858094 bytes .../tmp_oeb/cvc.oeb.debug.gz | Bin 0 -> 101 bytes .../tmp_oeb/cvc.oeb.error.gz | Bin 0 -> 319 bytes .../tmp_oeb/cvc.oeb.log | 2580 +++++++++ .../tmp_oeb/cvc.oeb.report | 84 + .../tmp_oeb/cvc.oeb.script | 183 + .../tmp_oeb/cvc.power.user_project_wrapper | 18 + .../12_MAY_2026___07_45_39/tmp_oeb/cvcrc | 35 + .../12_MAY_2026___07_45_39/tmp_oeb/cvcrc.oeb | 35 + .../tmp_oeb/user_defines.v | 92 + .../tmp_oeb/user_project_wrapper.cdl.gz | Bin 0 -> 3146000 bytes 54 files changed, 26747 insertions(+) create mode 100644 .cf/project.json create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/LVS_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/OEB_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/cvc.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/cvc.oeb.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/ext.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/gds.info create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/hier.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/lvs.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/pdks.info create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/precheck.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/spike_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/tools.info create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/xor_check.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/logs/xor_check.total create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.error.gz create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.oeb.report create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/hier.csv create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_zeroarea_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.report create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.unflattened create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/reports/user_project_wrapper.gds.spice.gz create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper.xor.gds create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_empty_erased.gds create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_erased.gds create mode 100644 precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_no_zero_areas.gds create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.debug.gz create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.error.gz create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.report create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.script create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.power.user_project_wrapper create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvcrc create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvcrc.oeb create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_defines.v create mode 100644 precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz diff --git a/.cf/project.json b/.cf/project.json new file mode 100644 index 00000000..251dbb7c --- /dev/null +++ b/.cf/project.json @@ -0,0 +1,869 @@ +{ + "precheck": { + "version": "1.3.3", + "timestamp": "2026-05-12T08:19:51.933250+00:00", + "pdk": "sky130A", + "passed": false, + "checks": { + "topcell_check": { + "status": "pass", + "duration_s": 1.95 + }, + "gpio_defines": { + "status": "fail", + "duration_s": 1.15, + "details": "GPIO defines: Invalid directives (33): USER_CONFIG_GPIO_5_INIT=13'hXXXX USER_CONFIG_GPIO_6_INIT=13'hXXXX USER_CONFIG_GPIO_7_INIT=13'hXXXX USER_CONFIG_GPIO_8_INIT=13'hXXXX USER_CONFIG_GPIO_9_INIT=13'hXXXX USER_CONFIG_GPIO_10_INIT=13'hXXXX USER_CONFIG_GPIO_11_INIT=13'hXXXX USER_CONFIG_GPIO_12_INIT=13'hXXXX USER_CONFIG_GPIO_13_INIT=13'hXXXX USER_CONFIG_GPIO_25_INIT=13'hXXXX USER_CONFIG_GPIO_26_INIT=13'hXXXX USER_CONFIG_GPIO_27_INIT=13'hXXXX USER_CONFIG_GPIO_28_INIT=13'hXXXX USER_CONFIG_GPIO_29_INIT=13'hXXXX USER_CONFIG_GPIO_30_INIT=13'hXXXX USER_CONFIG_GPIO_31_INIT=13'hXXXX USER_CONFIG_GPIO_32_INIT=13'hXXXX USER_CONFIG_GPIO_33_INIT=13'hXXXX USER_CONFIG_GPIO_34_INIT=13'hXXXX USER_CONFIG_GPIO_35_INIT=13'hXXXX USER_CONFIG_GPIO_36_INIT=13'hXXXX USER_CONFIG_GPIO_37_INIT=13'hXXXX USER_CONFIG_GPIO_14_INIT=13'hXXXX USER_CONFIG_GPIO_15_INIT=13'hXXXX USER_CONFIG_GPIO_16_INIT=13'hXXXX USER_CONFIG_GPIO_17_INIT=13'hXXXX USER_CONFIG_GPIO_18_INIT=13'hXXXX USER_CONFIG_GPIO_19_INIT=13'hXXXX USER_CONFIG_GPIO_20_INIT=13'hXXXX USER_CONFIG_GPIO_21_INIT=13'hXXXX USER_CONFIG_GPIO_22_INIT=13'hXXXX USER_CONFIG_GPIO_23_INIT=13'hXXXX USER_CONFIG_GPIO_24_INIT=13'hXXXX" + }, + "xor": { + "status": "pass", + "duration_s": 17.34 + }, + "klayout_feol": { + "status": "pass", + "duration_s": 288.31 + }, + "klayout_beol": { + "status": "pass", + "duration_s": 735.19 + }, + "klayout_offgrid": { + "status": "pass", + "duration_s": 184.92 + }, + "klayout_met_min_ca_density": { + "status": "pass", + "duration_s": 53.09 + }, + "klayout_pin_label_purposes_overlapping_drawing": { + "status": "pass", + "duration_s": 33.4 + }, + "klayout_zeroarea": { + "status": "pass", + "duration_s": 9.45 + }, + "spike_check": { + "status": "pass", + "duration_s": 6.62 + }, + "illegal_cellname_check": { + "status": "pass", + "duration_s": 1.96 + }, + "lvs": { + "status": "pass", + "duration_s": 710.51 + }, + "oeb": { + "status": "fail", + "duration_s": 7.94, + "details": "33 errors, 10 warnings across 38 GPIOs", + "report": { + "report_relpath": "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.oeb.report", + "design_type": "caravel", + "gpios": [ + { + "gpio": 0, + "user_index": 0, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "FIXED_STD_INPUT_NOPULL", + "resolved_mode": "FIXED_STD_INPUT_NOPULL", + "warning_count": 2, + "error_count": 0 + }, + { + "gpio": 1, + "user_index": 1, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "FIXED_STD_INPUT_NOPULL", + "resolved_mode": "FIXED_STD_INPUT_NOPULL", + "warning_count": 2, + "error_count": 0 + }, + { + "gpio": 2, + "user_index": 2, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "FIXED_STD_INPUT_NOPULL", + "resolved_mode": "FIXED_STD_INPUT_NOPULL", + "warning_count": 2, + "error_count": 0 + }, + { + "gpio": 3, + "user_index": 3, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "FIXED_STD_INPUT_PULLUP", + "resolved_mode": "FIXED_STD_INPUT_PULLUP", + "warning_count": 2, + "error_count": 0 + }, + { + "gpio": 4, + "user_index": 4, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "FIXED_STD_INPUT_NOPULL", + "resolved_mode": "FIXED_STD_INPUT_NOPULL", + "warning_count": 2, + "error_count": 0 + }, + { + "gpio": 5, + "user_index": 5, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 6, + "user_index": 6, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 7, + "user_index": 7, + "analog_index": 0, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 8, + "user_index": 8, + "analog_index": 1, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 9, + "user_index": 9, + "analog_index": 2, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 10, + "user_index": 10, + "analog_index": 3, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 11, + "user_index": 11, + "analog_index": 4, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 12, + "user_index": 12, + "analog_index": 5, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 13, + "user_index": 13, + "analog_index": 6, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 14, + "user_index": 14, + "analog_index": 7, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 15, + "user_index": 15, + "analog_index": 8, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 16, + "user_index": 16, + "analog_index": 9, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 17, + "user_index": 17, + "analog_index": 10, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 18, + "user_index": 18, + "analog_index": 11, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 19, + "user_index": 19, + "analog_index": 12, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 20, + "user_index": 20, + "analog_index": 13, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 21, + "user_index": 21, + "analog_index": 14, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 22, + "user_index": 22, + "analog_index": 15, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 23, + "user_index": 23, + "analog_index": 16, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 24, + "user_index": 24, + "analog_index": 17, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 25, + "user_index": 25, + "analog_index": 18, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 26, + "user_index": 26, + "analog_index": 19, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 27, + "user_index": 27, + "analog_index": 20, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 28, + "user_index": 28, + "analog_index": 21, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 29, + "user_index": 29, + "analog_index": 22, + "in": null, + "out": null, + "analog": null, + "oeb_min": null, + "oeb_sim": null, + "oeb_max": null, + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 30, + "user_index": 30, + "analog_index": 23, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 31, + "user_index": 31, + "analog_index": 24, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 32, + "user_index": 32, + "analog_index": 25, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 33, + "user_index": 33, + "analog_index": 26, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 34, + "user_index": 34, + "analog_index": 27, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 35, + "user_index": 35, + "analog_index": 28, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 36, + "user_index": 36, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + }, + { + "gpio": 37, + "user_index": 37, + "analog_index": null, + "in": null, + "out": "2", + "analog": null, + "oeb_min": "vssd*", + "oeb_sim": null, + "oeb_max": "vccd*", + "configuration": "INVALID missing mode", + "resolved_mode": "INVALID missing mode", + "warning_count": 0, + "error_count": 1 + } + ], + "messages": [ + { + "gpio": 0, + "severity": "warning", + "text": "user output connection to fixed input gpio - firmware override required" + }, + { + "gpio": 0, + "severity": "warning", + "text": "user oeb connection to fixed input gpio - firmware override required" + }, + { + "gpio": 1, + "severity": "warning", + "text": "user output connection to fixed input gpio - firmware override required" + }, + { + "gpio": 1, + "severity": "warning", + "text": "user oeb connection to fixed input gpio - firmware override required" + }, + { + "gpio": 2, + "severity": "warning", + "text": "user output connection to fixed input gpio - firmware override required" + }, + { + "gpio": 2, + "severity": "warning", + "text": "user oeb connection to fixed input gpio - firmware override required" + }, + { + "gpio": 3, + "severity": "warning", + "text": "user output connection to fixed input gpio - firmware override required" + }, + { + "gpio": 3, + "severity": "warning", + "text": "user oeb connection to fixed input gpio - firmware override required" + }, + { + "gpio": 4, + "severity": "warning", + "text": "user output connection to fixed input gpio - firmware override required" + }, + { + "gpio": 4, + "severity": "warning", + "text": "user oeb connection to fixed input gpio - firmware override required" + }, + { + "gpio": 5, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 6, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 7, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 8, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 9, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 10, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 11, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 12, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 13, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 14, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 15, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 16, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 17, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 18, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 19, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 20, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 21, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 22, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 23, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 24, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 25, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 26, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 27, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 28, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 29, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 30, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 31, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 32, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 33, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 34, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 35, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 36, + "severity": "error", + "text": "missing gpio configuration" + }, + { + "gpio": 37, + "severity": "error", + "text": "missing gpio configuration" + } + ], + "summary": { + "total": 38, + "errors": 33, + "warnings": 10, + "no_issues_banner": false + } + } + }, + "magic_drc": { + "status": "skip", + "duration_s": 0, + "reason": "optional (use --magic-drc to include)" + } + }, + "input_file_hash": "7dedb0577fede3bf2014261de4d5e78fb372daa1" + } +} diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/LVS_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/LVS_check.log new file mode 100644 index 00000000..c20f14e2 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/LVS_check.log @@ -0,0 +1,3508 @@ + +TOP SOURCE: user_project_wrapper +SOURCE FILE(S): /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_20_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_40_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_60_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_80_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +TOP LAYOUT: user_project_wrapper +LAYOUT FILE: /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +EXTRACT_FLATGLOB: +EXTRACT_ABSTRACT: *__fill_* + *__fakediode_* + *__tapvpwrvgnd_* +LVS_FLATTEN: +LVS_NOFLATTEN: +LVS_IGNORE: +WORK_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp +LOG_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs +SIGNOFF_ROOT: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports + +Running hierarchical comparison between verilog and layout... +Creating /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/verilog.cells from the following files... + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +[INFO] Changing from /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds + to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/layout.txt +Hierarchy check for user_project_wrapper passed. + +Running LVS... +TOP SOURCE: user_project_wrapper +SOURCE FILE(S): /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_20_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_40_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_60_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_80_12.spice + /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +TOP LAYOUT: user_project_wrapper +LAYOUT FILE: /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +EXTRACT_FLATGLOB: +EXTRACT_ABSTRACT: *__fill_* + *__fakediode_* + *__tapvpwrvgnd_* +LVS_FLATTEN: +LVS_NOFLATTEN: +LVS_IGNORE: +WORK_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp +LOG_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs +SIGNOFF_ROOT: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports + +Running extract... +TOP LAYOUT: user_project_wrapper +LAYOUT FILE: /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +EXTRACT_FLATGLOB: +EXTRACT_ABSTRACT: *__fill_* + *__fakediode_* + *__tapvpwrvgnd_* +WORK_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp +LOG_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs +SIGNOFF_ROOT: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports +LOG FILE: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs/ext.log +Adding subcutout style to tech file. +/opt/pdks/sky130A/libs.tech/magic/sky130A.tech: version 1.0.493 +Extracting to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext + + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design magicrc.well for technology sky130A ... +2 Magic internal units = 1 Lambda +Loading tech file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A.tech +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/abstract.tcl" from command line. +Abstracting +CIF input style is now "sky130()" +Abstracting /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "EZ_sky130_ef_sc_hd__decap_40_12". +Reading "EZ_sky130_fd_sc_hd__decap_3". +Reading "EZ_sky130_fd_sc_hd__fill_1". +Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "EZ_sky130_fd_sc_hd__fill_2". +Reading "EZ_sky130_fd_sc_hd__fill_4". +Reading "EZ_sky130_fd_sc_hd__buf_4". +Reading "EZ_sky130_fd_sc_hd__fill_8". +Reading "EZ_sky130_fd_sc_hd__diode_2". +Reading "EZ_sky130_fd_sc_hd__buf_12". +Reading "EZ_sky130_fd_sc_hd__clkbuf_8". +Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1". +Reading "EZ_sky130_fd_sc_hd__clkbuf_4". +Reading "EZ_sky130_fd_sc_hd__buf_2". +Reading "EZ_sky130_fd_sc_hd__dfxtp_1". +Reading "EZ_sky130_fd_sc_hd__mux2_1". +Reading "EZ_sky130_fd_sc_hd__dfxtp_2". +Reading "EZ_sky130_fd_sc_hd__conb_1". +Reading "EZ_sky130_fd_sc_hd__and2_4". +Reading "EZ_sky130_fd_sc_hd__and2_2". +Reading "EZ_sky130_fd_sc_hd__nand2_8". +Reading "EZ_sky130_fd_sc_hd__nor2_2". +Reading "EZ_sky130_fd_sc_hd__inv_2". +Reading "EZ_sky130_fd_sc_hd__buf_6". +Reading "EZ_sky130_fd_sc_hd__nand3b_4". +Reading "EZ_sky130_fd_sc_hd__a211o_1". +Reading "EZ_sky130_fd_sc_hd__nor2_1". +Reading "EZ_sky130_fd_sc_hd__and3_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_4". +Reading "EZ_sky130_fd_sc_hd__and2b_1". +Reading "EZ_sky130_fd_sc_hd__buf_1". +Reading "EZ_sky130_fd_sc_hd__a22o_1". +Reading "EZ_sky130_fd_sc_hd__a31o_1". +Reading "EZ_sky130_fd_sc_hd__o21a_1". +Reading "EZ_sky130_fd_sc_hd__a221o_1". +Reading "EZ_sky130_fd_sc_hd__a32o_1". +Reading "EZ_sky130_fd_sc_hd__and2_1". +Reading "EZ_sky130_fd_sc_hd__nand2_1". +Reading "EZ_sky130_fd_sc_hd__o2bb2a_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_1". +Reading "EZ_sky130_fd_sc_hd__o21ai_1". +Reading "EZ_sky130_fd_sc_hd__a32o_4". +Reading "EZ_sky130_fd_sc_hd__a21o_1". +Reading "EZ_sky130_fd_sc_hd__or3b_2". +Reading "EZ_sky130_fd_sc_hd__and2b_2". +Reading "EZ_sky130_fd_sc_hd__a31o_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_1". +Reading "EZ_sky130_fd_sc_hd__or3b_4". +Reading "EZ_sky130_fd_sc_hd__and4_1". +Reading "EZ_sky130_fd_sc_hd__a41o_4". +Reading "EZ_sky130_fd_sc_hd__and3b_4". +Reading "EZ_sky130_fd_sc_hd__buf_8". +Reading "EZ_sky130_fd_sc_hd__clkbuf_16". +Reading "EZ_sky130_fd_sc_hd__dfxtp_4". +Reading "EZ_sky130_fd_sc_hd__nor2_8". +Reading "EZ_sky130_fd_sc_hd__or2_1". +Reading "EZ_sky130_fd_sc_hd__o31a_1". +Reading "EZ_sky130_fd_sc_hd__o211a_1". +Reading "EZ_sky130_fd_sc_hd__o32a_1". +Reading "EZ_sky130_fd_sc_hd__a31oi_1". +Reading "EZ_sky130_fd_sc_hd__o31ai_1". +Reading "EZ_sky130_fd_sc_hd__o211ai_4". +Reading "EZ_sky130_fd_sc_hd__a41oi_4". +Reading "EZ_sky130_fd_sc_hd__and4_2". +Reading "EZ_sky130_fd_sc_hd__xor2_1". +Reading "EZ_sky130_fd_sc_hd__or2_2". +Reading "EZ_sky130_fd_sc_hd__nor2_4". +Reading "EZ_sky130_fd_sc_hd__or3_4". +Reading "EZ_sky130_fd_sc_hd__nand2_2". +Reading "EZ_sky130_fd_sc_hd__xnor2_1". +Reading "EZ_sky130_fd_sc_hd__and3b_1". +Reading "EZ_sky130_fd_sc_hd__a31o_2". +Reading "EZ_sky130_fd_sc_hd__a21bo_1". +Reading "EZ_sky130_fd_sc_hd__a21boi_1". +Reading "EZ_sky130_fd_sc_hd__nand2b_1". +Reading "EZ_sky130_fd_sc_hd__xnor2_2". +Reading "EZ_sky130_fd_sc_hd__nand4_2". +Reading "EZ_sky130_fd_sc_hd__a41o_1". +Reading "EZ_sky130_fd_sc_hd__and4_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_2". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses + 55000 uses + 60000 uses + 65000 uses + 70000 uses + 75000 uses + 80000 uses + 85000 uses + 90000 uses + 95000 uses + 100000 uses + 105000 uses + 110000 uses + 115000 uses + 120000 uses + 125000 uses + 130000 uses + 135000 uses + 140000 uses + 145000 uses + 150000 uses + 155000 uses + 160000 uses + 165000 uses + 170000 uses + 175000 uses + 180000 uses + 185000 uses + 190000 uses + 195000 uses + 200000 uses + 205000 uses + 210000 uses + 215000 uses + 220000 uses + 225000 uses + 230000 uses + 235000 uses + 240000 uses + 245000 uses + 250000 uses + 255000 uses + 260000 uses + 265000 uses + 270000 uses + 275000 uses + 280000 uses + 285000 uses + 290000 uses + 295000 uses + 300000 uses + 305000 uses + 310000 uses + 315000 uses + 320000 uses + 325000 uses + 330000 uses + 335000 uses + 340000 uses + 345000 uses + 350000 uses + 355000 uses + 360000 uses + 365000 uses + 370000 uses + 375000 uses + 380000 uses + 385000 uses + 390000 uses + 395000 uses + 400000 uses + 405000 uses + 410000 uses + 415000 uses + 420000 uses + 425000 uses + 430000 uses + 435000 uses + 440000 uses + 445000 uses + 450000 uses + 455000 uses + 460000 uses + 465000 uses + 470000 uses + 475000 uses + 480000 uses + 485000 uses + 490000 uses + 495000 uses + 500000 uses + 505000 uses + 510000 uses + 515000 uses + 520000 uses + 525000 uses + 530000 uses + 535000 uses + 540000 uses + 545000 uses + 550000 uses + 555000 uses +Reading "user_project_wrapper". + +TIME: read GDS: 00:00:11 + + +TIME: create subcut: 00:00:00 + +Abstracting EZ_sky130_fd_sc_hd__fill_1 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_2 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_4 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_8 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 +instance count:0 port count:3 + +TIME: create abstract: 00:00:00 + +Using technology "sky130A", version 1.0.493 + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design magicrc.well for technology sky130A ... +2 Magic internal units = 1 Lambda +Loading tech file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A.tech +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/extract.tcl" from command line. +Extracting with top ports unique (digital) +CIF input style is now "sky130()" +Flattening + +Extracting /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "EZ_sky130_ef_sc_hd__decap_40_12". +Reading "EZ_sky130_fd_sc_hd__decap_3". +Reading "EZ_sky130_fd_sc_hd__fill_1". +Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "EZ_sky130_fd_sc_hd__fill_2". +Reading "EZ_sky130_fd_sc_hd__fill_4". +Reading "EZ_sky130_fd_sc_hd__buf_4". +Reading "EZ_sky130_fd_sc_hd__fill_8". +Reading "EZ_sky130_fd_sc_hd__diode_2". +Reading "EZ_sky130_fd_sc_hd__buf_12". +Reading "EZ_sky130_fd_sc_hd__clkbuf_8". +Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1". +Reading "EZ_sky130_fd_sc_hd__clkbuf_4". +Reading "EZ_sky130_fd_sc_hd__buf_2". +Reading "EZ_sky130_fd_sc_hd__dfxtp_1". +Reading "EZ_sky130_fd_sc_hd__mux2_1". +Reading "EZ_sky130_fd_sc_hd__dfxtp_2". +Reading "EZ_sky130_fd_sc_hd__conb_1". +Reading "EZ_sky130_fd_sc_hd__and2_4". +Reading "EZ_sky130_fd_sc_hd__and2_2". +Reading "EZ_sky130_fd_sc_hd__nand2_8". +Reading "EZ_sky130_fd_sc_hd__nor2_2". +Reading "EZ_sky130_fd_sc_hd__inv_2". +Reading "EZ_sky130_fd_sc_hd__buf_6". +Reading "EZ_sky130_fd_sc_hd__nand3b_4". +Reading "EZ_sky130_fd_sc_hd__a211o_1". +Reading "EZ_sky130_fd_sc_hd__nor2_1". +Reading "EZ_sky130_fd_sc_hd__and3_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_4". +Reading "EZ_sky130_fd_sc_hd__and2b_1". +Reading "EZ_sky130_fd_sc_hd__buf_1". +Reading "EZ_sky130_fd_sc_hd__a22o_1". +Reading "EZ_sky130_fd_sc_hd__a31o_1". +Reading "EZ_sky130_fd_sc_hd__o21a_1". +Reading "EZ_sky130_fd_sc_hd__a221o_1". +Reading "EZ_sky130_fd_sc_hd__a32o_1". +Reading "EZ_sky130_fd_sc_hd__and2_1". +Reading "EZ_sky130_fd_sc_hd__nand2_1". +Reading "EZ_sky130_fd_sc_hd__o2bb2a_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_1". +Reading "EZ_sky130_fd_sc_hd__o21ai_1". +Reading "EZ_sky130_fd_sc_hd__a32o_4". +Reading "EZ_sky130_fd_sc_hd__a21o_1". +Reading "EZ_sky130_fd_sc_hd__or3b_2". +Reading "EZ_sky130_fd_sc_hd__and2b_2". +Reading "EZ_sky130_fd_sc_hd__a31o_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_1". +Reading "EZ_sky130_fd_sc_hd__or3b_4". +Reading "EZ_sky130_fd_sc_hd__and4_1". +Reading "EZ_sky130_fd_sc_hd__a41o_4". +Reading "EZ_sky130_fd_sc_hd__and3b_4". +Reading "EZ_sky130_fd_sc_hd__buf_8". +Reading "EZ_sky130_fd_sc_hd__clkbuf_16". +Reading "EZ_sky130_fd_sc_hd__dfxtp_4". +Reading "EZ_sky130_fd_sc_hd__nor2_8". +Reading "EZ_sky130_fd_sc_hd__or2_1". +Reading "EZ_sky130_fd_sc_hd__o31a_1". +Reading "EZ_sky130_fd_sc_hd__o211a_1". +Reading "EZ_sky130_fd_sc_hd__o32a_1". +Reading "EZ_sky130_fd_sc_hd__a31oi_1". +Reading "EZ_sky130_fd_sc_hd__o31ai_1". +Reading "EZ_sky130_fd_sc_hd__o211ai_4". +Reading "EZ_sky130_fd_sc_hd__a41oi_4". +Reading "EZ_sky130_fd_sc_hd__and4_2". +Reading "EZ_sky130_fd_sc_hd__xor2_1". +Reading "EZ_sky130_fd_sc_hd__or2_2". +Reading "EZ_sky130_fd_sc_hd__nor2_4". +Reading "EZ_sky130_fd_sc_hd__or3_4". +Reading "EZ_sky130_fd_sc_hd__nand2_2". +Reading "EZ_sky130_fd_sc_hd__xnor2_1". +Reading "EZ_sky130_fd_sc_hd__and3b_1". +Reading "EZ_sky130_fd_sc_hd__a31o_2". +Reading "EZ_sky130_fd_sc_hd__a21bo_1". +Reading "EZ_sky130_fd_sc_hd__a21boi_1". +Reading "EZ_sky130_fd_sc_hd__nand2b_1". +Reading "EZ_sky130_fd_sc_hd__xnor2_2". +Reading "EZ_sky130_fd_sc_hd__nand4_2". +Reading "EZ_sky130_fd_sc_hd__a41o_1". +Reading "EZ_sky130_fd_sc_hd__and4_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_2". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses + 55000 uses + 60000 uses + 65000 uses + 70000 uses + 75000 uses + 80000 uses + 85000 uses + 90000 uses + 95000 uses + 100000 uses + 105000 uses + 110000 uses + 115000 uses + 120000 uses + 125000 uses + 130000 uses + 135000 uses + 140000 uses + 145000 uses + 150000 uses + 155000 uses + 160000 uses + 165000 uses + 170000 uses + 175000 uses + 180000 uses + 185000 uses + 190000 uses + 195000 uses + 200000 uses + 205000 uses + 210000 uses + 215000 uses + 220000 uses + 225000 uses + 230000 uses + 235000 uses + 240000 uses + 245000 uses + 250000 uses + 255000 uses + 260000 uses + 265000 uses + 270000 uses + 275000 uses + 280000 uses + 285000 uses + 290000 uses + 295000 uses + 300000 uses + 305000 uses + 310000 uses + 315000 uses + 320000 uses + 325000 uses + 330000 uses + 335000 uses + 340000 uses + 345000 uses + 350000 uses + 355000 uses + 360000 uses + 365000 uses + 370000 uses + 375000 uses + 380000 uses + 385000 uses + 390000 uses + 395000 uses + 400000 uses + 405000 uses + 410000 uses + 415000 uses + 420000 uses + 425000 uses + 430000 uses + 435000 uses + 440000 uses + 445000 uses + 450000 uses + 455000 uses + 460000 uses + 465000 uses + 470000 uses + 475000 uses + 480000 uses + 485000 uses + 490000 uses + 495000 uses + 500000 uses + 505000 uses + 510000 uses + 515000 uses + 520000 uses + 525000 uses + 530000 uses + 535000 uses + 540000 uses + 545000 uses + 550000 uses + 555000 uses +Reading "user_project_wrapper". + +TIME: read GDS: 00:00:10 + + +TIME: add subcut: 00:00:00 + +Abstracting EZ_sky130_fd_sc_hd__fill_1 +Abstracting EZ_sky130_fd_sc_hd__fill_2 +Abstracting EZ_sky130_fd_sc_hd__fill_4 +Abstracting EZ_sky130_fd_sc_hd__fill_8 +Abstracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 + +TIME: set abstract: 00:00:00 + +Processing EZ_sky130_fd_sc_hd__decap_3 +Processing EZ_sky130_ef_sc_hd__decap_40_12 +Processing EZ_sky130_fd_sc_hd__buf_12 +Processing EZ_sky130_fd_sc_hd__diode_2 +Processing EZ_sky130_fd_sc_hd__clkbuf_2 +Processing EZ_sky130_fd_sc_hd__buf_1 +Processing EZ_sky130_fd_sc_hd__and2_1 +Processing EZ_sky130_fd_sc_hd__and4_1 +Processing EZ_sky130_fd_sc_hd__a31o_1 +Processing EZ_sky130_fd_sc_hd__and3_1 +Processing EZ_sky130_fd_sc_hd__and4_2 +Processing EZ_sky130_fd_sc_hd__dlygate4sd3_1 +Processing EZ_sky130_fd_sc_hd__nand2b_1 +Processing EZ_sky130_fd_sc_hd__xor2_1 +Processing EZ_sky130_fd_sc_hd__and4_4 +Processing EZ_sky130_fd_sc_hd__a21oi_1 +Processing EZ_sky130_fd_sc_hd__nand2_1 +Processing EZ_sky130_fd_sc_hd__a41o_1 +Processing EZ_sky130_fd_sc_hd__nand4_2 +Processing EZ_sky130_fd_sc_hd__xnor2_1 +Processing EZ_sky130_fd_sc_hd__dfxtp_4 +Processing EZ_sky130_fd_sc_hd__a211o_1 +Processing EZ_sky130_fd_sc_hd__a21o_1 +Processing EZ_sky130_fd_sc_hd__xnor2_2 +Processing EZ_sky130_fd_sc_hd__a22o_1 +Processing EZ_sky130_fd_sc_hd__dfxtp_2 +Processing EZ_sky130_fd_sc_hd__a21boi_1 +Processing EZ_sky130_fd_sc_hd__a21bo_1 +Processing EZ_sky130_fd_sc_hd__clkbuf_4 +Processing EZ_sky130_fd_sc_hd__o21a_1 +Processing EZ_sky130_fd_sc_hd__clkbuf_16 +Processing EZ_sky130_fd_sc_hd__a31o_2 +Processing EZ_sky130_fd_sc_hd__and3b_1 +Processing EZ_sky130_fd_sc_hd__buf_4 +Processing EZ_sky130_fd_sc_hd__inv_2 +Processing EZ_sky130_fd_sc_hd__nand2_2 +Processing EZ_sky130_fd_sc_hd__clkbuf_8 +Processing EZ_sky130_fd_sc_hd__dfxtp_1 +Processing EZ_sky130_fd_sc_hd__nor2_1 +Processing EZ_sky130_fd_sc_hd__or3_4 +Processing EZ_sky130_fd_sc_hd__nor2_4 +Processing EZ_sky130_fd_sc_hd__or2_1 +Processing EZ_sky130_fd_sc_hd__o2bb2a_1 +Processing EZ_sky130_fd_sc_hd__and2b_1 +Processing EZ_sky130_fd_sc_hd__or2_2 +Processing EZ_sky130_fd_sc_hd__mux2_1 +Processing EZ_sky130_fd_sc_hd__a41oi_4 +Processing EZ_sky130_fd_sc_hd__a21oi_4 +Processing EZ_sky130_fd_sc_hd__o211ai_4 +Processing EZ_sky130_fd_sc_hd__o31ai_1 +Processing EZ_sky130_fd_sc_hd__a31oi_1 +Processing EZ_sky130_fd_sc_hd__o32a_1 +Processing EZ_sky130_fd_sc_hd__o211a_1 +Processing EZ_sky130_fd_sc_hd__o31a_1 +Processing EZ_sky130_fd_sc_hd__nor2_8 +Processing EZ_sky130_fd_sc_hd__a32o_1 +Processing EZ_sky130_fd_sc_hd__conb_1 +Processing EZ_sky130_fd_sc_hd__buf_8 +Processing EZ_sky130_fd_sc_hd__clkbuf_1 +Processing EZ_sky130_fd_sc_hd__or3b_4 +Processing EZ_sky130_fd_sc_hd__and3b_4 +Processing EZ_sky130_fd_sc_hd__buf_6 +Processing EZ_sky130_fd_sc_hd__and2_2 +Processing EZ_sky130_fd_sc_hd__a41o_4 +Processing EZ_sky130_fd_sc_hd__a31o_4 +Processing EZ_sky130_fd_sc_hd__and2b_2 +Processing EZ_sky130_fd_sc_hd__or3b_2 +Processing EZ_sky130_fd_sc_hd__a32o_4 +Processing EZ_sky130_fd_sc_hd__o21ai_1 +Processing EZ_sky130_fd_sc_hd__a221o_1 +Processing EZ_sky130_fd_sc_hd__nand3b_4 +Processing EZ_sky130_fd_sc_hd__nand2_8 +Processing EZ_sky130_fd_sc_hd__and2_4 +Processing EZ_sky130_fd_sc_hd__nor2_2 +Processing EZ_sky130_fd_sc_hd__buf_2 +Processing user_proj_example +Processing user_project_wrapper +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Extraction style is now "ngspice()" +Extracting EZ_sky130_fd_sc_hd__decap_3 into EZ_sky130_fd_sc_hd__decap_3.ext: +EZ_sky130_fd_sc_hd__decap_3: 2 warnings +Extracting EZ_sky130_fd_sc_hd__fill_2 into EZ_sky130_fd_sc_hd__fill_2.ext: +Extracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 into EZ_sky130_fd_sc_hd__tapvpwrvgnd_1.ext: +Extracting EZ_sky130_fd_sc_hd__fill_8 into EZ_sky130_fd_sc_hd__fill_8.ext: +Extracting EZ_sky130_fd_sc_hd__fill_1 into EZ_sky130_fd_sc_hd__fill_1.ext: +Extracting EZ_sky130_ef_sc_hd__decap_40_12 into EZ_sky130_ef_sc_hd__decap_40_12.ext: +EZ_sky130_ef_sc_hd__decap_40_12: 2 warnings +Extracting EZ_sky130_fd_sc_hd__fill_4 into EZ_sky130_fd_sc_hd__fill_4.ext: +Extracting EZ_sky130_fd_sc_hd__buf_12 into EZ_sky130_fd_sc_hd__buf_12.ext: +Extracting EZ_sky130_fd_sc_hd__diode_2 into EZ_sky130_fd_sc_hd__diode_2.ext: +EZ_sky130_fd_sc_hd__diode_2: 1 warning +Extracting EZ_sky130_fd_sc_hd__clkbuf_2 into EZ_sky130_fd_sc_hd__clkbuf_2.ext: +Extracting EZ_sky130_fd_sc_hd__buf_1 into EZ_sky130_fd_sc_hd__buf_1.ext: +Extracting EZ_sky130_fd_sc_hd__and2_1 into EZ_sky130_fd_sc_hd__and2_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_1 into EZ_sky130_fd_sc_hd__and4_1.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_1 into EZ_sky130_fd_sc_hd__a31o_1.ext: +Extracting EZ_sky130_fd_sc_hd__and3_1 into EZ_sky130_fd_sc_hd__and3_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_2 into EZ_sky130_fd_sc_hd__and4_2.ext: +Extracting EZ_sky130_fd_sc_hd__dlygate4sd3_1 into EZ_sky130_fd_sc_hd__dlygate4sd3_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand2b_1 into EZ_sky130_fd_sc_hd__nand2b_1.ext: +Extracting EZ_sky130_fd_sc_hd__xor2_1 into EZ_sky130_fd_sc_hd__xor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_4 into EZ_sky130_fd_sc_hd__and4_4.ext: +Extracting EZ_sky130_fd_sc_hd__a21oi_1 into EZ_sky130_fd_sc_hd__a21oi_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_1 into EZ_sky130_fd_sc_hd__nand2_1.ext: +Extracting EZ_sky130_fd_sc_hd__a41o_1 into EZ_sky130_fd_sc_hd__a41o_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand4_2 into EZ_sky130_fd_sc_hd__nand4_2.ext: +Extracting EZ_sky130_fd_sc_hd__xnor2_1 into EZ_sky130_fd_sc_hd__xnor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_4 into EZ_sky130_fd_sc_hd__dfxtp_4.ext: +Extracting EZ_sky130_fd_sc_hd__a211o_1 into EZ_sky130_fd_sc_hd__a211o_1.ext: +Extracting EZ_sky130_fd_sc_hd__a21o_1 into EZ_sky130_fd_sc_hd__a21o_1.ext: +Extracting EZ_sky130_fd_sc_hd__xnor2_2 into EZ_sky130_fd_sc_hd__xnor2_2.ext: +Extracting EZ_sky130_fd_sc_hd__a22o_1 into EZ_sky130_fd_sc_hd__a22o_1.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_2 into EZ_sky130_fd_sc_hd__dfxtp_2.ext: +Extracting EZ_sky130_fd_sc_hd__a21boi_1 into EZ_sky130_fd_sc_hd__a21boi_1.ext: +Extracting EZ_sky130_fd_sc_hd__a21bo_1 into EZ_sky130_fd_sc_hd__a21bo_1.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_4 into EZ_sky130_fd_sc_hd__clkbuf_4.ext: +Extracting EZ_sky130_fd_sc_hd__o21a_1 into EZ_sky130_fd_sc_hd__o21a_1.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_16 into EZ_sky130_fd_sc_hd__clkbuf_16.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_2 into EZ_sky130_fd_sc_hd__a31o_2.ext: +Extracting EZ_sky130_fd_sc_hd__and3b_1 into EZ_sky130_fd_sc_hd__and3b_1.ext: +Extracting EZ_sky130_fd_sc_hd__buf_4 into EZ_sky130_fd_sc_hd__buf_4.ext: +Extracting EZ_sky130_fd_sc_hd__inv_2 into EZ_sky130_fd_sc_hd__inv_2.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_2 into EZ_sky130_fd_sc_hd__nand2_2.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_8 into EZ_sky130_fd_sc_hd__clkbuf_8.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_1 into EZ_sky130_fd_sc_hd__dfxtp_1.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_1 into EZ_sky130_fd_sc_hd__nor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__or3_4 into EZ_sky130_fd_sc_hd__or3_4.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_4 into EZ_sky130_fd_sc_hd__nor2_4.ext: +Extracting EZ_sky130_fd_sc_hd__or2_1 into EZ_sky130_fd_sc_hd__or2_1.ext: +Extracting EZ_sky130_fd_sc_hd__o2bb2a_1 into EZ_sky130_fd_sc_hd__o2bb2a_1.ext: +Extracting EZ_sky130_fd_sc_hd__and2b_1 into EZ_sky130_fd_sc_hd__and2b_1.ext: +Extracting EZ_sky130_fd_sc_hd__or2_2 into EZ_sky130_fd_sc_hd__or2_2.ext: +Extracting EZ_sky130_fd_sc_hd__mux2_1 into EZ_sky130_fd_sc_hd__mux2_1.ext: +Extracting EZ_sky130_fd_sc_hd__a41oi_4 into EZ_sky130_fd_sc_hd__a41oi_4.ext: +Extracting EZ_sky130_fd_sc_hd__a21oi_4 into EZ_sky130_fd_sc_hd__a21oi_4.ext: +Extracting EZ_sky130_fd_sc_hd__o211ai_4 into EZ_sky130_fd_sc_hd__o211ai_4.ext: +Extracting EZ_sky130_fd_sc_hd__o31ai_1 into EZ_sky130_fd_sc_hd__o31ai_1.ext: +Extracting EZ_sky130_fd_sc_hd__a31oi_1 into EZ_sky130_fd_sc_hd__a31oi_1.ext: +Extracting EZ_sky130_fd_sc_hd__o32a_1 into EZ_sky130_fd_sc_hd__o32a_1.ext: +Extracting EZ_sky130_fd_sc_hd__o211a_1 into EZ_sky130_fd_sc_hd__o211a_1.ext: +Extracting EZ_sky130_fd_sc_hd__o31a_1 into EZ_sky130_fd_sc_hd__o31a_1.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_8 into EZ_sky130_fd_sc_hd__nor2_8.ext: +Extracting EZ_sky130_fd_sc_hd__a32o_1 into EZ_sky130_fd_sc_hd__a32o_1.ext: +Extracting EZ_sky130_fd_sc_hd__conb_1 into EZ_sky130_fd_sc_hd__conb_1.ext: +Extracting EZ_sky130_fd_sc_hd__buf_8 into EZ_sky130_fd_sc_hd__buf_8.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_1 into EZ_sky130_fd_sc_hd__clkbuf_1.ext: +Extracting EZ_sky130_fd_sc_hd__or3b_4 into EZ_sky130_fd_sc_hd__or3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__and3b_4 into EZ_sky130_fd_sc_hd__and3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__buf_6 into EZ_sky130_fd_sc_hd__buf_6.ext: +Extracting EZ_sky130_fd_sc_hd__and2_2 into EZ_sky130_fd_sc_hd__and2_2.ext: +Extracting EZ_sky130_fd_sc_hd__a41o_4 into EZ_sky130_fd_sc_hd__a41o_4.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_4 into EZ_sky130_fd_sc_hd__a31o_4.ext: +Extracting EZ_sky130_fd_sc_hd__and2b_2 into EZ_sky130_fd_sc_hd__and2b_2.ext: +Extracting EZ_sky130_fd_sc_hd__or3b_2 into EZ_sky130_fd_sc_hd__or3b_2.ext: +Extracting EZ_sky130_fd_sc_hd__a32o_4 into EZ_sky130_fd_sc_hd__a32o_4.ext: +Extracting EZ_sky130_fd_sc_hd__o21ai_1 into EZ_sky130_fd_sc_hd__o21ai_1.ext: +Extracting EZ_sky130_fd_sc_hd__a221o_1 into EZ_sky130_fd_sc_hd__a221o_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand3b_4 into EZ_sky130_fd_sc_hd__nand3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_8 into EZ_sky130_fd_sc_hd__nand2_8.ext: +Extracting EZ_sky130_fd_sc_hd__and2_4 into EZ_sky130_fd_sc_hd__and2_4.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_2 into EZ_sky130_fd_sc_hd__nor2_2.ext: +Extracting EZ_sky130_fd_sc_hd__buf_2 into EZ_sky130_fd_sc_hd__buf_2.ext: +Extracting user_proj_example into user_proj_example.ext: +Extracting user_project_wrapper into user_project_wrapper.ext: +Total of 5 warnings. + +TIME: extract: 00:07:52 + +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 28 +Devs merged: 28 +Devs merged: 28 +Devs merged: 28 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 40 +Devs merged: 40 +Devs merged: 46 +Devs merged: 46 +Devs merged: 46 +Devs merged: 62 +Devs merged: 62 +Devs merged: 73 +Devs merged: 79 +Devs merged: 81 +Devs merged: 81 +Devs merged: 97 +Devs merged: 97 +Devs merged: 97 +Devs merged: 103 +Devs merged: 133 +Devs merged: 133 +Devs merged: 135 +Devs merged: 171 +Devs merged: 173 +Devs merged: 175 +Devs merged: 183 +Devs merged: 183 +Devs merged: 185 +Devs merged: 185 +Devs merged: 191 +Devs merged: 191 +Devs merged: 209 +Devs merged: 209 +Devs merged: 225 +Devs merged: 225 +Devs merged: 227 +Devs merged: 229 +Devs merged: 229 +Devs merged: 233 +Devs merged: 233 +Devs merged: 233 +Devs merged: 235 +Devs merged: 241 +Devs merged: 241 +Devs merged: 259 +Devs merged: 271 +Devs merged: 271 +Devs merged: 299 +Devs merged: 305 +Devs merged: 323 +Devs merged: 327 +Devs merged: 327 +Devs merged: 337 +Devs merged: 365 +Devs merged: 385 +Devs merged: 385 +Devs merged: 387 +Devs merged: 387 +Devs merged: 399 +Devs merged: 401 +Devs merged: 401 +Devs merged: 401 +Devs merged: 401 +exttospice finished. + +TIME: netlist: 00:00:46 + +Using technology "sky130A", version 1.0.493 +Creating layout hierarchy in /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/user_project_wrapper.hier... + +Netgen 1.5.272 compiled on Wed Apr 22 16:24:02 UTC 2026 +Warning: netgen command 'format' use fully-qualified name '::netgen::format' +Warning: netgen command 'global' use fully-qualified name '::netgen::global' +Reading layout /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/user_project_wrapper.gds.spice... +Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__nfet_01v8 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__diode_pw2nd_05v5 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__res_generic_po +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_nfet_01v8 +Creating placeholder cell definition. +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice... +Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__nfet_01v8 +Creating placeholder cell definition. +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_20_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_40_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_60_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_80_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice... +Call to undefined subcircuit sky130_fd_pr__res_generic_po +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_nfet_01v8 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__diode_pw2nd_05v5 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_sc_hd__nand2_2 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_sc_hd__nor2_2 +Creating placeholder cell definition. +Reading source /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v... +Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. +Note: Implicit pin HI in instance user_proj_example_142 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_143 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_144 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_145 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_146 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_147 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_148 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_149 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_150 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_151 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_152 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_153 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_154 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_155 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_156 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_157 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_158 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_159 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_160 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_161 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_162 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_163 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_164 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_165 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_166 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_167 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_168 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_169 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_170 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_171 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_172 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_173 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_174 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_175 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_176 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_177 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_178 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_179 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_180 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_181 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_182 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_183 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_184 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_185 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_186 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_187 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_188 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_189 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_190 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_191 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_192 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_193 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_194 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_195 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_196 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_197 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_198 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_199 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_200 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_201 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_202 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_203 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_204 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_205 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_206 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_207 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_208 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_209 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_210 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_211 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_212 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_213 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_214 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_215 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_216 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_217 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_218 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_219 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_220 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_221 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_222 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_223 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_224 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_225 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_226 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_227 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_228 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_229 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_230 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_231 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_232 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_233 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_234 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_235 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_236 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_237 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_238 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_239 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_240 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_241 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_242 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_243 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_244 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_245 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_246 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_247 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_248 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_249 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_250 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_251 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_252 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_253 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_254 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_255 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_256 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_257 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_258 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_259 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_260 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_261 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_262 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_263 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_264 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_265 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_266 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_267 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_268 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_269 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_270 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_271 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_141 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin X in instance clkload0 of sky130_fd_sc_hd__clkbuf_8 in cell user_proj_example +Note: Implicit pin X in instance clkload1 of sky130_fd_sc_hd__clkbuf_4 in cell user_proj_example +Note: Implicit pin X in instance clkload2 of sky130_fd_sc_hd__clkbuf_4 in cell user_proj_example +Reading source /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v... +Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. +Treating empty subcircuits as black-box cells +Generating JSON file result + +Reading setup file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A_setup.tcl + +Model sky130_fd_pr__res_generic_po pin 1 == 2 +No property value found for device sky130_fd_pr__res_generic_po +No property mult found for device sky130_fd_pr__res_generic_po +Model sky130_fd_pr__res_generic_po pin 1 == 2 +No property value found for device sky130_fd_pr__res_generic_po +No property mult found for device sky130_fd_pr__res_generic_po +Model sky130_fd_pr__nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__nfet_01v8 +No property sa found for device sky130_fd_pr__nfet_01v8 +No property sb found for device sky130_fd_pr__nfet_01v8 +No property sd found for device sky130_fd_pr__nfet_01v8 +No property nf found for device sky130_fd_pr__nfet_01v8 +No property nrd found for device sky130_fd_pr__nfet_01v8 +No property nrs found for device sky130_fd_pr__nfet_01v8 +No property area found for device sky130_fd_pr__nfet_01v8 +No property perim found for device sky130_fd_pr__nfet_01v8 +No property topography found for device sky130_fd_pr__nfet_01v8 +Model sky130_fd_pr__nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__nfet_01v8 +No property sa found for device sky130_fd_pr__nfet_01v8 +No property sb found for device sky130_fd_pr__nfet_01v8 +No property sd found for device sky130_fd_pr__nfet_01v8 +No property nf found for device sky130_fd_pr__nfet_01v8 +No property nrd found for device sky130_fd_pr__nfet_01v8 +No property nrs found for device sky130_fd_pr__nfet_01v8 +No property area found for device sky130_fd_pr__nfet_01v8 +No property perim found for device sky130_fd_pr__nfet_01v8 +No property topography found for device sky130_fd_pr__nfet_01v8 +Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3 +No property mult found for device sky130_fd_pr__pfet_01v8_hvt +No property sa found for device sky130_fd_pr__pfet_01v8_hvt +No property sb found for device sky130_fd_pr__pfet_01v8_hvt +No property sd found for device sky130_fd_pr__pfet_01v8_hvt +No property nf found for device sky130_fd_pr__pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__pfet_01v8_hvt +No property area found for device sky130_fd_pr__pfet_01v8_hvt +No property perim found for device sky130_fd_pr__pfet_01v8_hvt +No property topography found for device sky130_fd_pr__pfet_01v8_hvt +Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3 +No property mult found for device sky130_fd_pr__pfet_01v8_hvt +No property sa found for device sky130_fd_pr__pfet_01v8_hvt +No property sb found for device sky130_fd_pr__pfet_01v8_hvt +No property sd found for device sky130_fd_pr__pfet_01v8_hvt +No property nf found for device sky130_fd_pr__pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__pfet_01v8_hvt +No property area found for device sky130_fd_pr__pfet_01v8_hvt +No property perim found for device sky130_fd_pr__pfet_01v8_hvt +No property topography found for device sky130_fd_pr__pfet_01v8_hvt +Model sky130_fd_pr__special_nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__special_nfet_01v8 +No property sa found for device sky130_fd_pr__special_nfet_01v8 +No property sb found for device sky130_fd_pr__special_nfet_01v8 +No property sd found for device sky130_fd_pr__special_nfet_01v8 +No property nf found for device sky130_fd_pr__special_nfet_01v8 +No property nrd found for device sky130_fd_pr__special_nfet_01v8 +No property nrs found for device sky130_fd_pr__special_nfet_01v8 +No property area found for device sky130_fd_pr__special_nfet_01v8 +No property perim found for device sky130_fd_pr__special_nfet_01v8 +No property topography found for device sky130_fd_pr__special_nfet_01v8 +Model sky130_fd_pr__special_nfet_01v8 pin 1 == 3 +No property as found for device sky130_fd_pr__special_nfet_01v8 +No property ad found for device sky130_fd_pr__special_nfet_01v8 +No property ps found for device sky130_fd_pr__special_nfet_01v8 +No property pd found for device sky130_fd_pr__special_nfet_01v8 +No property mult found for device sky130_fd_pr__special_nfet_01v8 +No property sa found for device sky130_fd_pr__special_nfet_01v8 +No property sb found for device sky130_fd_pr__special_nfet_01v8 +No property sd found for device sky130_fd_pr__special_nfet_01v8 +No property nf found for device sky130_fd_pr__special_nfet_01v8 +No property nrd found for device sky130_fd_pr__special_nfet_01v8 +No property nrs found for device sky130_fd_pr__special_nfet_01v8 +No property area found for device sky130_fd_pr__special_nfet_01v8 +No property perim found for device sky130_fd_pr__special_nfet_01v8 +No property topography found for device sky130_fd_pr__special_nfet_01v8 +Model sky130_fd_pr__special_pfet_01v8_hvt pin 1 == 3 +No property as found for device sky130_fd_pr__special_pfet_01v8_hvt +No property ad found for device sky130_fd_pr__special_pfet_01v8_hvt +No property ps found for device sky130_fd_pr__special_pfet_01v8_hvt +No property pd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property mult found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sa found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sb found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nf found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__special_pfet_01v8_hvt +No property area found for device sky130_fd_pr__special_pfet_01v8_hvt +No property perim found for device sky130_fd_pr__special_pfet_01v8_hvt +No property topography found for device sky130_fd_pr__special_pfet_01v8_hvt +No property value found for device sky130_fd_pr__diode_pw2nd_05v5 +No property mult found for device sky130_fd_pr__diode_pw2nd_05v5 +No property value found for device sky130_fd_pr__diode_pw2nd_05v5 +No property mult found for device sky130_fd_pr__diode_pw2nd_05v5 +Matching pins of sky130_fd_pr__nfet_01v8 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__pfet_01v8_hvt in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__diode_pw2nd_05v5 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__diode_pw2nd_05v5 |Circuit 2: sky130_fd_pr__diode_pw2nd_05v5 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__res_generic_po in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__res_generic_po |Circuit 2: sky130_fd_pr__res_generic_po +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__special_nfet_01v8 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__special_nfet_01v8 |Circuit 2: sky130_fd_pr__special_nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_sc_hd__and3_1 and EZ_sky130_fd_sc_hd__and3_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3_1 in circuit 1 and sky130_fd_sc_hd__and3_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2b_1 and EZ_sky130_fd_sc_hd__and2b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2b_1 in circuit 1 and sky130_fd_sc_hd__and2b_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2b_2 and EZ_sky130_fd_sc_hd__and2b_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2b_2 in circuit 1 and sky130_fd_sc_hd__and2b_2 in circuit 2 +Device classes sky130_fd_sc_hd__a21bo_1 and EZ_sky130_fd_sc_hd__a21bo_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21bo_1 in circuit 1 and sky130_fd_sc_hd__a21bo_1 in circuit 2 +Device classes sky130_fd_sc_hd__tapvpwrvgnd_1 and EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit 1 and sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2_1 and EZ_sky130_fd_sc_hd__and2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_1 in circuit 1 and sky130_fd_sc_hd__and2_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2_2 and EZ_sky130_fd_sc_hd__and2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_2 in circuit 1 and sky130_fd_sc_hd__and2_2 in circuit 2 +Device classes sky130_fd_sc_hd__and2_4 and EZ_sky130_fd_sc_hd__and2_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_4 in circuit 1 and sky130_fd_sc_hd__and2_4 in circuit 2 +Device classes sky130_fd_sc_hd__decap_3 and EZ_sky130_fd_sc_hd__decap_3 are equivalent. +Equating EZ_sky130_fd_sc_hd__decap_3 in circuit 1 and sky130_fd_sc_hd__decap_3 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_1 and EZ_sky130_fd_sc_hd__clkbuf_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_1 in circuit 1 and sky130_fd_sc_hd__clkbuf_1 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_2 and EZ_sky130_fd_sc_hd__clkbuf_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_2 in circuit 1 and sky130_fd_sc_hd__clkbuf_2 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_4 and EZ_sky130_fd_sc_hd__clkbuf_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_4 in circuit 1 and sky130_fd_sc_hd__clkbuf_4 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_8 and EZ_sky130_fd_sc_hd__clkbuf_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_8 in circuit 1 and sky130_fd_sc_hd__clkbuf_8 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_1 and EZ_sky130_fd_sc_hd__nand2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_1 in circuit 1 and sky130_fd_sc_hd__nand2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_2 and EZ_sky130_fd_sc_hd__nand2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_2 in circuit 1 and sky130_fd_sc_hd__nand2_2 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_8 and EZ_sky130_fd_sc_hd__nand2_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_8 in circuit 1 and sky130_fd_sc_hd__nand2_8 in circuit 2 +Device classes sky130_fd_sc_hd__conb_1 and EZ_sky130_fd_sc_hd__conb_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__conb_1 in circuit 1 and sky130_fd_sc_hd__conb_1 in circuit 2 +Device classes sky130_fd_sc_hd__buf_12 and EZ_sky130_fd_sc_hd__buf_12 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_12 in circuit 1 and sky130_fd_sc_hd__buf_12 in circuit 2 +Device classes sky130_fd_sc_hd__a21boi_1 and EZ_sky130_fd_sc_hd__a21boi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21boi_1 in circuit 1 and sky130_fd_sc_hd__a21boi_1 in circuit 2 +Device classes sky130_fd_sc_hd__o211ai_4 and EZ_sky130_fd_sc_hd__o211ai_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__o211ai_4 in circuit 1 and sky130_fd_sc_hd__o211ai_4 in circuit 2 +Device classes sky130_ef_sc_hd__decap_40_12 and EZ_sky130_ef_sc_hd__decap_40_12 are equivalent. +Equating EZ_sky130_ef_sc_hd__decap_40_12 in circuit 1 and sky130_ef_sc_hd__decap_40_12 in circuit 2 +Device classes sky130_fd_sc_hd__a32o_1 and EZ_sky130_fd_sc_hd__a32o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a32o_1 in circuit 1 and sky130_fd_sc_hd__a32o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a32o_4 and EZ_sky130_fd_sc_hd__a32o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a32o_4 in circuit 1 and sky130_fd_sc_hd__a32o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a22o_1 and EZ_sky130_fd_sc_hd__a22o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a22o_1 in circuit 1 and sky130_fd_sc_hd__a22o_1 in circuit 2 +Device classes sky130_fd_sc_hd__xnor2_1 and EZ_sky130_fd_sc_hd__xnor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__xnor2_1 in circuit 1 and sky130_fd_sc_hd__xnor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__xnor2_2 and EZ_sky130_fd_sc_hd__xnor2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__xnor2_2 in circuit 1 and sky130_fd_sc_hd__xnor2_2 in circuit 2 +Device classes sky130_fd_sc_hd__buf_1 and EZ_sky130_fd_sc_hd__buf_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_1 in circuit 1 and sky130_fd_sc_hd__buf_1 in circuit 2 +Device classes sky130_fd_sc_hd__buf_2 and EZ_sky130_fd_sc_hd__buf_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_2 in circuit 1 and sky130_fd_sc_hd__buf_2 in circuit 2 +Device classes sky130_fd_sc_hd__buf_4 and EZ_sky130_fd_sc_hd__buf_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_4 in circuit 1 and sky130_fd_sc_hd__buf_4 in circuit 2 +Device classes sky130_fd_sc_hd__buf_6 and EZ_sky130_fd_sc_hd__buf_6 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_6 in circuit 1 and sky130_fd_sc_hd__buf_6 in circuit 2 +Device classes sky130_fd_sc_hd__buf_8 and EZ_sky130_fd_sc_hd__buf_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_8 in circuit 1 and sky130_fd_sc_hd__buf_8 in circuit 2 +Device classes sky130_fd_sc_hd__o211a_1 and EZ_sky130_fd_sc_hd__o211a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o211a_1 in circuit 1 and sky130_fd_sc_hd__o211a_1 in circuit 2 +Device classes sky130_fd_sc_hd__mux2_1 and EZ_sky130_fd_sc_hd__mux2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__mux2_1 in circuit 1 and sky130_fd_sc_hd__mux2_1 in circuit 2 +Device classes sky130_fd_sc_hd__diode_2 and EZ_sky130_fd_sc_hd__diode_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__diode_2 in circuit 1 and sky130_fd_sc_hd__diode_2 in circuit 2 +Device classes sky130_fd_sc_hd__a221o_1 and EZ_sky130_fd_sc_hd__a221o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a221o_1 in circuit 1 and sky130_fd_sc_hd__a221o_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand3b_4 and EZ_sky130_fd_sc_hd__nand3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand3b_4 in circuit 1 and sky130_fd_sc_hd__nand3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__a211o_1 and EZ_sky130_fd_sc_hd__a211o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a211o_1 in circuit 1 and sky130_fd_sc_hd__a211o_1 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_1 and EZ_sky130_fd_sc_hd__nor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_1 in circuit 1 and sky130_fd_sc_hd__nor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_2 and EZ_sky130_fd_sc_hd__nor2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_2 in circuit 1 and sky130_fd_sc_hd__nor2_2 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_4 and EZ_sky130_fd_sc_hd__nor2_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_4 in circuit 1 and sky130_fd_sc_hd__nor2_4 in circuit 2 +Device classes sky130_fd_sc_hd__inv_2 and EZ_sky130_fd_sc_hd__inv_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__inv_2 in circuit 1 and sky130_fd_sc_hd__inv_2 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_8 and EZ_sky130_fd_sc_hd__nor2_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_8 in circuit 1 and sky130_fd_sc_hd__nor2_8 in circuit 2 +Device classes sky130_fd_sc_hd__a41o_1 and EZ_sky130_fd_sc_hd__a41o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41o_1 in circuit 1 and sky130_fd_sc_hd__a41o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a41o_4 and EZ_sky130_fd_sc_hd__a41o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41o_4 in circuit 1 and sky130_fd_sc_hd__a41o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_1 and EZ_sky130_fd_sc_hd__a31o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_1 in circuit 1 and sky130_fd_sc_hd__a31o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_2 and EZ_sky130_fd_sc_hd__a31o_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_2 in circuit 1 and sky130_fd_sc_hd__a31o_2 in circuit 2 +Device classes sky130_fd_sc_hd__o32a_1 and EZ_sky130_fd_sc_hd__o32a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o32a_1 in circuit 1 and sky130_fd_sc_hd__o32a_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_4 and EZ_sky130_fd_sc_hd__a31o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_4 in circuit 1 and sky130_fd_sc_hd__a31o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a21o_1 and EZ_sky130_fd_sc_hd__a21o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21o_1 in circuit 1 and sky130_fd_sc_hd__a21o_1 in circuit 2 +Device classes sky130_fd_sc_hd__or3_4 and EZ_sky130_fd_sc_hd__or3_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3_4 in circuit 1 and sky130_fd_sc_hd__or3_4 in circuit 2 +Device classes sky130_fd_sc_hd__a41oi_4 and EZ_sky130_fd_sc_hd__a41oi_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41oi_4 in circuit 1 and sky130_fd_sc_hd__a41oi_4 in circuit 2 +Device classes sky130_fd_sc_hd__dlygate4sd3_1 and EZ_sky130_fd_sc_hd__dlygate4sd3_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__dlygate4sd3_1 in circuit 1 and sky130_fd_sc_hd__dlygate4sd3_1 in circuit 2 +Device classes sky130_fd_sc_hd__o21ai_1 and EZ_sky130_fd_sc_hd__o21ai_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o21ai_1 in circuit 1 and sky130_fd_sc_hd__o21ai_1 in circuit 2 +Device classes sky130_fd_sc_hd__a21oi_1 and EZ_sky130_fd_sc_hd__a21oi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21oi_1 in circuit 1 and sky130_fd_sc_hd__a21oi_1 in circuit 2 +Device classes sky130_fd_sc_hd__a21oi_4 and EZ_sky130_fd_sc_hd__a21oi_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21oi_4 in circuit 1 and sky130_fd_sc_hd__a21oi_4 in circuit 2 +Device classes sky130_fd_sc_hd__xor2_1 and EZ_sky130_fd_sc_hd__xor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__xor2_1 in circuit 1 and sky130_fd_sc_hd__xor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand2b_1 and EZ_sky130_fd_sc_hd__nand2b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2b_1 in circuit 1 and sky130_fd_sc_hd__nand2b_1 in circuit 2 +Device classes sky130_fd_sc_hd__or3b_2 and EZ_sky130_fd_sc_hd__or3b_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3b_2 in circuit 1 and sky130_fd_sc_hd__or3b_2 in circuit 2 +Device classes sky130_fd_sc_hd__or3b_4 and EZ_sky130_fd_sc_hd__or3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3b_4 in circuit 1 and sky130_fd_sc_hd__or3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__and4_1 and EZ_sky130_fd_sc_hd__and4_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_1 in circuit 1 and sky130_fd_sc_hd__and4_1 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_16 and EZ_sky130_fd_sc_hd__clkbuf_16 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_16 in circuit 1 and sky130_fd_sc_hd__clkbuf_16 in circuit 2 +Device classes sky130_fd_sc_hd__and4_2 and EZ_sky130_fd_sc_hd__and4_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_2 in circuit 1 and sky130_fd_sc_hd__and4_2 in circuit 2 +Device classes sky130_fd_sc_hd__and4_4 and EZ_sky130_fd_sc_hd__and4_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_4 in circuit 1 and sky130_fd_sc_hd__and4_4 in circuit 2 +Device classes sky130_fd_sc_hd__o31a_1 and EZ_sky130_fd_sc_hd__o31a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o31a_1 in circuit 1 and sky130_fd_sc_hd__o31a_1 in circuit 2 +Device classes sky130_fd_sc_hd__o21a_1 and EZ_sky130_fd_sc_hd__o21a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o21a_1 in circuit 1 and sky130_fd_sc_hd__o21a_1 in circuit 2 +Device classes sky130_fd_sc_hd__o2bb2a_1 and EZ_sky130_fd_sc_hd__o2bb2a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o2bb2a_1 in circuit 1 and sky130_fd_sc_hd__o2bb2a_1 in circuit 2 +Device classes sky130_fd_sc_hd__or2_1 and EZ_sky130_fd_sc_hd__or2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__or2_1 in circuit 1 and sky130_fd_sc_hd__or2_1 in circuit 2 +Device classes sky130_fd_sc_hd__or2_2 and EZ_sky130_fd_sc_hd__or2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__or2_2 in circuit 1 and sky130_fd_sc_hd__or2_2 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_1 and EZ_sky130_fd_sc_hd__dfxtp_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_1 in circuit 1 and sky130_fd_sc_hd__dfxtp_1 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_2 and EZ_sky130_fd_sc_hd__dfxtp_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_2 in circuit 1 and sky130_fd_sc_hd__dfxtp_2 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_4 and EZ_sky130_fd_sc_hd__dfxtp_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_4 in circuit 1 and sky130_fd_sc_hd__dfxtp_4 in circuit 2 +Device classes sky130_fd_sc_hd__o31ai_1 and EZ_sky130_fd_sc_hd__o31ai_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o31ai_1 in circuit 1 and sky130_fd_sc_hd__o31ai_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31oi_1 and EZ_sky130_fd_sc_hd__a31oi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31oi_1 in circuit 1 and sky130_fd_sc_hd__a31oi_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand4_2 and EZ_sky130_fd_sc_hd__nand4_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand4_2 in circuit 1 and sky130_fd_sc_hd__nand4_2 in circuit 2 +Device classes sky130_fd_sc_hd__and3b_1 and EZ_sky130_fd_sc_hd__and3b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3b_1 in circuit 1 and sky130_fd_sc_hd__and3b_1 in circuit 2 +Device classes sky130_fd_sc_hd__and3b_4 and EZ_sky130_fd_sc_hd__and3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3b_4 in circuit 1 and sky130_fd_sc_hd__and3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__fill_1 and EZ_sky130_fd_sc_hd__fill_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_1 in circuit 1 and sky130_fd_sc_hd__fill_1 in circuit 2 +Device classes sky130_fd_sc_hd__fill_2 and EZ_sky130_fd_sc_hd__fill_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_2 in circuit 1 and sky130_fd_sc_hd__fill_2 in circuit 2 +Device classes sky130_fd_sc_hd__fill_4 and EZ_sky130_fd_sc_hd__fill_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_4 in circuit 1 and sky130_fd_sc_hd__fill_4 in circuit 2 +Device classes sky130_fd_sc_hd__fill_8 and EZ_sky130_fd_sc_hd__fill_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_8 in circuit 1 and sky130_fd_sc_hd__fill_8 in circuit 2 +Comparison output logged to file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report +Logging to file "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report" enabled +Circuit sky130_fd_pr__pfet_01v8_hvt contains no devices. +Circuit sky130_fd_pr__nfet_01v8 contains no devices. +Circuit sky130_fd_pr__diode_pw2nd_05v5 contains no devices. +Circuit sky130_fd_pr__res_generic_po contains no devices. +Circuit sky130_fd_pr__special_nfet_01v8 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_4' +Circuit EZ_sky130_fd_sc_hd__fill_4 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_4' +Circuit sky130_fd_sc_hd__fill_4 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_4 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_ef_sc_hd__decap_40_12' +Circuit EZ_sky130_ef_sc_hd__decap_40_12 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. +Contents of circuit 2: Circuit: 'sky130_ef_sc_hd__decap_40_12' +Circuit sky130_ef_sc_hd__decap_40_12 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_1' +Circuit EZ_sky130_fd_sc_hd__fill_1 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_1' +Circuit sky130_fd_sc_hd__fill_1 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_1 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_2' +Circuit EZ_sky130_fd_sc_hd__fill_2 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_2' +Circuit sky130_fd_sc_hd__fill_2 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_2 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__decap_3' +Circuit EZ_sky130_fd_sc_hd__decap_3 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_3' +Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__tapvpwrvgnd_1' +Circuit EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. +Circuit contains 0 nets, and 2 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1' +Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. +Circuit contains 0 nets, and 2 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__diode_2' +Circuit EZ_sky130_fd_sc_hd__diode_2 contains 1 device instances. + Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1 +Circuit contains 2 nets, and 3 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__diode_2' +Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances. + Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1 +Circuit contains 2 nets, and 3 disconnected pins. + +Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. +Circuit 1 contains 2 nets, Circuit 2 contains 2 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__mux2_1' +Circuit EZ_sky130_fd_sc_hd__mux2_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__mux2_1' +Circuit sky130_fd_sc_hd__mux2_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_8' +Circuit EZ_sky130_fd_sc_hd__fill_8 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_8' +Circuit sky130_fd_sc_hd__fill_8 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_8 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dlygate4sd3_1' +Circuit EZ_sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dlygate4sd3_1' +Circuit sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o21ai_1' +Circuit EZ_sky130_fd_sc_hd__o21ai_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21ai_1' +Circuit sky130_fd_sc_hd__o21ai_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_1' +Circuit EZ_sky130_fd_sc_hd__nor2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_1' +Circuit sky130_fd_sc_hd__nor2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__conb_1' +Circuit EZ_sky130_fd_sc_hd__conb_1 contains 2 device instances. + Class: sky130_fd_pr__res_generic_po instances: 2 +Circuit contains 4 nets, and 2 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__conb_1' +Circuit sky130_fd_sc_hd__conb_1 contains 2 device instances. + Class: sky130_fd_pr__res_generic_po instances: 2 +Circuit contains 4 nets, and 2 disconnected pins. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_12' +Circuit EZ_sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_12' +Circuit sky130_fd_sc_hd__buf_12 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_12' +Circuit EZ_sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_12' +Circuit sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o31ai_1' +Circuit EZ_sky130_fd_sc_hd__o31ai_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o31ai_1' +Circuit sky130_fd_sc_hd__o31ai_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_1' +Circuit EZ_sky130_fd_sc_hd__dfxtp_1 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_1' +Circuit sky130_fd_sc_hd__dfxtp_1 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_1' +Circuit EZ_sky130_fd_sc_hd__and2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_1' +Circuit sky130_fd_sc_hd__and2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_4' +Circuit EZ_sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_4' +Circuit sky130_fd_sc_hd__buf_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_4' +Circuit EZ_sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_4' +Circuit sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_1' +Circuit EZ_sky130_fd_sc_hd__a32o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_1' +Circuit sky130_fd_sc_hd__a32o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a221o_1' +Circuit EZ_sky130_fd_sc_hd__a221o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a221o_1' +Circuit sky130_fd_sc_hd__a221o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xor2_1' +Circuit EZ_sky130_fd_sc_hd__xor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xor2_1' +Circuit sky130_fd_sc_hd__xor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_1' +Circuit EZ_sky130_fd_sc_hd__buf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_1' +Circuit sky130_fd_sc_hd__buf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_1' +Circuit EZ_sky130_fd_sc_hd__and3b_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_1' +Circuit sky130_fd_sc_hd__and3b_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_4' +Circuit EZ_sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_4' +Circuit sky130_fd_sc_hd__and3b_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_4' +Circuit EZ_sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_4' +Circuit sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3_1' +Circuit EZ_sky130_fd_sc_hd__and3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3_1' +Circuit sky130_fd_sc_hd__and3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_4' +Circuit EZ_sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_4' +Circuit sky130_fd_sc_hd__dfxtp_4 contains 30 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 11 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 15 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_4' +Circuit EZ_sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_4' +Circuit sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21boi_1' +Circuit EZ_sky130_fd_sc_hd__a21boi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21boi_1' +Circuit sky130_fd_sc_hd__a21boi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_1' +Circuit EZ_sky130_fd_sc_hd__a31o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_1' +Circuit sky130_fd_sc_hd__a31o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_8' +Circuit EZ_sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8' +Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 10 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 10 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_8' +Circuit EZ_sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8' +Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_1' +Circuit EZ_sky130_fd_sc_hd__a21oi_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_1' +Circuit sky130_fd_sc_hd__a21oi_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_4' +Circuit EZ_sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_4' +Circuit sky130_fd_sc_hd__a31o_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 12 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_4' +Circuit EZ_sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_4' +Circuit sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. + +Circuit 1 contains 13 devices, Circuit 2 contains 13 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_4' +Circuit EZ_sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_4' +Circuit sky130_fd_sc_hd__clkbuf_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_4' +Circuit EZ_sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_4' +Circuit sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_2' +Circuit EZ_sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_2' +Circuit sky130_fd_sc_hd__dfxtp_2 contains 26 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 9 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 13 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_2' +Circuit EZ_sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_2' +Circuit sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21bo_1' +Circuit EZ_sky130_fd_sc_hd__a21bo_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21bo_1' +Circuit sky130_fd_sc_hd__a21bo_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_4' +Circuit EZ_sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_4' +Circuit sky130_fd_sc_hd__a41o_4 contains 28 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 14 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 14 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_4' +Circuit EZ_sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_4' +Circuit sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o2bb2a_1' +Circuit EZ_sky130_fd_sc_hd__o2bb2a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o2bb2a_1' +Circuit sky130_fd_sc_hd__o2bb2a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a211o_1' +Circuit EZ_sky130_fd_sc_hd__a211o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a211o_1' +Circuit sky130_fd_sc_hd__a211o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_4' +Circuit EZ_sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_4' +Circuit sky130_fd_sc_hd__or3b_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_4' +Circuit EZ_sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_4' +Circuit sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41oi_4' +Circuit EZ_sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41oi_4' +Circuit sky130_fd_sc_hd__a41oi_4 contains 40 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 20 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 20 +Circuit contains 14 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41oi_4' +Circuit EZ_sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41oi_4' +Circuit sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a22o_1' +Circuit EZ_sky130_fd_sc_hd__a22o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a22o_1' +Circuit sky130_fd_sc_hd__a22o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_2' +Circuit EZ_sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_2' +Circuit sky130_fd_sc_hd__and2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_2' +Circuit EZ_sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_2' +Circuit sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_16' +Circuit EZ_sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16' +Circuit sky130_fd_sc_hd__clkbuf_16 contains 40 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 20 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 20 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_16' +Circuit EZ_sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16' +Circuit sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_2' +Circuit EZ_sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_2' +Circuit sky130_fd_sc_hd__clkbuf_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_2' +Circuit EZ_sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_2' +Circuit sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_2' +Circuit EZ_sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_2' +Circuit sky130_fd_sc_hd__or2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_2' +Circuit EZ_sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_2' +Circuit sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand4_2' +Circuit EZ_sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand4_2' +Circuit sky130_fd_sc_hd__nand4_2 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand4_2' +Circuit EZ_sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand4_2' +Circuit sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_1' +Circuit EZ_sky130_fd_sc_hd__and4_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_1' +Circuit sky130_fd_sc_hd__and4_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__inv_2' +Circuit EZ_sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_2' +Circuit sky130_fd_sc_hd__inv_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 6 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__inv_2' +Circuit EZ_sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_2' +Circuit sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 6 nets, Circuit 2 contains 6 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2b_1' +Circuit EZ_sky130_fd_sc_hd__nand2b_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2b_1' +Circuit sky130_fd_sc_hd__nand2b_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3_4' +Circuit EZ_sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3_4' +Circuit sky130_fd_sc_hd__or3_4 contains 14 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 7 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 7 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3_4' +Circuit EZ_sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3_4' +Circuit sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_1' +Circuit EZ_sky130_fd_sc_hd__or2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_1' +Circuit sky130_fd_sc_hd__or2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_4' +Circuit EZ_sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_4' +Circuit sky130_fd_sc_hd__a21oi_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 12 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 +Circuit contains 10 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_4' +Circuit EZ_sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_4' +Circuit sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_1' +Circuit EZ_sky130_fd_sc_hd__nand2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_1' +Circuit sky130_fd_sc_hd__nand2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_4' +Circuit EZ_sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4' +Circuit sky130_fd_sc_hd__a32o_4 contains 28 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 14 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 14 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_4' +Circuit EZ_sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4' +Circuit sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21o_1' +Circuit EZ_sky130_fd_sc_hd__a21o_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21o_1' +Circuit sky130_fd_sc_hd__a21o_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_2' +Circuit EZ_sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_2' +Circuit sky130_fd_sc_hd__a31o_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_2' +Circuit EZ_sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_2' +Circuit sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_2' +Circuit EZ_sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_2' +Circuit sky130_fd_sc_hd__and4_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_2' +Circuit EZ_sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_2' +Circuit sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_1' +Circuit EZ_sky130_fd_sc_hd__xnor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_1' +Circuit sky130_fd_sc_hd__xnor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_2' +Circuit EZ_sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_2' +Circuit sky130_fd_sc_hd__nand2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_2' +Circuit EZ_sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_2' +Circuit sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_1' +Circuit EZ_sky130_fd_sc_hd__clkbuf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_1' +Circuit sky130_fd_sc_hd__clkbuf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o32a_1' +Circuit EZ_sky130_fd_sc_hd__o32a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o32a_1' +Circuit sky130_fd_sc_hd__o32a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_2' +Circuit EZ_sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_2' +Circuit sky130_fd_sc_hd__buf_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_2' +Circuit EZ_sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_2' +Circuit sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_4' +Circuit EZ_sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_4' +Circuit sky130_fd_sc_hd__and4_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_4' +Circuit EZ_sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_4' +Circuit sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o21a_1' +Circuit EZ_sky130_fd_sc_hd__o21a_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21a_1' +Circuit sky130_fd_sc_hd__o21a_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_8' +Circuit EZ_sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_8' +Circuit sky130_fd_sc_hd__buf_8 contains 22 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 11 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 11 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_8' +Circuit EZ_sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_8' +Circuit sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_6' +Circuit EZ_sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_6' +Circuit sky130_fd_sc_hd__buf_6 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_6' +Circuit EZ_sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_6' +Circuit sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_1' +Circuit EZ_sky130_fd_sc_hd__a41o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_1' +Circuit sky130_fd_sc_hd__a41o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_8' +Circuit EZ_sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_8' +Circuit sky130_fd_sc_hd__nand2_8 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_8' +Circuit EZ_sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_8' +Circuit sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_4' +Circuit EZ_sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4' +Circuit sky130_fd_sc_hd__and2_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_4' +Circuit EZ_sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4' +Circuit sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand3b_4' +Circuit EZ_sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand3b_4' +Circuit sky130_fd_sc_hd__nand3b_4 contains 26 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 13 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 13 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand3b_4' +Circuit EZ_sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand3b_4' +Circuit sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_2' +Circuit EZ_sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_2' +Circuit sky130_fd_sc_hd__nor2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_2' +Circuit EZ_sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_2' +Circuit sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_1' +Circuit EZ_sky130_fd_sc_hd__and2b_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_1' +Circuit sky130_fd_sc_hd__and2b_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_2' +Circuit EZ_sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_2' +Circuit sky130_fd_sc_hd__xnor2_2 contains 20 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 10 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 10 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_2' +Circuit EZ_sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_2' +Circuit sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_8' +Circuit EZ_sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_8' +Circuit sky130_fd_sc_hd__nor2_8 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_8' +Circuit EZ_sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_8' +Circuit sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211ai_4' +Circuit EZ_sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211ai_4' +Circuit sky130_fd_sc_hd__o211ai_4 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 14 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211ai_4' +Circuit EZ_sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211ai_4' +Circuit sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211a_1' +Circuit EZ_sky130_fd_sc_hd__o211a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211a_1' +Circuit sky130_fd_sc_hd__o211a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_2' +Circuit EZ_sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_2' +Circuit sky130_fd_sc_hd__or3b_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_2' +Circuit EZ_sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_2' +Circuit sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o31a_1' +Circuit EZ_sky130_fd_sc_hd__o31a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o31a_1' +Circuit sky130_fd_sc_hd__o31a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_4' +Circuit EZ_sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_4' +Circuit sky130_fd_sc_hd__nor2_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_4' +Circuit EZ_sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_4' +Circuit sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_2' +Circuit EZ_sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_2' +Circuit sky130_fd_sc_hd__and2b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 10 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_2' +Circuit EZ_sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_2' +Circuit sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31oi_1' +Circuit EZ_sky130_fd_sc_hd__a31oi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31oi_1' +Circuit sky130_fd_sc_hd__a31oi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'user_proj_example' +Circuit user_proj_example contains 555952 device instances. + Class: EZ_sky130_fd_sc_hd__and3_1 instances: 6 + Class: EZ_sky130_fd_sc_hd__and2b_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 69228 + Class: EZ_sky130_fd_sc_hd__and2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__and2_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__decap_3 instances: 1278 + Class: EZ_sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: EZ_sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: EZ_sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: EZ_sky130_fd_sc_hd__nand2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nand2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand2_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__conb_1 instances: 131 + Class: EZ_sky130_fd_sc_hd__buf_12 instances: 81 + Class: EZ_sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: EZ_sky130_ef_sc_hd__decap_40_12 instances: 275484 + Class: EZ_sky130_fd_sc_hd__a32o_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__a32o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a22o_1 instances: 7 + Class: EZ_sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__buf_1 instances: 35 + Class: EZ_sky130_fd_sc_hd__buf_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__buf_4 instances: 18 + Class: EZ_sky130_fd_sc_hd__buf_6 instances: 3 + Class: EZ_sky130_fd_sc_hd__buf_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__o211a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__mux2_1 instances: 17 + Class: EZ_sky130_fd_sc_hd__diode_2 instances: 644 + Class: EZ_sky130_fd_sc_hd__a221o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a211o_1 instances: 8 + Class: EZ_sky130_fd_sc_hd__nor2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nor2_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__inv_2 instances: 7 + Class: EZ_sky130_fd_sc_hd__nor2_8 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__a31o_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__o32a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21o_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or3_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: EZ_sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: EZ_sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__xor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or3b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__or3b_4 instances: 7 + Class: EZ_sky130_fd_sc_hd__and4_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: EZ_sky130_fd_sc_hd__and4_2 instances: 3 + Class: EZ_sky130_fd_sc_hd__and4_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__o31a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o21a_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or2_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: EZ_sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: EZ_sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: EZ_sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand4_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__fill_1 instances: 69626 + Class: EZ_sky130_fd_sc_hd__fill_2 instances: 69894 + Class: EZ_sky130_fd_sc_hd__fill_4 instances: 68575 + Class: EZ_sky130_fd_sc_hd__fill_8 instances: 505 +Circuit contains 910 nets, and 286 disconnected pins. +Contents of circuit 2: Circuit: 'user_proj_example' +Circuit user_proj_example contains 555952 device instances. + Class: sky130_fd_sc_hd__a41o_1 instances: 1 + Class: sky130_fd_sc_hd__a41o_4 instances: 1 + Class: sky130_fd_sc_hd__a31o_1 instances: 5 + Class: sky130_fd_sc_hd__a31o_2 instances: 1 + Class: sky130_fd_sc_hd__a31o_4 instances: 1 + Class: sky130_fd_sc_hd__a21o_1 instances: 2 + Class: sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_1 instances: 35 + Class: sky130_fd_sc_hd__nand4_2 instances: 1 + Class: sky130_fd_sc_hd__buf_2 instances: 2 + Class: sky130_fd_sc_hd__buf_4 instances: 18 + Class: sky130_fd_sc_hd__buf_6 instances: 3 + Class: sky130_fd_sc_hd__buf_8 instances: 2 + Class: sky130_fd_sc_hd__and3b_1 instances: 1 + Class: sky130_fd_sc_hd__and3b_4 instances: 2 + Class: sky130_fd_sc_hd__xor2_1 instances: 3 + Class: sky130_fd_sc_hd__and4_1 instances: 3 + Class: sky130_fd_sc_hd__and4_2 instances: 3 + Class: sky130_fd_sc_hd__and4_4 instances: 1 + Class: sky130_fd_sc_hd__inv_2 instances: 7 + Class: sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: sky130_fd_sc_hd__or3_4 instances: 1 + Class: sky130_fd_sc_hd__and2b_1 instances: 2 + Class: sky130_fd_sc_hd__conb_1 instances: 131 + Class: sky130_fd_sc_hd__and2b_2 instances: 1 + Class: sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_12 instances: 81 + Class: sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: sky130_fd_sc_hd__and3_1 instances: 6 + Class: sky130_fd_sc_hd__decap_3 instances: 1278 + Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: sky130_fd_sc_hd__or2_1 instances: 2 + Class: sky130_fd_sc_hd__or2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_1 instances: 5 + Class: sky130_fd_sc_hd__nand2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_8 instances: 2 + Class: sky130_fd_sc_hd__mux2_1 instances: 17 + Class: sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: sky130_fd_sc_hd__and2_1 instances: 3 + Class: sky130_fd_sc_hd__and2_2 instances: 2 + Class: sky130_fd_sc_hd__and2_4 instances: 2 + Class: sky130_fd_sc_hd__o32a_1 instances: 1 + Class: sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: sky130_fd_sc_hd__o211a_1 instances: 1 + Class: sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: sky130_fd_sc_hd__diode_2 instances: 644 + Class: sky130_fd_sc_hd__a221o_1 instances: 1 + Class: sky130_fd_sc_hd__a211o_1 instances: 8 + Class: sky130_fd_sc_hd__or3b_2 instances: 1 + Class: sky130_fd_sc_hd__or3b_4 instances: 7 + Class: sky130_fd_sc_hd__a32o_1 instances: 3 + Class: sky130_fd_sc_hd__a32o_4 instances: 1 + Class: sky130_fd_sc_hd__a22o_1 instances: 7 + Class: sky130_fd_sc_hd__o31a_1 instances: 1 + Class: sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: sky130_fd_sc_hd__o21a_1 instances: 2 + Class: sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 69228 + Class: sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: sky130_fd_sc_hd__fill_1 instances: 69626 + Class: sky130_fd_sc_hd__fill_2 instances: 69894 + Class: sky130_fd_sc_hd__fill_4 instances: 68575 + Class: sky130_fd_sc_hd__fill_8 instances: 505 + Class: sky130_ef_sc_hd__decap_40_12 instances: 275484 + Class: sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_1 instances: 5 + Class: sky130_fd_sc_hd__nor2_2 instances: 1 + Class: sky130_fd_sc_hd__nor2_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'user_proj_example' +Circuit user_proj_example contains 944 device instances. + Class: EZ_sky130_fd_sc_hd__and3_1 instances: 6 + Class: EZ_sky130_fd_sc_hd__and2b_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__and2_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__decap_3 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: EZ_sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: EZ_sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: EZ_sky130_fd_sc_hd__nand2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nand2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand2_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__conb_1 instances: 131 + Class: EZ_sky130_fd_sc_hd__buf_12 instances: 81 + Class: EZ_sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: EZ_sky130_ef_sc_hd__decap_40_12 instances: 1 + Class: EZ_sky130_fd_sc_hd__a32o_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__a32o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a22o_1 instances: 7 + Class: EZ_sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__buf_1 instances: 35 + Class: EZ_sky130_fd_sc_hd__buf_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__buf_4 instances: 18 + Class: EZ_sky130_fd_sc_hd__buf_6 instances: 3 + Class: EZ_sky130_fd_sc_hd__buf_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__o211a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__mux2_1 instances: 17 + Class: EZ_sky130_fd_sc_hd__diode_2 instances: 219 + Class: EZ_sky130_fd_sc_hd__a221o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a211o_1 instances: 8 + Class: EZ_sky130_fd_sc_hd__nor2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nor2_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__inv_2 instances: 7 + Class: EZ_sky130_fd_sc_hd__nor2_8 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__a31o_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__o32a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21o_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or3_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: EZ_sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: EZ_sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__xor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or3b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__or3b_4 instances: 7 + Class: EZ_sky130_fd_sc_hd__and4_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: EZ_sky130_fd_sc_hd__and4_2 instances: 3 + Class: EZ_sky130_fd_sc_hd__and4_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__o31a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o21a_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or2_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: EZ_sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: EZ_sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: EZ_sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand4_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__fill_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. +Contents of circuit 2: Circuit: 'user_proj_example' +Circuit user_proj_example contains 944 device instances. + Class: sky130_fd_sc_hd__a41o_1 instances: 1 + Class: sky130_fd_sc_hd__a41o_4 instances: 1 + Class: sky130_fd_sc_hd__a31o_1 instances: 5 + Class: sky130_fd_sc_hd__a31o_2 instances: 1 + Class: sky130_fd_sc_hd__a31o_4 instances: 1 + Class: sky130_fd_sc_hd__a21o_1 instances: 2 + Class: sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_1 instances: 35 + Class: sky130_fd_sc_hd__nand4_2 instances: 1 + Class: sky130_fd_sc_hd__buf_2 instances: 2 + Class: sky130_fd_sc_hd__buf_4 instances: 18 + Class: sky130_fd_sc_hd__buf_6 instances: 3 + Class: sky130_fd_sc_hd__buf_8 instances: 2 + Class: sky130_fd_sc_hd__and3b_1 instances: 1 + Class: sky130_fd_sc_hd__and3b_4 instances: 2 + Class: sky130_fd_sc_hd__xor2_1 instances: 3 + Class: sky130_fd_sc_hd__and4_1 instances: 3 + Class: sky130_fd_sc_hd__and4_2 instances: 3 + Class: sky130_fd_sc_hd__and4_4 instances: 1 + Class: sky130_fd_sc_hd__inv_2 instances: 7 + Class: sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: sky130_fd_sc_hd__or3_4 instances: 1 + Class: sky130_fd_sc_hd__and2b_1 instances: 2 + Class: sky130_fd_sc_hd__conb_1 instances: 131 + Class: sky130_fd_sc_hd__and2b_2 instances: 1 + Class: sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_12 instances: 81 + Class: sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: sky130_fd_sc_hd__and3_1 instances: 6 + Class: sky130_fd_sc_hd__decap_3 instances: 1 + Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: sky130_fd_sc_hd__or2_1 instances: 2 + Class: sky130_fd_sc_hd__or2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_1 instances: 5 + Class: sky130_fd_sc_hd__nand2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_8 instances: 2 + Class: sky130_fd_sc_hd__mux2_1 instances: 17 + Class: sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: sky130_fd_sc_hd__and2_1 instances: 3 + Class: sky130_fd_sc_hd__and2_2 instances: 2 + Class: sky130_fd_sc_hd__and2_4 instances: 2 + Class: sky130_fd_sc_hd__o32a_1 instances: 1 + Class: sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: sky130_fd_sc_hd__o211a_1 instances: 1 + Class: sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: sky130_fd_sc_hd__diode_2 instances: 219 + Class: sky130_fd_sc_hd__a221o_1 instances: 1 + Class: sky130_fd_sc_hd__a211o_1 instances: 8 + Class: sky130_fd_sc_hd__or3b_2 instances: 1 + Class: sky130_fd_sc_hd__or3b_4 instances: 7 + Class: sky130_fd_sc_hd__a32o_1 instances: 3 + Class: sky130_fd_sc_hd__a32o_4 instances: 1 + Class: sky130_fd_sc_hd__a22o_1 instances: 7 + Class: sky130_fd_sc_hd__o31a_1 instances: 1 + Class: sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: sky130_fd_sc_hd__o21a_1 instances: 2 + Class: sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1 + Class: sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: sky130_fd_sc_hd__fill_1 instances: 1 + Class: sky130_fd_sc_hd__fill_2 instances: 1 + Class: sky130_fd_sc_hd__fill_4 instances: 1 + Class: sky130_fd_sc_hd__fill_8 instances: 1 + Class: sky130_ef_sc_hd__decap_40_12 instances: 1 + Class: sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_1 instances: 5 + Class: sky130_fd_sc_hd__nor2_2 instances: 1 + Class: sky130_fd_sc_hd__nor2_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. + +Circuit 1 contains 944 devices, Circuit 2 contains 944 devices. +Circuit 1 contains 910 nets, Circuit 2 contains 910 nets. + + +Contents of circuit 1: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 543 nets, and 102 disconnected pins. +Contents of circuit 2: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 543 nets, and 102 disconnected pins. + +Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. +Circuit 1 contains 543 nets, Circuit 2 contains 543 nets. + + +Final result: +Circuits match uniquely. +. +Logging to file "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report" disabled +LVS Done. +DESIGN NAME: user_project_wrapper +WORK_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp +LOG_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs +SIGNOFF_ROOT: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports + +Running CVC... +Creating /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/user_project_wrapper.cdl.gz +Default cvcrc in default.cvcrc +CVC: Circuit Validation Check Version 1.1.7 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log +CVC: Error output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.error.gz +CVC: Debug output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.debug.gz +CVC: Start: Tue May 12 08:19:38 2026 + +Using the following parameters for CVC (Circuit Validation Check) from /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvcrc +CVC_TOP = 'user_project_wrapper' +CVC_NETLIST = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/user_project_wrapper.cdl.gz' +CVC_MODE = 'user_project_wrapper' +CVC_MODEL_FILE = '/usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models' +CVC_POWER_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.power.user_project_wrapper' +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log' +CVC_REPORT_TITLE = 'CVC user_project_wrapper' +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' +CVC_MODEL_CHECK_FILE = '' +End of parameters + +CVC: Reading device model settings... +CVC: Reading power settings... +CVC: Parsing netlist /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/user_project_wrapper.cdl.gz + +Read 77 circuits, 555952 instances, 604 devices Cdl fixed data size 9987917 +Usage CDL: Time: 3 Memory: 267508 I/O: 24 Swap: 0 +CVC: Counting and linking... +CVC: Assigning IDs ... +Usage DB: Time: 3 Memory: 318476 I/O: 24 Swap: 0 +CVC: 555954(555954) instances, 2997(2997) nets, 558967(558967) devices. +Setting power for mode... +Setting models... +CVC: Setting models ... +Setting model tolerances... +CVC: Shorting switches... + model short... + Shorted 0 short + model sky130_fd_pr__res_generic_l1... + Shorted 0 sky130_fd_pr__res_generic_l1 + model sky130_fd_pr__res_generic_m1... + Shorted 0 sky130_fd_pr__res_generic_m1 + model sky130_fd_pr__res_generic_m2... + Shorted 0 sky130_fd_pr__res_generic_m2 + model sky130_fd_pr__res_generic_m3... + Shorted 0 sky130_fd_pr__res_generic_m3 + model sky130_fd_pr__res_generic_m4... + Shorted 0 sky130_fd_pr__res_generic_m4 + model sky130_fd_pr__res_generic_m5... + Shorted 0 sky130_fd_pr__res_generic_m5 +Setting instance power... +CVC: Linking devices... + +Usage EQUIV: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 396 +CVC: Shorting non conducting resistors... +CVC: Calculating resistor voltages... +Usage RES: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 396 +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX1: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 813 +! Checking forward bias diode errors: + +! Checking nmos source/drain vs bias errors: + +! Checking nmos gate vs source errors: + +! Checking pmos source/drain vs bias errors: + +! Checking pmos gate vs source errors: + +Usage ERROR: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Saving min/max voltages... +CVC: Propagating Simulation voltages 1... +Usage SIM1: Time: 3 Memory: 347756 I/O: 88 Swap: 0 +Power nets 813 +Saving simulation voltages... +CVC: Propagating Simulation voltages 3... +Usage SIM2: Time: 3 Memory: 347756 I/O: 88 Swap: 0 +Power nets 813 +Added 0 latch voltages +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX2: Time: 3 Memory: 347756 I/O: 96 Swap: 0 +Power nets 1230 +! Checking overvoltage errors + +! Checking nmos possible leak errors: + +! Checking pmos possible leak errors: + +! Checking mos floating input errors: + +! Checking expected values: + +CVC: Error Counts +CVC: Fuse Problems: 0 +CVC: Min Voltage Conflicts: 0 +CVC: Max Voltage Conflicts: 0 +CVC: Leaks: 0 +CVC: LDD drain->source: 0 +CVC: HI-Z Inputs: 0 +CVC: Forward Bias Diodes: 0 +CVC: NMOS Source vs Bulk: 0 +CVC: NMOS Gate vs Source: 0 +CVC: NMOS Possible Leaks: 0 +CVC: PMOS Source vs Bulk: 0 +CVC: PMOS Gate vs Source: 0 +CVC: PMOS Possible Leaks: 0 +CVC: Overvoltage-VBG: 0 +CVC: Overvoltage-VBS: 0 +CVC: Overvoltage-VDS: 0 +CVC: Overvoltage-VGS: 0 +CVC: Model errors: 0 +CVC: Unexpected voltage : 0 +CVC: Total: 0 +Usage Total: Time: 4 Memory: 348328 I/O: 144 Swap: 0 +Virtual net update/access 18312/27061257 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log +CVC: End: Tue May 12 08:19:43 2026 + + +LVS result: +Final result: +Circuits match uniquely. +. +LVS Done. + +CVC result: +CVC: Total: 0 + +Runtime: 0:11:50 (hh:mm:ss) + +No errors detected diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/OEB_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/OEB_check.log new file mode 100644 index 00000000..85e2bb44 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/OEB_check.log @@ -0,0 +1,2361 @@ +DESIGN NAME: user_project_wrapper +WORK_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb +LOG_ROOT : /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs +SIGNOFF_ROOT: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports + +Running CVC for oeb check... +Creating /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz +CVC: Circuit Validation Check Version 1.1.7 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log +CVC: Error output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.error.gz +CVC: Debug output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.debug.gz +CVC: Start: Tue May 12 08:19:47 2026 + +Using the following parameters for CVC (Circuit Validation Check) from /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvcrc.oeb +CVC_TOP = 'user_project_wrapper' +CVC_NETLIST = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz' +CVC_MODE = 'user_project_wrapper' +CVC_MODEL_FILE = '/usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models' +CVC_POWER_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.power.user_project_wrapper' +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log' +CVC_REPORT_TITLE = 'CVC user_project_wrapper' +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' +CVC_MODEL_CHECK_FILE = '' +End of parameters + +CVC: Reading device model settings... +CVC: Reading power settings... +CVC: Parsing netlist /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz + +Read 77 circuits, 555952 instances, 604 devices Cdl fixed data size 9987917 +Usage CDL: Time: 3 Memory: 267528 I/O: 8 Swap: 0 +CVC: Counting and linking... +CVC: Assigning IDs ... +Usage DB: Time: 3 Memory: 318496 I/O: 8 Swap: 0 +CVC: 555954(555954) instances, 2997(2997) nets, 558967(558967) devices. +Setting power for mode... +Setting models... +CVC: Setting models ... +Setting model tolerances... +** Stage 1/7: Enter command ?> c 6 + +> c 6 +continuing for 6 step(s) +CVC: Shorting switches... + model short... + Shorted 0 short + model sky130_fd_pr__res_generic_l1... + Shorted 0 sky130_fd_pr__res_generic_l1 + model sky130_fd_pr__res_generic_m1... + Shorted 0 sky130_fd_pr__res_generic_m1 + model sky130_fd_pr__res_generic_m2... + Shorted 0 sky130_fd_pr__res_generic_m2 + model sky130_fd_pr__res_generic_m3... + Shorted 0 sky130_fd_pr__res_generic_m3 + model sky130_fd_pr__res_generic_m4... + Shorted 0 sky130_fd_pr__res_generic_m4 + model sky130_fd_pr__res_generic_m5... + Shorted 0 sky130_fd_pr__res_generic_m5 +Setting instance power... +CVC: Linking devices... + +Usage EQUIV: Time: 3 Memory: 346148 I/O: 72 Swap: 0 +Power nets 396 +CVC: Shorting non conducting resistors... +CVC: Calculating resistor voltages... +Usage RES: Time: 3 Memory: 346148 I/O: 72 Swap: 0 +Power nets 396 +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX1: Time: 3 Memory: 346148 I/O: 80 Swap: 0 +Power nets 813 +! Checking forward bias diode errors: + +! Checking nmos source/drain vs bias errors: + +! Checking nmos gate vs source errors: + +! Checking pmos source/drain vs bias errors: + +! Checking pmos gate vs source errors: + +Usage ERROR: Time: 4 Memory: 346148 I/O: 80 Swap: 0 +Saving min/max voltages... +CVC: Propagating Simulation voltages 1... +Usage SIM1: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 813 +Saving simulation voltages... +CVC: Propagating Simulation voltages 3... +Usage SIM2: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 813 +Added 0 latch voltages +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX2: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 1230 +! Checking overvoltage errors + +! Checking nmos possible leak errors: + +! Checking pmos possible leak errors: + +! Checking mos floating input errors: + +! Checking expected values: + +CVC: Error Counts +CVC: Fuse Problems: 0 +CVC: Min Voltage Conflicts: 0 +CVC: Max Voltage Conflicts: 0 +CVC: Leaks: 0 +CVC: LDD drain->source: 0 +CVC: HI-Z Inputs: 0 +CVC: Forward Bias Diodes: 0 +CVC: NMOS Source vs Bulk: 0 +CVC: NMOS Gate vs Source: 0 +CVC: NMOS Possible Leaks: 0 +CVC: PMOS Source vs Bulk: 0 +CVC: PMOS Gate vs Source: 0 +CVC: PMOS Possible Leaks: 0 +CVC: Overvoltage-VBG: 0 +CVC: Overvoltage-VBS: 0 +CVC: Overvoltage-VDS: 0 +CVC: Overvoltage-VGS: 0 +CVC: Model errors: 0 +CVC: Unexpected voltage : 0 +CVC: Total: 0 +Usage Total: Time: 4 Memory: 348908 I/O: 120 Swap: 0 +Virtual net update/access 18312/27061257 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log +CVC: End: Tue May 12 08:19:51 2026 + +** Stage 7/7: Enter command ?> gn io_in[0] + +> gn io_in[0] +Net io_in[0]: 29 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[1] + +> gn io_in[1] +Net io_in[1]: 40 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[2] + +> gn io_in[2] +Net io_in[2]: 51 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[3] + +> gn io_in[3] +Net io_in[3]: 60 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[4] + +> gn io_in[4] +Net io_in[4]: 61 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[5] + +> gn io_in[5] +Net io_in[5]: 62 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[6] + +> gn io_in[6] +Net io_in[6]: 63 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[7] + +> gn io_in[7] +Net io_in[7]: 64 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[8] + +> gn io_in[8] +Net io_in[8]: 65 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[9] + +> gn io_in[9] +Net io_in[9]: 66 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[10] + +> gn io_in[10] +Net io_in[10]: 30 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[11] + +> gn io_in[11] +Net io_in[11]: 31 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[12] + +> gn io_in[12] +Net io_in[12]: 32 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[13] + +> gn io_in[13] +Net io_in[13]: 33 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[14] + +> gn io_in[14] +Net io_in[14]: 34 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[15] + +> gn io_in[15] +Net io_in[15]: 35 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[16] + +> gn io_in[16] +Net io_in[16]: 36 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[17] + +> gn io_in[17] +Net io_in[17]: 37 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[18] + +> gn io_in[18] +Net io_in[18]: 38 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[19] + +> gn io_in[19] +Net io_in[19]: 39 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[20] + +> gn io_in[20] +Net io_in[20]: 41 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[21] + +> gn io_in[21] +Net io_in[21]: 42 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[22] + +> gn io_in[22] +Net io_in[22]: 43 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[23] + +> gn io_in[23] +Net io_in[23]: 44 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[24] + +> gn io_in[24] +Net io_in[24]: 45 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[25] + +> gn io_in[25] +Net io_in[25]: 46 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[26] + +> gn io_in[26] +Net io_in[26]: 47 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[27] + +> gn io_in[27] +Net io_in[27]: 48 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[28] + +> gn io_in[28] +Net io_in[28]: 49 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[29] + +> gn io_in[29] +Net io_in[29]: 50 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[30] + +> gn io_in[30] +Net io_in[30]: 52 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[31] + +> gn io_in[31] +Net io_in[31]: 53 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[32] + +> gn io_in[32] +Net io_in[32]: 54 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[33] + +> gn io_in[33] +Net io_in[33]: 55 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[34] + +> gn io_in[34] +Net io_in[34]: 56 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[35] + +> gn io_in[35] +Net io_in[35]: 57 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[36] + +> gn io_in[36] +Net io_in[36]: 58 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[37] + +> gn io_in[37] +Net io_in[37]: 59 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_out[0] + +> gn io_out[0] +Net io_out[0]: 105 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[0] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[0] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[0] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[0] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[1] + +> gn io_out[1] +Net io_out[1]: 116 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[1] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[1] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[1] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[1] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[2] + +> gn io_out[2] +Net io_out[2]: 127 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[2] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[2] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[2] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[2] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[3] + +> gn io_out[3] +Net io_out[3]: 136 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[3] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[3] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[3] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[3] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[4] + +> gn io_out[4] +Net io_out[4]: 137 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[4] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[4] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[4] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[4] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[5] + +> gn io_out[5] +Net io_out[5]: 138 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[5] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[5] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[5] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[5] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[6] + +> gn io_out[6] +Net io_out[6]: 139 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[6] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[6] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[6] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[6] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[7] + +> gn io_out[7] +Net io_out[7]: 140 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[7] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[7] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[7] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[7] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[8] + +> gn io_out[8] +Net io_out[8]: 141 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[9] + +> gn io_out[9] +Net io_out[9]: 142 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[10] + +> gn io_out[10] +Net io_out[10]: 106 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[11] + +> gn io_out[11] +Net io_out[11]: 107 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[12] + +> gn io_out[12] +Net io_out[12]: 108 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[13] + +> gn io_out[13] +Net io_out[13]: 109 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[14] + +> gn io_out[14] +Net io_out[14]: 110 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[15] + +> gn io_out[15] +Net io_out[15]: 111 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[16] + +> gn io_out[16] +Net io_out[16]: 112 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[17] + +> gn io_out[17] +Net io_out[17]: 113 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[18] + +> gn io_out[18] +Net io_out[18]: 114 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[19] + +> gn io_out[19] +Net io_out[19]: 115 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[20] + +> gn io_out[20] +Net io_out[20]: 117 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[21] + +> gn io_out[21] +Net io_out[21]: 118 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[22] + +> gn io_out[22] +Net io_out[22]: 119 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[23] + +> gn io_out[23] +Net io_out[23]: 120 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[24] + +> gn io_out[24] +Net io_out[24]: 121 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[25] + +> gn io_out[25] +Net io_out[25]: 122 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[26] + +> gn io_out[26] +Net io_out[26]: 123 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[27] + +> gn io_out[27] +Net io_out[27]: 124 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[28] + +> gn io_out[28] +Net io_out[28]: 125 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[29] + +> gn io_out[29] +Net io_out[29]: 126 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_out[30] + +> gn io_out[30] +Net io_out[30]: 128 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[30] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[30] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[30] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[30] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[31] + +> gn io_out[31] +Net io_out[31]: 129 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[31] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[31] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[31] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[31] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[32] + +> gn io_out[32] +Net io_out[32]: 130 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[32] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[32] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[32] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[32] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[33] + +> gn io_out[33] +Net io_out[33]: 131 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[33] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[33] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[33] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[33] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[34] + +> gn io_out[34] +Net io_out[34]: 132 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[34] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[34] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[34] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[34] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[35] + +> gn io_out[35] +Net io_out[35]: 133 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[35] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[35] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[35] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[35] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[36] + +> gn io_out[36] +Net io_out[36]: 134 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[36] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[36] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[36] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[36] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_out[37] + +> gn io_out[37] +Net io_out[37]: 135 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[37] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[37] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[37] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[37] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[0] + +> gn io_oeb[0] +Net io_oeb[0]: 67 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[0] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[0] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[0] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[0] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[1] + +> gn io_oeb[1] +Net io_oeb[1]: 78 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[1] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[1] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[1] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[1] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[2] + +> gn io_oeb[2] +Net io_oeb[2]: 89 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[2] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[2] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[2] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[2] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[3] + +> gn io_oeb[3] +Net io_oeb[3]: 98 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[3] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[3] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[3] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[3] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[4] + +> gn io_oeb[4] +Net io_oeb[4]: 99 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[4] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[4] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[4] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[4] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[5] + +> gn io_oeb[5] +Net io_oeb[5]: 100 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[5] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[5] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[5] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[5] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[6] + +> gn io_oeb[6] +Net io_oeb[6]: 101 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[6] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[6] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[6] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[6] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[7] + +> gn io_oeb[7] +Net io_oeb[7]: 102 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[7] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[7] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[7] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[7] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[8] + +> gn io_oeb[8] +Net io_oeb[8]: 103 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[9] + +> gn io_oeb[9] +Net io_oeb[9]: 104 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[10] + +> gn io_oeb[10] +Net io_oeb[10]: 68 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[11] + +> gn io_oeb[11] +Net io_oeb[11]: 69 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[12] + +> gn io_oeb[12] +Net io_oeb[12]: 70 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[13] + +> gn io_oeb[13] +Net io_oeb[13]: 71 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[14] + +> gn io_oeb[14] +Net io_oeb[14]: 72 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[15] + +> gn io_oeb[15] +Net io_oeb[15]: 73 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[16] + +> gn io_oeb[16] +Net io_oeb[16]: 74 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[17] + +> gn io_oeb[17] +Net io_oeb[17]: 75 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[18] + +> gn io_oeb[18] +Net io_oeb[18]: 76 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[19] + +> gn io_oeb[19] +Net io_oeb[19]: 77 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[20] + +> gn io_oeb[20] +Net io_oeb[20]: 79 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[21] + +> gn io_oeb[21] +Net io_oeb[21]: 80 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[22] + +> gn io_oeb[22] +Net io_oeb[22]: 81 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[23] + +> gn io_oeb[23] +Net io_oeb[23]: 82 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[24] + +> gn io_oeb[24] +Net io_oeb[24]: 83 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[25] + +> gn io_oeb[25] +Net io_oeb[25]: 84 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[26] + +> gn io_oeb[26] +Net io_oeb[26]: 85 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[27] + +> gn io_oeb[27] +Net io_oeb[27]: 86 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[28] + +> gn io_oeb[28] +Net io_oeb[28]: 87 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[29] + +> gn io_oeb[29] +Net io_oeb[29]: 88 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn io_oeb[30] + +> gn io_oeb[30] +Net io_oeb[30]: 90 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[30] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[30] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[30] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[30] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[31] + +> gn io_oeb[31] +Net io_oeb[31]: 91 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[31] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[31] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[31] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[31] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[32] + +> gn io_oeb[32] +Net io_oeb[32]: 92 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[32] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[32] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[32] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[32] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[33] + +> gn io_oeb[33] +Net io_oeb[33]: 93 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[33] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[33] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[33] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[33] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[34] + +> gn io_oeb[34] +Net io_oeb[34]: 94 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[34] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[34] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[34] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[34] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[35] + +> gn io_oeb[35] +Net io_oeb[35]: 95 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[35] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[35] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[35] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[35] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[36] + +> gn io_oeb[36] +Net io_oeb[36]: 96 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[36] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[36] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[36] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[36] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_oeb[37] + +> gn io_oeb[37] +Net io_oeb[37]: 97 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[37] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[37] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[37] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[37] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + +** Stage 7/7: Enter command ?> gn io_in[0] + +> gn io_in[0] +Net io_in[0]: 29 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[1] + +> gn io_in[1] +Net io_in[1]: 40 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[2] + +> gn io_in[2] +Net io_in[2]: 51 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[3] + +> gn io_in[3] +Net io_in[3]: 60 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[4] + +> gn io_in[4] +Net io_in[4]: 61 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[5] + +> gn io_in[5] +Net io_in[5]: 62 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[6] + +> gn io_in[6] +Net io_in[6]: 63 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[7] + +> gn io_in[7] +Net io_in[7]: 64 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[8] + +> gn io_in[8] +Net io_in[8]: 65 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[9] + +> gn io_in[9] +Net io_in[9]: 66 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[10] + +> gn io_in[10] +Net io_in[10]: 30 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[11] + +> gn io_in[11] +Net io_in[11]: 31 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[12] + +> gn io_in[12] +Net io_in[12]: 32 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[13] + +> gn io_in[13] +Net io_in[13]: 33 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[14] + +> gn io_in[14] +Net io_in[14]: 34 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[15] + +> gn io_in[15] +Net io_in[15]: 35 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[16] + +> gn io_in[16] +Net io_in[16]: 36 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[17] + +> gn io_in[17] +Net io_in[17]: 37 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[18] + +> gn io_in[18] +Net io_in[18]: 38 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[19] + +> gn io_in[19] +Net io_in[19]: 39 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[20] + +> gn io_in[20] +Net io_in[20]: 41 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[21] + +> gn io_in[21] +Net io_in[21]: 42 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[22] + +> gn io_in[22] +Net io_in[22]: 43 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[23] + +> gn io_in[23] +Net io_in[23]: 44 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[24] + +> gn io_in[24] +Net io_in[24]: 45 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[25] + +> gn io_in[25] +Net io_in[25]: 46 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[26] + +> gn io_in[26] +Net io_in[26]: 47 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[27] + +> gn io_in[27] +Net io_in[27]: 48 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[28] + +> gn io_in[28] +Net io_in[28]: 49 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[29] + +> gn io_in[29] +Net io_in[29]: 50 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[30] + +> gn io_in[30] +Net io_in[30]: 52 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[31] + +> gn io_in[31] +Net io_in[31]: 53 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[32] + +> gn io_in[32] +Net io_in[32]: 54 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[33] + +> gn io_in[33] +Net io_in[33]: 55 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[34] + +> gn io_in[34] +Net io_in[34]: 56 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[35] + +> gn io_in[35] +Net io_in[35]: 57 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[36] + +> gn io_in[36] +Net io_in[36]: 58 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn io_in[37] + +> gn io_in[37] +Net io_in[37]: 59 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + +** Stage 7/7: Enter command ?> gn analog_io[0] + +> gn analog_io[0] +Net analog_io[0]: 0 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[1] + +> gn analog_io[1] +Net analog_io[1]: 11 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[2] + +> gn analog_io[2] +Net analog_io[2]: 21 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[3] + +> gn analog_io[3] +Net analog_io[3]: 22 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[4] + +> gn analog_io[4] +Net analog_io[4]: 23 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[5] + +> gn analog_io[5] +Net analog_io[5]: 24 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[6] + +> gn analog_io[6] +Net analog_io[6]: 25 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[7] + +> gn analog_io[7] +Net analog_io[7]: 26 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[8] + +> gn analog_io[8] +Net analog_io[8]: 27 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[9] + +> gn analog_io[9] +Net analog_io[9]: 28 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[10] + +> gn analog_io[10] +Net analog_io[10]: 1 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[11] + +> gn analog_io[11] +Net analog_io[11]: 2 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[12] + +> gn analog_io[12] +Net analog_io[12]: 3 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[13] + +> gn analog_io[13] +Net analog_io[13]: 4 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[14] + +> gn analog_io[14] +Net analog_io[14]: 5 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[15] + +> gn analog_io[15] +Net analog_io[15]: 6 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[16] + +> gn analog_io[16] +Net analog_io[16]: 7 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[17] + +> gn analog_io[17] +Net analog_io[17]: 8 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[18] + +> gn analog_io[18] +Net analog_io[18]: 9 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[19] + +> gn analog_io[19] +Net analog_io[19]: 10 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[20] + +> gn analog_io[20] +Net analog_io[20]: 12 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[21] + +> gn analog_io[21] +Net analog_io[21]: 13 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[22] + +> gn analog_io[22] +Net analog_io[22]: 14 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[23] + +> gn analog_io[23] +Net analog_io[23]: 15 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[24] + +> gn analog_io[24] +Net analog_io[24]: 16 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[25] + +> gn analog_io[25] +Net analog_io[25]: 17 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[26] + +> gn analog_io[26] +Net analog_io[26]: 18 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[27] + +> gn analog_io[27] +Net analog_io[27]: 19 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> gn analog_io[28] + +> gn analog_io[28] +Net analog_io[28]: 20 + connections: gate 0 source 0 drain 0 bulk 0 + +** Stage 7/7: Enter command ?> q + +> q + gpio/user/analog | in | out | analog | oeb min/sim/max | configuration + 0 / 0 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 1 / 1 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 2 / 2 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 3 / 3 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_PULLUP 2 warnings/errors + 4 / 4 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 5 / 5 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 6 / 6 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 7 / 7 / 0 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 8 / 8 / 1 | | | | / / | INVALID missing mode 1 warnings/errors + 9 / 9 / 2 | | | | / / | INVALID missing mode 1 warnings/errors + 10 / 10 / 3 | | | | / / | INVALID missing mode 1 warnings/errors + 11 / 11 / 4 | | | | / / | INVALID missing mode 1 warnings/errors + 12 / 12 / 5 | | | | / / | INVALID missing mode 1 warnings/errors + 13 / 13 / 6 | | | | / / | INVALID missing mode 1 warnings/errors + 14 / 14 / 7 | | | | / / | INVALID missing mode 1 warnings/errors + 15 / 15 / 8 | | | | / / | INVALID missing mode 1 warnings/errors + 16 / 16 / 9 | | | | / / | INVALID missing mode 1 warnings/errors + 17 / 17 / 10 | | | | / / | INVALID missing mode 1 warnings/errors + 18 / 18 / 11 | | | | / / | INVALID missing mode 1 warnings/errors + 19 / 19 / 12 | | | | / / | INVALID missing mode 1 warnings/errors + 20 / 20 / 13 | | | | / / | INVALID missing mode 1 warnings/errors + 21 / 21 / 14 | | | | / / | INVALID missing mode 1 warnings/errors + 22 / 22 / 15 | | | | / / | INVALID missing mode 1 warnings/errors + 23 / 23 / 16 | | | | / / | INVALID missing mode 1 warnings/errors + 24 / 24 / 17 | | | | / / | INVALID missing mode 1 warnings/errors + 25 / 25 / 18 | | | | / / | INVALID missing mode 1 warnings/errors + 26 / 26 / 19 | | | | / / | INVALID missing mode 1 warnings/errors + 27 / 27 / 20 | | | | / / | INVALID missing mode 1 warnings/errors + 28 / 28 / 21 | | | | / / | INVALID missing mode 1 warnings/errors + 29 / 29 / 22 | | | | / / | INVALID missing mode 1 warnings/errors + 30 / 30 / 23 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 31 / 31 / 24 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 32 / 32 / 25 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 33 / 33 / 26 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 34 / 34 / 27 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 35 / 35 / 28 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 36 / 36 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 37 / 37 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + +*** Detected the following warnings and/or errors: *** +GPIO 0: Warning: user output connection to fixed input gpio - firmware override required +GPIO 0: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 1: Warning: user output connection to fixed input gpio - firmware override required +GPIO 1: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 2: Warning: user output connection to fixed input gpio - firmware override required +GPIO 2: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 3: Warning: user output connection to fixed input gpio - firmware override required +GPIO 3: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 4: Warning: user output connection to fixed input gpio - firmware override required +GPIO 4: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 5: ERROR: missing gpio configuration +GPIO 6: ERROR: missing gpio configuration +GPIO 7: ERROR: missing gpio configuration +GPIO 8: ERROR: missing gpio configuration +GPIO 9: ERROR: missing gpio configuration +GPIO 10: ERROR: missing gpio configuration +GPIO 11: ERROR: missing gpio configuration +GPIO 12: ERROR: missing gpio configuration +GPIO 13: ERROR: missing gpio configuration +GPIO 14: ERROR: missing gpio configuration +GPIO 15: ERROR: missing gpio configuration +GPIO 16: ERROR: missing gpio configuration +GPIO 17: ERROR: missing gpio configuration +GPIO 18: ERROR: missing gpio configuration +GPIO 19: ERROR: missing gpio configuration +GPIO 20: ERROR: missing gpio configuration +GPIO 21: ERROR: missing gpio configuration +GPIO 22: ERROR: missing gpio configuration +GPIO 23: ERROR: missing gpio configuration +GPIO 24: ERROR: missing gpio configuration +GPIO 25: ERROR: missing gpio configuration +GPIO 26: ERROR: missing gpio configuration +GPIO 27: ERROR: missing gpio configuration +GPIO 28: ERROR: missing gpio configuration +GPIO 29: ERROR: missing gpio configuration +GPIO 30: ERROR: missing gpio configuration +GPIO 31: ERROR: missing gpio configuration +GPIO 32: ERROR: missing gpio configuration +GPIO 33: ERROR: missing gpio configuration +GPIO 34: ERROR: missing gpio configuration +GPIO 35: ERROR: missing gpio configuration +GPIO 36: ERROR: missing gpio configuration +GPIO 37: ERROR: missing gpio configuration diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/cvc.log b/precheck_results/12_MAY_2026___07_45_39/logs/cvc.log new file mode 100644 index 00000000..6c000a6c --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/cvc.log @@ -0,0 +1,651 @@ +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log +CVC: Error output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.error.gz +CVC: Debug output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.debug.gz +CVC: Circuit Validation Check Version 1.1.7 +CVC: Start: Tue May 12 08:19:38 2026 + +Using the following parameters for CVC (Circuit Validation Check) from /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvcrc +CVC_TOP = 'user_project_wrapper' +CVC_NETLIST = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/user_project_wrapper.cdl.gz' +CVC_MODE = 'user_project_wrapper' +CVC_MODEL_FILE = '/usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models' +CVC_POWER_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.power.user_project_wrapper' +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log' +CVC_REPORT_TITLE = 'CVC user_project_wrapper' +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' +CVC_MODEL_CHECK_FILE = '' +End of parameters + +CVC: Reading device model settings... +CVC: Reading power settings... +CVC: Parsing netlist /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/user_project_wrapper.cdl.gz +Cdl fixed data size 9987917 +Usage CDL: Time: 3 Memory: 267508 I/O: 24 Swap: 0 +CVC: Counting and linking... +CVC: Assigning IDs ... +Usage DB: Time: 3 Memory: 318476 I/O: 24 Swap: 0 +CVC: 555954(555954) instances, 2997(2997) nets, 558967(558967) devices. +CVC: Setting models ... +Setting model tolerances... +CVC: Shorting switches... + Shorted 0 short + Shorted 0 sky130_fd_pr__res_generic_l1 + Shorted 0 sky130_fd_pr__res_generic_m1 + Shorted 0 sky130_fd_pr__res_generic_m2 + Shorted 0 sky130_fd_pr__res_generic_m3 + Shorted 0 sky130_fd_pr__res_generic_m4 + Shorted 0 sky130_fd_pr__res_generic_m5 +Setting instance power... + +ModelList> filename /usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models + Model> sky130_fd_pr__cap_mim_m3_1 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_mim_m3_2 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_var 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_var_lvt 0 C->capacitor Parameters> + Model> condiode 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_05v5 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_05v5_lvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_11v0 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5 644 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5_lvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5_nvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_11v0 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_ps2dn 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_ps2nw 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_pw2dn 0 D->diode Parameters> Diodes> 1-2 + Model> nfet_01v8 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> pfet_01v8_hvt 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_bs_flash__special_sonosfet_star 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__esd_nfet_g5v0d10v5 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_01v8 278902 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_01v8_lvt 0 M->nmos Parameters> Vth=0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_03v3_nvt 0 M->nmos Parameters> Vth=0.2 Vds=3.3 Vgs=3.3 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_05v0_nvt 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_g5v0d10v5 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__pfet_01v8 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_01v8_hvt 279027 M->pmos Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_01v8_lvt 0 M->pmos Parameters> Vth=-0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_g5v0d10v5 0 M->pmos Parameters> Vth=-0.2 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_nfet_01v8 132 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_nfet_latch 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_nfet_pass 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_pfet_01v8_hvt 0 M->pmos Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_pfet_latch 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_pfet_pass 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__npn_11v0 0 Q->bipolar Parameters> + Model> sky130_fd_pr__npn_11v0_W1p00L1p00 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5_W0p68L0p68 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5_W3p40L3p40 0 Q->bipolar Parameters> + Model> short 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_l1 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m1 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m2 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m3 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m4 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m5 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_nd 0 R->resistor Parameters> R=l/w*120 + Model> sky130_fd_pr__res_generic_nd__hv 0 R->resistor Parameters> R=l/w*114 + Model> sky130_fd_pr__res_generic_pd 0 R->resistor Parameters> R=l/w*197 + Model> sky130_fd_pr__res_generic_pd__hv 0 R->resistor Parameters> R=l/w*191 + Model> sky130_fd_pr__res_generic_po 262 R->resistor Parameters> R=l/w*48 + Model> sky130_fd_pr__res_high_po 0 R->resistor Parameters> R=l/w*300 + Model> sky130_fd_pr__res_high_po_0p35 0 R->resistor Parameters> R=l/0.35*300 + Model> sky130_fd_pr__res_high_po_0p69 0 R->resistor Parameters> R=l/0.69*300 + Model> sky130_fd_pr__res_high_po_1p41 0 R->resistor Parameters> R=l/1.41*300 + Model> sky130_fd_pr__res_high_po_2p85 0 R->resistor Parameters> R=l/2.85*300 + Model> sky130_fd_pr__res_high_po_5p73 0 R->resistor Parameters> R=l/5.73*300 + Model> sky130_fd_pr__res_iso_pw 0 R->resistor Parameters> R=l/w*4400 + Model> sky130_fd_pr__res_xhigh_po 0 R->resistor Parameters> R=l/w*2000 + Model> sky130_fd_pr__res_xhigh_po_0p35 0 R->resistor Parameters> R=l/0.35*2000 + Model> sky130_fd_pr__res_xhigh_po_0p69 0 R->resistor Parameters> R=l/0.69*2000 + Model> sky130_fd_pr__res_xhigh_po_1p41 0 R->resistor Parameters> R=l/1.41*2000 + Model> sky130_fd_pr__res_xhigh_po_2p85 0 R->resistor Parameters> R=l/2.85*2000 + Model> sky130_fd_pr__res_xhigh_po_5p73 0 R->resistor Parameters> R=l/5.73*2000 +ModelList> end + +Power List> filename /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.power.user_project_wrapper +vccd* power 1.8 + ->vccd1 power 1.8 -> 1.8 power + ->vccd2 power 1.8 -> 1.8 power +vdda* power 3.3 + ->vdda1 power 3.3 -> 3.3 power + ->vdda2 power 3.3 -> 3.3 power +vssa* power 0.0 + ->vssa1 power 0.0 -> 0.0 power + ->vssa2 power 0.0 -> 0.0 power +vssd* power 0.0 + ->vssd1 power 0.0 -> 0.0 power + ->vssd2 power 0.0 -> 0.0 power + user_clock2 input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wb_clk_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wb_rst_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_cyc_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_stb_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_we_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input +io_in[*] input min@0.0 max@1.8 + ->io_in[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +la_data_in[*] input min@0.0 max@1.8 + ->la_data_in[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[100] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[101] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[102] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[103] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[104] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[105] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[106] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[107] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[108] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[109] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[110] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[111] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[112] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[113] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[114] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[115] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[116] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[117] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[118] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[119] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[120] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[121] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[122] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[123] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[124] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[125] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[126] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[127] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[38] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[39] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[40] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[41] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[42] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[43] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[44] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[45] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[46] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[47] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[48] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[49] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[50] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[51] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[52] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[53] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[54] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[55] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[56] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[57] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[58] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[59] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[60] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[61] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[62] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[63] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[64] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[65] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[66] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[67] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[68] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[69] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[70] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[71] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[72] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[73] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[74] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[75] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[76] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[77] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[78] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[79] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[80] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[81] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[82] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[83] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[84] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[85] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[86] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[87] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[88] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[89] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[90] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[91] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[92] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[93] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[94] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[95] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[96] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[97] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[98] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[99] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +la_oenb[*] input min@0.0 max@1.8 + ->la_oenb[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[100] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[101] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[102] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[103] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[104] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[105] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[106] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[107] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[108] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[109] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[110] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[111] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[112] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[113] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[114] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[115] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[116] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[117] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[118] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[119] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[120] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[121] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[122] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[123] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[124] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[125] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[126] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[127] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[38] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[39] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[40] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[41] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[42] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[43] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[44] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[45] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[46] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[47] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[48] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[49] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[50] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[51] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[52] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[53] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[54] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[55] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[56] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[57] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[58] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[59] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[60] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[61] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[62] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[63] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[64] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[65] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[66] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[67] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[68] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[69] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[70] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[71] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[72] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[73] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[74] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[75] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[76] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[77] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[78] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[79] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[80] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[81] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[82] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[83] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[84] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[85] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[86] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[87] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[88] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[89] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[90] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[91] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[92] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[93] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[94] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[95] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[96] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[97] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[98] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[99] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_adr_i[*] input min@0.0 max@1.8 + ->wbs_adr_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_dat_i[*] input min@0.0 max@1.8 + ->wbs_dat_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_sel_i[*] input min@0.0 max@1.8 + ->wbs_sel_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +> expected values +io_out[6:0] expectMin@0.0 expectMax@1.8 + ->io_out[0] expectMin@0.0 expectMax@1.8 + ->io_out[1] expectMin@0.0 expectMax@1.8 + ->io_out[2] expectMin@0.0 expectMax@1.8 + ->io_out[3] expectMin@0.0 expectMax@1.8 + ->io_out[4] expectMin@0.0 expectMax@1.8 + ->io_out[5] expectMin@0.0 expectMax@1.8 + ->io_out[6] expectMin@0.0 expectMax@1.8 +io_oeb[6:0] expectMin@0.0 expectMax@1.8 + ->io_oeb[0] expectMin@0.0 expectMax@1.8 + ->io_oeb[1] expectMin@0.0 expectMax@1.8 + ->io_oeb[2] expectMin@0.0 expectMax@1.8 + ->io_oeb[3] expectMin@0.0 expectMax@1.8 + ->io_oeb[4] expectMin@0.0 expectMax@1.8 + ->io_oeb[5] expectMin@0.0 expectMax@1.8 + ->io_oeb[6] expectMin@0.0 expectMax@1.8 +> macros +Power List> end + +CVC: Linking devices... +Usage EQUIV: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 396 +Hash dump:parameter->resistance map +Contains 193 buckets, 384 elements +Element count 0, 3 +Element count 1, 79 +Element count 2, 64 +Element count 3, 24 +Element count 4, 12 +Element count 5, 9 +Element count 6, 2 +Unused hash: 0.02, average depth 2.71 +Hash dump:text->circuit map +Contains 79 buckets, 82 elements +Element count 0, 20 +Element count 1, 42 +Element count 2, 12 +Element count 3, 4 +Element count 4, 1 +Unused hash: 0.25, average depth 1.73 +Hash dump:string->text map +Contains 444487 buckets, 558146 elements +Element count 0, 127129 +Element count 1, 158275 +Element count 2, 99816 +Element count 3, 41875 +Element count 4, 13318 +Element count 5, 3266 +Element count 6, 663 +Element count 7, 128 +Element count 8, 15 +Element count 9, 2 +Unused hash: 0.29, average depth 2.26 +CVC: Shorting non conducting resistors... +CVC: Calculating resistor voltages... +Usage RES: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 396 +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX1: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +Power nets 813 +! Checking forward bias diode errors: + +! Checking nmos source/drain vs bias errors: + +! Checking nmos gate vs source errors: + +! Checking pmos source/drain vs bias errors: + +! Checking pmos gate vs source errors: + +Usage ERROR: Time: 3 Memory: 345320 I/O: 88 Swap: 0 +CVC: Propagating Simulation voltages 1... +Usage SIM1: Time: 3 Memory: 347756 I/O: 88 Swap: 0 +Power nets 813 +CVC: Propagating Simulation voltages 3... +Usage SIM2: Time: 3 Memory: 347756 I/O: 88 Swap: 0 +Power nets 813 +Added 0 latch voltages +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX2: Time: 3 Memory: 347756 I/O: 96 Swap: 0 +Power nets 1230 +! Checking overvoltage errors + +! Checking nmos possible leak errors: + +! Checking pmos possible leak errors: + +! Checking mos floating input errors: + +! Checking expected values: + +CVC: Error Counts +CVC: Fuse Problems: 0 +CVC: Min Voltage Conflicts: 0 +CVC: Max Voltage Conflicts: 0 +CVC: Leaks: 0 +CVC: LDD drain->source: 0 +CVC: HI-Z Inputs: 0 +CVC: Forward Bias Diodes: 0 +CVC: NMOS Source vs Bulk: 0 +CVC: NMOS Gate vs Source: 0 +CVC: NMOS Possible Leaks: 0 +CVC: PMOS Source vs Bulk: 0 +CVC: PMOS Gate vs Source: 0 +CVC: PMOS Possible Leaks: 0 +CVC: Overvoltage-VBG: 0 +CVC: Overvoltage-VBS: 0 +CVC: Overvoltage-VDS: 0 +CVC: Overvoltage-VGS: 0 +CVC: Model errors: 0 +CVC: Unexpected voltage : 0 +CVC: Total: 0 +Usage Total: Time: 4 Memory: 348328 I/O: 144 Swap: 0 +Virtual net update/access 18312/27061257 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/cvc.log +CVC: End: Tue May 12 08:19:43 2026 + +Runtime: 0:00:05 (hh:mm:ss) diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/cvc.oeb.log b/precheck_results/12_MAY_2026___07_45_39/logs/cvc.oeb.log new file mode 100644 index 00000000..7eb77f8b --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/cvc.oeb.log @@ -0,0 +1,2580 @@ +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log +CVC: Error output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.error.gz +CVC: Debug output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.debug.gz +CVC: Circuit Validation Check Version 1.1.7 +CVC: Start: Tue May 12 08:19:47 2026 + +Using the following parameters for CVC (Circuit Validation Check) from /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvcrc.oeb +CVC_TOP = 'user_project_wrapper' +CVC_NETLIST = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz' +CVC_MODE = 'user_project_wrapper' +CVC_MODEL_FILE = '/usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models' +CVC_POWER_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.power.user_project_wrapper' +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = '/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log' +CVC_REPORT_TITLE = 'CVC user_project_wrapper' +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' +CVC_MODEL_CHECK_FILE = '' +End of parameters + +CVC: Reading device model settings... +CVC: Reading power settings... +CVC: Parsing netlist /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/user_project_wrapper.cdl.gz +Cdl fixed data size 9987917 +Usage CDL: Time: 3 Memory: 267528 I/O: 8 Swap: 0 +CVC: Counting and linking... +CVC: Assigning IDs ... +Usage DB: Time: 3 Memory: 318496 I/O: 8 Swap: 0 +CVC: 555954(555954) instances, 2997(2997) nets, 558967(558967) devices. +CVC: Setting models ... +Setting model tolerances... + +> c 6 +CVC: Shorting switches... + Shorted 0 short + Shorted 0 sky130_fd_pr__res_generic_l1 + Shorted 0 sky130_fd_pr__res_generic_m1 + Shorted 0 sky130_fd_pr__res_generic_m2 + Shorted 0 sky130_fd_pr__res_generic_m3 + Shorted 0 sky130_fd_pr__res_generic_m4 + Shorted 0 sky130_fd_pr__res_generic_m5 +Setting instance power... + +ModelList> filename /usr/local/lib/python3.9/site-packages/cf_precheck/be_checks/tech/sky130A/cvc.models + Model> sky130_fd_pr__cap_mim_m3_1 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_mim_m3_2 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_var 0 C->capacitor Parameters> + Model> sky130_fd_pr__cap_var_lvt 0 C->capacitor Parameters> + Model> condiode 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_05v5 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_05v5_lvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pd2nw_11v0 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5 644 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5_lvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_05v5_nvt 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__diode_pw2nd_11v0 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_ps2dn 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_ps2nw 0 D->diode Parameters> Diodes> 1-2 + Model> sky130_fd_pr__model__parasitic__diode_pw2dn 0 D->diode Parameters> Diodes> 1-2 + Model> nfet_01v8 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> pfet_01v8_hvt 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_bs_flash__special_sonosfet_star 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__esd_nfet_g5v0d10v5 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_01v8 278902 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_01v8_lvt 0 M->nmos Parameters> Vth=0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_03v3_nvt 0 M->nmos Parameters> Vth=0.2 Vds=3.3 Vgs=3.3 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_05v0_nvt 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__nfet_g5v0d10v5 0 M->nmos Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__pfet_01v8 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_01v8_hvt 279027 M->pmos Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_01v8_lvt 0 M->pmos Parameters> Vth=-0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__pfet_g5v0d10v5 0 M->pmos Parameters> Vth=-0.2 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_nfet_01v8 132 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_nfet_latch 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_nfet_pass 0 M->nmos Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3 + Model> sky130_fd_pr__special_pfet_01v8_hvt 0 M->pmos Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_pfet_latch 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__special_pfet_pass 0 M->pmos Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4 + Model> sky130_fd_pr__npn_11v0 0 Q->bipolar Parameters> + Model> sky130_fd_pr__npn_11v0_W1p00L1p00 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5_W0p68L0p68 0 Q->bipolar Parameters> + Model> sky130_fd_pr__pnp_05v5_W3p40L3p40 0 Q->bipolar Parameters> + Model> short 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_l1 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m1 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m2 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m3 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m4 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_m5 0 R->switch_on Parameters> + Model> sky130_fd_pr__res_generic_nd 0 R->resistor Parameters> R=l/w*120 + Model> sky130_fd_pr__res_generic_nd__hv 0 R->resistor Parameters> R=l/w*114 + Model> sky130_fd_pr__res_generic_pd 0 R->resistor Parameters> R=l/w*197 + Model> sky130_fd_pr__res_generic_pd__hv 0 R->resistor Parameters> R=l/w*191 + Model> sky130_fd_pr__res_generic_po 262 R->resistor Parameters> R=l/w*48 + Model> sky130_fd_pr__res_high_po 0 R->resistor Parameters> R=l/w*300 + Model> sky130_fd_pr__res_high_po_0p35 0 R->resistor Parameters> R=l/0.35*300 + Model> sky130_fd_pr__res_high_po_0p69 0 R->resistor Parameters> R=l/0.69*300 + Model> sky130_fd_pr__res_high_po_1p41 0 R->resistor Parameters> R=l/1.41*300 + Model> sky130_fd_pr__res_high_po_2p85 0 R->resistor Parameters> R=l/2.85*300 + Model> sky130_fd_pr__res_high_po_5p73 0 R->resistor Parameters> R=l/5.73*300 + Model> sky130_fd_pr__res_iso_pw 0 R->resistor Parameters> R=l/w*4400 + Model> sky130_fd_pr__res_xhigh_po 0 R->resistor Parameters> R=l/w*2000 + Model> sky130_fd_pr__res_xhigh_po_0p35 0 R->resistor Parameters> R=l/0.35*2000 + Model> sky130_fd_pr__res_xhigh_po_0p69 0 R->resistor Parameters> R=l/0.69*2000 + Model> sky130_fd_pr__res_xhigh_po_1p41 0 R->resistor Parameters> R=l/1.41*2000 + Model> sky130_fd_pr__res_xhigh_po_2p85 0 R->resistor Parameters> R=l/2.85*2000 + Model> sky130_fd_pr__res_xhigh_po_5p73 0 R->resistor Parameters> R=l/5.73*2000 +ModelList> end + +Power List> filename /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.power.user_project_wrapper +vccd* power 1.8 + ->vccd1 power 1.8 -> 1.8 power + ->vccd2 power 1.8 -> 1.8 power +vdda* power 3.3 + ->vdda1 power 3.3 -> 3.3 power + ->vdda2 power 3.3 -> 3.3 power +vssa* power 0.0 + ->vssa1 power 0.0 -> 0.0 power + ->vssa2 power 0.0 -> 0.0 power +vssd* power 0.0 + ->vssd1 power 0.0 -> 0.0 power + ->vssd2 power 0.0 -> 0.0 power + user_clock2 input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wb_clk_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wb_rst_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_cyc_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_stb_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input + wbs_we_i input min@0.0 max@1.8 -> min@0.0 max@1.8 input +io_in[*] input min@0.0 max@1.8 + ->io_in[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->io_in[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +la_data_in[*] input min@0.0 max@1.8 + ->la_data_in[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[100] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[101] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[102] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[103] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[104] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[105] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[106] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[107] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[108] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[109] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[110] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[111] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[112] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[113] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[114] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[115] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[116] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[117] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[118] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[119] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[120] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[121] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[122] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[123] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[124] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[125] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[126] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[127] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[38] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[39] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[40] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[41] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[42] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[43] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[44] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[45] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[46] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[47] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[48] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[49] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[50] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[51] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[52] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[53] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[54] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[55] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[56] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[57] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[58] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[59] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[60] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[61] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[62] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[63] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[64] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[65] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[66] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[67] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[68] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[69] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[70] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[71] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[72] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[73] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[74] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[75] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[76] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[77] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[78] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[79] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[80] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[81] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[82] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[83] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[84] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[85] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[86] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[87] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[88] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[89] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[90] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[91] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[92] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[93] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[94] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[95] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[96] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[97] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[98] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[99] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_data_in[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +la_oenb[*] input min@0.0 max@1.8 + ->la_oenb[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[100] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[101] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[102] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[103] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[104] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[105] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[106] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[107] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[108] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[109] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[110] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[111] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[112] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[113] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[114] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[115] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[116] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[117] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[118] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[119] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[120] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[121] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[122] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[123] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[124] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[125] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[126] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[127] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[32] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[33] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[34] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[35] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[36] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[37] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[38] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[39] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[40] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[41] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[42] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[43] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[44] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[45] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[46] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[47] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[48] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[49] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[50] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[51] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[52] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[53] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[54] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[55] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[56] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[57] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[58] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[59] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[60] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[61] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[62] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[63] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[64] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[65] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[66] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[67] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[68] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[69] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[70] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[71] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[72] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[73] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[74] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[75] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[76] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[77] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[78] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[79] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[80] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[81] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[82] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[83] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[84] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[85] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[86] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[87] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[88] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[89] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[90] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[91] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[92] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[93] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[94] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[95] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[96] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[97] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[98] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[99] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->la_oenb[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_adr_i[*] input min@0.0 max@1.8 + ->wbs_adr_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_adr_i[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_dat_i[*] input min@0.0 max@1.8 + ->wbs_dat_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[10] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[11] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[12] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[13] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[14] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[15] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[16] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[17] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[18] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[19] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[20] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[21] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[22] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[23] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[24] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[25] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[26] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[27] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[28] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[29] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[30] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[31] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[4] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[5] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[6] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[7] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[8] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_dat_i[9] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +wbs_sel_i[*] input min@0.0 max@1.8 + ->wbs_sel_i[0] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[1] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[2] input min@0.0 max@1.8 -> min@0.0 max@1.8 input + ->wbs_sel_i[3] input min@0.0 max@1.8 -> min@0.0 max@1.8 input +> expected values +io_out[6:0] expectMin@0.0 expectMax@1.8 + ->io_out[0] expectMin@0.0 expectMax@1.8 + ->io_out[1] expectMin@0.0 expectMax@1.8 + ->io_out[2] expectMin@0.0 expectMax@1.8 + ->io_out[3] expectMin@0.0 expectMax@1.8 + ->io_out[4] expectMin@0.0 expectMax@1.8 + ->io_out[5] expectMin@0.0 expectMax@1.8 + ->io_out[6] expectMin@0.0 expectMax@1.8 +io_oeb[6:0] expectMin@0.0 expectMax@1.8 + ->io_oeb[0] expectMin@0.0 expectMax@1.8 + ->io_oeb[1] expectMin@0.0 expectMax@1.8 + ->io_oeb[2] expectMin@0.0 expectMax@1.8 + ->io_oeb[3] expectMin@0.0 expectMax@1.8 + ->io_oeb[4] expectMin@0.0 expectMax@1.8 + ->io_oeb[5] expectMin@0.0 expectMax@1.8 + ->io_oeb[6] expectMin@0.0 expectMax@1.8 +> macros +Power List> end + +CVC: Linking devices... +Usage EQUIV: Time: 3 Memory: 346148 I/O: 72 Swap: 0 +Power nets 396 +Hash dump:parameter->resistance map +Contains 193 buckets, 384 elements +Element count 0, 5 +Element count 1, 73 +Element count 2, 67 +Element count 3, 25 +Element count 4, 15 +Element count 5, 6 +Element count 6, 2 +Unused hash: 0.03, average depth 2.68 +Hash dump:text->circuit map +Contains 79 buckets, 82 elements +Element count 0, 24 +Element count 1, 36 +Element count 2, 12 +Element count 3, 6 +Element count 4, 1 +Unused hash: 0.30, average depth 1.88 +Hash dump:string->text map +Contains 444487 buckets, 558146 elements +Element count 0, 127129 +Element count 1, 158275 +Element count 2, 99816 +Element count 3, 41875 +Element count 4, 13318 +Element count 5, 3266 +Element count 6, 663 +Element count 7, 128 +Element count 8, 15 +Element count 9, 2 +Unused hash: 0.29, average depth 2.26 +CVC: Shorting non conducting resistors... +CVC: Calculating resistor voltages... +Usage RES: Time: 3 Memory: 346148 I/O: 72 Swap: 0 +Power nets 396 +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX1: Time: 3 Memory: 346148 I/O: 80 Swap: 0 +Power nets 813 +! Checking forward bias diode errors: + +! Checking nmos source/drain vs bias errors: + +! Checking nmos gate vs source errors: + +! Checking pmos source/drain vs bias errors: + +! Checking pmos gate vs source errors: + +Usage ERROR: Time: 4 Memory: 346148 I/O: 80 Swap: 0 +CVC: Propagating Simulation voltages 1... +Usage SIM1: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 813 +CVC: Propagating Simulation voltages 3... +Usage SIM2: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 813 +Added 0 latch voltages +CVC: Calculating min/max voltages... +Processing trivial nets found 1517 trivial nets +CVC: Ignoring invalid calculations... +CVC: Removed 0 calculations +Copying master nets +CVC: Ignoring non-conducting devices... +CVC: Ignored 0 devices +Usage MIN/MAX2: Time: 4 Memory: 348320 I/O: 80 Swap: 0 +Power nets 1230 +! Checking overvoltage errors + +! Checking nmos possible leak errors: + +! Checking pmos possible leak errors: + +! Checking mos floating input errors: + +! Checking expected values: + +CVC: Error Counts +CVC: Fuse Problems: 0 +CVC: Min Voltage Conflicts: 0 +CVC: Max Voltage Conflicts: 0 +CVC: Leaks: 0 +CVC: LDD drain->source: 0 +CVC: HI-Z Inputs: 0 +CVC: Forward Bias Diodes: 0 +CVC: NMOS Source vs Bulk: 0 +CVC: NMOS Gate vs Source: 0 +CVC: NMOS Possible Leaks: 0 +CVC: PMOS Source vs Bulk: 0 +CVC: PMOS Gate vs Source: 0 +CVC: PMOS Possible Leaks: 0 +CVC: Overvoltage-VBG: 0 +CVC: Overvoltage-VBS: 0 +CVC: Overvoltage-VDS: 0 +CVC: Overvoltage-VGS: 0 +CVC: Model errors: 0 +CVC: Unexpected voltage : 0 +CVC: Total: 0 +Usage Total: Time: 4 Memory: 348908 I/O: 120 Swap: 0 +Virtual net update/access 18312/27061257 +CVC: Log output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp_oeb/cvc.oeb.log +CVC: End: Tue May 12 08:19:51 2026 + + +> gn io_in[0] +Net io_in[0]: 29 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[1] +Net io_in[1]: 40 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[2] +Net io_in[2]: 51 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[3] +Net io_in[3]: 60 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[4] +Net io_in[4]: 61 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[5] +Net io_in[5]: 62 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[6] +Net io_in[6]: 63 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[7] +Net io_in[7]: 64 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[8] +Net io_in[8]: 65 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[9] +Net io_in[9]: 66 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[10] +Net io_in[10]: 30 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[11] +Net io_in[11]: 31 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[12] +Net io_in[12]: 32 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[13] +Net io_in[13]: 33 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[14] +Net io_in[14]: 34 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[15] +Net io_in[15]: 35 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[16] +Net io_in[16]: 36 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[17] +Net io_in[17]: 37 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[18] +Net io_in[18]: 38 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[19] +Net io_in[19]: 39 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[20] +Net io_in[20]: 41 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[21] +Net io_in[21]: 42 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[22] +Net io_in[22]: 43 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[23] +Net io_in[23]: 44 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[24] +Net io_in[24]: 45 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[25] +Net io_in[25]: 46 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[26] +Net io_in[26]: 47 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[27] +Net io_in[27]: 48 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[28] +Net io_in[28]: 49 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[29] +Net io_in[29]: 50 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[30] +Net io_in[30]: 52 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[31] +Net io_in[31]: 53 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[32] +Net io_in[32]: 54 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[33] +Net io_in[33]: 55 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[34] +Net io_in[34]: 56 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[35] +Net io_in[35]: 57 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[36] +Net io_in[36]: 58 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[37] +Net io_in[37]: 59 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_out[0] +Net io_out[0]: 105 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[0] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[0] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[0] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[0] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[1] +Net io_out[1]: 116 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[1] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[1] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[1] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[1] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[2] +Net io_out[2]: 127 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[2] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[2] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[2] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[2] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[3] +Net io_out[3]: 136 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[3] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[3] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[3] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[3] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[4] +Net io_out[4]: 137 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[4] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[4] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[4] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[4] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[5] +Net io_out[5]: 138 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[5] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[5] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[5] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[5] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[6] +Net io_out[6]: 139 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[6] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[6] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[6] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[6] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[7] +Net io_out[7]: 140 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[7] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[7] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[7] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[7] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[8] +Net io_out[8]: 141 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[9] +Net io_out[9]: 142 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[10] +Net io_out[10]: 106 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[11] +Net io_out[11]: 107 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[12] +Net io_out[12]: 108 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[13] +Net io_out[13]: 109 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[14] +Net io_out[14]: 110 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[15] +Net io_out[15]: 111 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[16] +Net io_out[16]: 112 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[17] +Net io_out[17]: 113 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[18] +Net io_out[18]: 114 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[19] +Net io_out[19]: 115 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[20] +Net io_out[20]: 117 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[21] +Net io_out[21]: 118 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[22] +Net io_out[22]: 119 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[23] +Net io_out[23]: 120 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[24] +Net io_out[24]: 121 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[25] +Net io_out[25]: 122 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[26] +Net io_out[26]: 123 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[27] +Net io_out[27]: 124 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[28] +Net io_out[28]: 125 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[29] +Net io_out[29]: 126 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_out[30] +Net io_out[30]: 128 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[30] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[30] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[30] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[30] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[31] +Net io_out[31]: 129 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[31] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[31] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[31] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[31] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[32] +Net io_out[32]: 130 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[32] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[32] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[32] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[32] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[33] +Net io_out[33]: 131 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[33] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[33] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[33] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[33] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[34] +Net io_out[34]: 132 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[34] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[34] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[34] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[34] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[35] +Net io_out[35]: 133 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[35] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[35] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[35] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[35] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[36] +Net io_out[36]: 134 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[36] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[36] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[36] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[36] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_out[37] +Net io_out[37]: 135 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_out[37] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_out[37] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_out[37] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_out[37] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[0] +Net io_oeb[0]: 67 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[0] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[0] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[0] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[0] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[1] +Net io_oeb[1]: 78 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[1] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[1] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[1] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[1] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[2] +Net io_oeb[2]: 89 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[2] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[2] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[2] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[2] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[3] +Net io_oeb[3]: 98 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[3] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[3] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[3] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[3] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[4] +Net io_oeb[4]: 99 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[4] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[4] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[4] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[4] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[5] +Net io_oeb[5]: 100 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[5] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[5] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[5] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[5] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[6] +Net io_oeb[6]: 101 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[6] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[6] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[6] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[6] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[7] +Net io_oeb[7]: 102 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[7] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[7] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[7] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[7] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[8] +Net io_oeb[8]: 103 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[9] +Net io_oeb[9]: 104 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[10] +Net io_oeb[10]: 68 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[11] +Net io_oeb[11]: 69 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[12] +Net io_oeb[12]: 70 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[13] +Net io_oeb[13]: 71 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[14] +Net io_oeb[14]: 72 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[15] +Net io_oeb[15]: 73 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[16] +Net io_oeb[16]: 74 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[17] +Net io_oeb[17]: 75 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[18] +Net io_oeb[18]: 76 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[19] +Net io_oeb[19]: 77 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[20] +Net io_oeb[20]: 79 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[21] +Net io_oeb[21]: 80 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[22] +Net io_oeb[22]: 81 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[23] +Net io_oeb[23]: 82 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[24] +Net io_oeb[24]: 83 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[25] +Net io_oeb[25]: 84 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[26] +Net io_oeb[26]: 85 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[27] +Net io_oeb[27]: 86 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[28] +Net io_oeb[28]: 87 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[29] +Net io_oeb[29]: 88 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn io_oeb[30] +Net io_oeb[30]: 90 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[30] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[30] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[30] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[30] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[31] +Net io_oeb[31]: 91 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[31] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[31] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[31] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[31] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[32] +Net io_oeb[32]: 92 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[32] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[32] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[32] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[32] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[33] +Net io_oeb[33]: 93 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[33] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[33] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[33] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[33] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[34] +Net io_oeb[34]: 94 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[34] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[34] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[34] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[34] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[35] +Net io_oeb[35]: 95 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[35] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[35] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[35] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[35] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[36] +Net io_oeb[36]: 96 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[36] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[36] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[36] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[36] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_oeb[37] +Net io_oeb[37]: 97 + connections: gate 0 source 1 drain 1 bulk 0 + +Initial min path +io_oeb[37] +->vssd2 +vssd* power 0.0 -> 0.0 power + +Initial max path +io_oeb[37] +->vccd2 +vccd* power 1.8 -> 1.8 power + +Min path +io_oeb[37] +->vssd2 r=1615 +vssd* power 0.0 -> 0.0 power + +Max path +io_oeb[37] +->vccd2 r=1050 +vccd* power 1.8 -> 1.8 power + + +> gn io_in[0] +Net io_in[0]: 29 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[1] +Net io_in[1]: 40 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[2] +Net io_in[2]: 51 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[3] +Net io_in[3]: 60 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[4] +Net io_in[4]: 61 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[5] +Net io_in[5]: 62 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[6] +Net io_in[6]: 63 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[7] +Net io_in[7]: 64 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[8] +Net io_in[8]: 65 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[9] +Net io_in[9]: 66 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[10] +Net io_in[10]: 30 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[11] +Net io_in[11]: 31 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[12] +Net io_in[12]: 32 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[13] +Net io_in[13]: 33 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[14] +Net io_in[14]: 34 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[15] +Net io_in[15]: 35 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[16] +Net io_in[16]: 36 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[17] +Net io_in[17]: 37 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[18] +Net io_in[18]: 38 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[19] +Net io_in[19]: 39 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[20] +Net io_in[20]: 41 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[21] +Net io_in[21]: 42 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[22] +Net io_in[22]: 43 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[23] +Net io_in[23]: 44 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[24] +Net io_in[24]: 45 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[25] +Net io_in[25]: 46 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[26] +Net io_in[26]: 47 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[27] +Net io_in[27]: 48 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[28] +Net io_in[28]: 49 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[29] +Net io_in[29]: 50 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[30] +Net io_in[30]: 52 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[31] +Net io_in[31]: 53 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[32] +Net io_in[32]: 54 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[33] +Net io_in[33]: 55 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[34] +Net io_in[34]: 56 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[35] +Net io_in[35]: 57 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[36] +Net io_in[36]: 58 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn io_in[37] +Net io_in[37]: 59 + connections: gate 0 source 0 drain 0 bulk 0 + base definition io_in[*] + default min unknown + default sim unknown + default max unknown + defined as input min@0.0 max@1.8 => min@0.0 max@1.8 input + + +> gn analog_io[0] +Net analog_io[0]: 0 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[1] +Net analog_io[1]: 11 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[2] +Net analog_io[2]: 21 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[3] +Net analog_io[3]: 22 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[4] +Net analog_io[4]: 23 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[5] +Net analog_io[5]: 24 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[6] +Net analog_io[6]: 25 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[7] +Net analog_io[7]: 26 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[8] +Net analog_io[8]: 27 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[9] +Net analog_io[9]: 28 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[10] +Net analog_io[10]: 1 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[11] +Net analog_io[11]: 2 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[12] +Net analog_io[12]: 3 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[13] +Net analog_io[13]: 4 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[14] +Net analog_io[14]: 5 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[15] +Net analog_io[15]: 6 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[16] +Net analog_io[16]: 7 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[17] +Net analog_io[17]: 8 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[18] +Net analog_io[18]: 9 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[19] +Net analog_io[19]: 10 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[20] +Net analog_io[20]: 12 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[21] +Net analog_io[21]: 13 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[22] +Net analog_io[22]: 14 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[23] +Net analog_io[23]: 15 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[24] +Net analog_io[24]: 16 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[25] +Net analog_io[25]: 17 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[26] +Net analog_io[26]: 18 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[27] +Net analog_io[27]: 19 + connections: gate 0 source 0 drain 0 bulk 0 + + +> gn analog_io[28] +Net analog_io[28]: 20 + connections: gate 0 source 0 drain 0 bulk 0 + + +> q +Runtime: 0:00:04 (hh:mm:ss) diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/ext.log b/precheck_results/12_MAY_2026___07_45_39/logs/ext.log new file mode 100644 index 00000000..83a9d864 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/ext.log @@ -0,0 +1,717 @@ +BEGIN: Tue May 12 08:08:02 2026 +Extracting as digital. Top ports unique. + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design magicrc.well for technology sky130A ... +2 Magic internal units = 1 Lambda +Loading tech file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A.tech +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/abstract.tcl" from command line. +Abstracting +CIF input style is now "sky130()" +Abstracting /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "EZ_sky130_ef_sc_hd__decap_40_12". +Reading "EZ_sky130_fd_sc_hd__decap_3". +Reading "EZ_sky130_fd_sc_hd__fill_1". +Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "EZ_sky130_fd_sc_hd__fill_2". +Reading "EZ_sky130_fd_sc_hd__fill_4". +Reading "EZ_sky130_fd_sc_hd__buf_4". +Reading "EZ_sky130_fd_sc_hd__fill_8". +Reading "EZ_sky130_fd_sc_hd__diode_2". +Reading "EZ_sky130_fd_sc_hd__buf_12". +Reading "EZ_sky130_fd_sc_hd__clkbuf_8". +Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1". +Reading "EZ_sky130_fd_sc_hd__clkbuf_4". +Reading "EZ_sky130_fd_sc_hd__buf_2". +Reading "EZ_sky130_fd_sc_hd__dfxtp_1". +Reading "EZ_sky130_fd_sc_hd__mux2_1". +Reading "EZ_sky130_fd_sc_hd__dfxtp_2". +Reading "EZ_sky130_fd_sc_hd__conb_1". +Reading "EZ_sky130_fd_sc_hd__and2_4". +Reading "EZ_sky130_fd_sc_hd__and2_2". +Reading "EZ_sky130_fd_sc_hd__nand2_8". +Reading "EZ_sky130_fd_sc_hd__nor2_2". +Reading "EZ_sky130_fd_sc_hd__inv_2". +Reading "EZ_sky130_fd_sc_hd__buf_6". +Reading "EZ_sky130_fd_sc_hd__nand3b_4". +Reading "EZ_sky130_fd_sc_hd__a211o_1". +Reading "EZ_sky130_fd_sc_hd__nor2_1". +Reading "EZ_sky130_fd_sc_hd__and3_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_4". +Reading "EZ_sky130_fd_sc_hd__and2b_1". +Reading "EZ_sky130_fd_sc_hd__buf_1". +Reading "EZ_sky130_fd_sc_hd__a22o_1". +Reading "EZ_sky130_fd_sc_hd__a31o_1". +Reading "EZ_sky130_fd_sc_hd__o21a_1". +Reading "EZ_sky130_fd_sc_hd__a221o_1". +Reading "EZ_sky130_fd_sc_hd__a32o_1". +Reading "EZ_sky130_fd_sc_hd__and2_1". +Reading "EZ_sky130_fd_sc_hd__nand2_1". +Reading "EZ_sky130_fd_sc_hd__o2bb2a_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_1". +Reading "EZ_sky130_fd_sc_hd__o21ai_1". +Reading "EZ_sky130_fd_sc_hd__a32o_4". +Reading "EZ_sky130_fd_sc_hd__a21o_1". +Reading "EZ_sky130_fd_sc_hd__or3b_2". +Reading "EZ_sky130_fd_sc_hd__and2b_2". +Reading "EZ_sky130_fd_sc_hd__a31o_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_1". +Reading "EZ_sky130_fd_sc_hd__or3b_4". +Reading "EZ_sky130_fd_sc_hd__and4_1". +Reading "EZ_sky130_fd_sc_hd__a41o_4". +Reading "EZ_sky130_fd_sc_hd__and3b_4". +Reading "EZ_sky130_fd_sc_hd__buf_8". +Reading "EZ_sky130_fd_sc_hd__clkbuf_16". +Reading "EZ_sky130_fd_sc_hd__dfxtp_4". +Reading "EZ_sky130_fd_sc_hd__nor2_8". +Reading "EZ_sky130_fd_sc_hd__or2_1". +Reading "EZ_sky130_fd_sc_hd__o31a_1". +Reading "EZ_sky130_fd_sc_hd__o211a_1". +Reading "EZ_sky130_fd_sc_hd__o32a_1". +Reading "EZ_sky130_fd_sc_hd__a31oi_1". +Reading "EZ_sky130_fd_sc_hd__o31ai_1". +Reading "EZ_sky130_fd_sc_hd__o211ai_4". +Reading "EZ_sky130_fd_sc_hd__a41oi_4". +Reading "EZ_sky130_fd_sc_hd__and4_2". +Reading "EZ_sky130_fd_sc_hd__xor2_1". +Reading "EZ_sky130_fd_sc_hd__or2_2". +Reading "EZ_sky130_fd_sc_hd__nor2_4". +Reading "EZ_sky130_fd_sc_hd__or3_4". +Reading "EZ_sky130_fd_sc_hd__nand2_2". +Reading "EZ_sky130_fd_sc_hd__xnor2_1". +Reading "EZ_sky130_fd_sc_hd__and3b_1". +Reading "EZ_sky130_fd_sc_hd__a31o_2". +Reading "EZ_sky130_fd_sc_hd__a21bo_1". +Reading "EZ_sky130_fd_sc_hd__a21boi_1". +Reading "EZ_sky130_fd_sc_hd__nand2b_1". +Reading "EZ_sky130_fd_sc_hd__xnor2_2". +Reading "EZ_sky130_fd_sc_hd__nand4_2". +Reading "EZ_sky130_fd_sc_hd__a41o_1". +Reading "EZ_sky130_fd_sc_hd__and4_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_2". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses + 55000 uses + 60000 uses + 65000 uses + 70000 uses + 75000 uses + 80000 uses + 85000 uses + 90000 uses + 95000 uses + 100000 uses + 105000 uses + 110000 uses + 115000 uses + 120000 uses + 125000 uses + 130000 uses + 135000 uses + 140000 uses + 145000 uses + 150000 uses + 155000 uses + 160000 uses + 165000 uses + 170000 uses + 175000 uses + 180000 uses + 185000 uses + 190000 uses + 195000 uses + 200000 uses + 205000 uses + 210000 uses + 215000 uses + 220000 uses + 225000 uses + 230000 uses + 235000 uses + 240000 uses + 245000 uses + 250000 uses + 255000 uses + 260000 uses + 265000 uses + 270000 uses + 275000 uses + 280000 uses + 285000 uses + 290000 uses + 295000 uses + 300000 uses + 305000 uses + 310000 uses + 315000 uses + 320000 uses + 325000 uses + 330000 uses + 335000 uses + 340000 uses + 345000 uses + 350000 uses + 355000 uses + 360000 uses + 365000 uses + 370000 uses + 375000 uses + 380000 uses + 385000 uses + 390000 uses + 395000 uses + 400000 uses + 405000 uses + 410000 uses + 415000 uses + 420000 uses + 425000 uses + 430000 uses + 435000 uses + 440000 uses + 445000 uses + 450000 uses + 455000 uses + 460000 uses + 465000 uses + 470000 uses + 475000 uses + 480000 uses + 485000 uses + 490000 uses + 495000 uses + 500000 uses + 505000 uses + 510000 uses + 515000 uses + 520000 uses + 525000 uses + 530000 uses + 535000 uses + 540000 uses + 545000 uses + 550000 uses + 555000 uses +Reading "user_project_wrapper". + +TIME: read GDS: 00:00:11 + + +TIME: create subcut: 00:00:00 + +Abstracting EZ_sky130_fd_sc_hd__fill_1 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_2 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_4 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__fill_8 +instance count:0 port count:5 +Abstracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 +instance count:0 port count:3 + +TIME: create abstract: 00:00:00 + +Using technology "sky130A", version 1.0.493 + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design magicrc.well for technology sky130A ... +2 Magic internal units = 1 Lambda +Loading tech file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A.tech +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/extract.tcl" from command line. +Extracting with top ports unique (digital) +CIF input style is now "sky130()" +Flattening + +Extracting /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "EZ_sky130_ef_sc_hd__decap_40_12". +Reading "EZ_sky130_fd_sc_hd__decap_3". +Reading "EZ_sky130_fd_sc_hd__fill_1". +Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "EZ_sky130_fd_sc_hd__fill_2". +Reading "EZ_sky130_fd_sc_hd__fill_4". +Reading "EZ_sky130_fd_sc_hd__buf_4". +Reading "EZ_sky130_fd_sc_hd__fill_8". +Reading "EZ_sky130_fd_sc_hd__diode_2". +Reading "EZ_sky130_fd_sc_hd__buf_12". +Reading "EZ_sky130_fd_sc_hd__clkbuf_8". +Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1". +Reading "EZ_sky130_fd_sc_hd__clkbuf_4". +Reading "EZ_sky130_fd_sc_hd__buf_2". +Reading "EZ_sky130_fd_sc_hd__dfxtp_1". +Reading "EZ_sky130_fd_sc_hd__mux2_1". +Reading "EZ_sky130_fd_sc_hd__dfxtp_2". +Reading "EZ_sky130_fd_sc_hd__conb_1". +Reading "EZ_sky130_fd_sc_hd__and2_4". +Reading "EZ_sky130_fd_sc_hd__and2_2". +Reading "EZ_sky130_fd_sc_hd__nand2_8". +Reading "EZ_sky130_fd_sc_hd__nor2_2". +Reading "EZ_sky130_fd_sc_hd__inv_2". +Reading "EZ_sky130_fd_sc_hd__buf_6". +Reading "EZ_sky130_fd_sc_hd__nand3b_4". +Reading "EZ_sky130_fd_sc_hd__a211o_1". +Reading "EZ_sky130_fd_sc_hd__nor2_1". +Reading "EZ_sky130_fd_sc_hd__and3_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_4". +Reading "EZ_sky130_fd_sc_hd__and2b_1". +Reading "EZ_sky130_fd_sc_hd__buf_1". +Reading "EZ_sky130_fd_sc_hd__a22o_1". +Reading "EZ_sky130_fd_sc_hd__a31o_1". +Reading "EZ_sky130_fd_sc_hd__o21a_1". +Reading "EZ_sky130_fd_sc_hd__a221o_1". +Reading "EZ_sky130_fd_sc_hd__a32o_1". +Reading "EZ_sky130_fd_sc_hd__and2_1". +Reading "EZ_sky130_fd_sc_hd__nand2_1". +Reading "EZ_sky130_fd_sc_hd__o2bb2a_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_1". +Reading "EZ_sky130_fd_sc_hd__o21ai_1". +Reading "EZ_sky130_fd_sc_hd__a32o_4". +Reading "EZ_sky130_fd_sc_hd__a21o_1". +Reading "EZ_sky130_fd_sc_hd__or3b_2". +Reading "EZ_sky130_fd_sc_hd__and2b_2". +Reading "EZ_sky130_fd_sc_hd__a31o_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_1". +Reading "EZ_sky130_fd_sc_hd__or3b_4". +Reading "EZ_sky130_fd_sc_hd__and4_1". +Reading "EZ_sky130_fd_sc_hd__a41o_4". +Reading "EZ_sky130_fd_sc_hd__and3b_4". +Reading "EZ_sky130_fd_sc_hd__buf_8". +Reading "EZ_sky130_fd_sc_hd__clkbuf_16". +Reading "EZ_sky130_fd_sc_hd__dfxtp_4". +Reading "EZ_sky130_fd_sc_hd__nor2_8". +Reading "EZ_sky130_fd_sc_hd__or2_1". +Reading "EZ_sky130_fd_sc_hd__o31a_1". +Reading "EZ_sky130_fd_sc_hd__o211a_1". +Reading "EZ_sky130_fd_sc_hd__o32a_1". +Reading "EZ_sky130_fd_sc_hd__a31oi_1". +Reading "EZ_sky130_fd_sc_hd__o31ai_1". +Reading "EZ_sky130_fd_sc_hd__o211ai_4". +Reading "EZ_sky130_fd_sc_hd__a41oi_4". +Reading "EZ_sky130_fd_sc_hd__and4_2". +Reading "EZ_sky130_fd_sc_hd__xor2_1". +Reading "EZ_sky130_fd_sc_hd__or2_2". +Reading "EZ_sky130_fd_sc_hd__nor2_4". +Reading "EZ_sky130_fd_sc_hd__or3_4". +Reading "EZ_sky130_fd_sc_hd__nand2_2". +Reading "EZ_sky130_fd_sc_hd__xnor2_1". +Reading "EZ_sky130_fd_sc_hd__and3b_1". +Reading "EZ_sky130_fd_sc_hd__a31o_2". +Reading "EZ_sky130_fd_sc_hd__a21bo_1". +Reading "EZ_sky130_fd_sc_hd__a21boi_1". +Reading "EZ_sky130_fd_sc_hd__nand2b_1". +Reading "EZ_sky130_fd_sc_hd__xnor2_2". +Reading "EZ_sky130_fd_sc_hd__nand4_2". +Reading "EZ_sky130_fd_sc_hd__a41o_1". +Reading "EZ_sky130_fd_sc_hd__and4_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_2". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses + 55000 uses + 60000 uses + 65000 uses + 70000 uses + 75000 uses + 80000 uses + 85000 uses + 90000 uses + 95000 uses + 100000 uses + 105000 uses + 110000 uses + 115000 uses + 120000 uses + 125000 uses + 130000 uses + 135000 uses + 140000 uses + 145000 uses + 150000 uses + 155000 uses + 160000 uses + 165000 uses + 170000 uses + 175000 uses + 180000 uses + 185000 uses + 190000 uses + 195000 uses + 200000 uses + 205000 uses + 210000 uses + 215000 uses + 220000 uses + 225000 uses + 230000 uses + 235000 uses + 240000 uses + 245000 uses + 250000 uses + 255000 uses + 260000 uses + 265000 uses + 270000 uses + 275000 uses + 280000 uses + 285000 uses + 290000 uses + 295000 uses + 300000 uses + 305000 uses + 310000 uses + 315000 uses + 320000 uses + 325000 uses + 330000 uses + 335000 uses + 340000 uses + 345000 uses + 350000 uses + 355000 uses + 360000 uses + 365000 uses + 370000 uses + 375000 uses + 380000 uses + 385000 uses + 390000 uses + 395000 uses + 400000 uses + 405000 uses + 410000 uses + 415000 uses + 420000 uses + 425000 uses + 430000 uses + 435000 uses + 440000 uses + 445000 uses + 450000 uses + 455000 uses + 460000 uses + 465000 uses + 470000 uses + 475000 uses + 480000 uses + 485000 uses + 490000 uses + 495000 uses + 500000 uses + 505000 uses + 510000 uses + 515000 uses + 520000 uses + 525000 uses + 530000 uses + 535000 uses + 540000 uses + 545000 uses + 550000 uses + 555000 uses +Reading "user_project_wrapper". + +TIME: read GDS: 00:00:10 + + +TIME: add subcut: 00:00:00 + +Abstracting EZ_sky130_fd_sc_hd__fill_1 +Abstracting EZ_sky130_fd_sc_hd__fill_2 +Abstracting EZ_sky130_fd_sc_hd__fill_4 +Abstracting EZ_sky130_fd_sc_hd__fill_8 +Abstracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 + +TIME: set abstract: 00:00:00 + +Processing EZ_sky130_fd_sc_hd__decap_3 +Processing EZ_sky130_ef_sc_hd__decap_40_12 +Processing EZ_sky130_fd_sc_hd__buf_12 +Processing EZ_sky130_fd_sc_hd__diode_2 +Processing EZ_sky130_fd_sc_hd__clkbuf_2 +Processing EZ_sky130_fd_sc_hd__buf_1 +Processing EZ_sky130_fd_sc_hd__and2_1 +Processing EZ_sky130_fd_sc_hd__and4_1 +Processing EZ_sky130_fd_sc_hd__a31o_1 +Processing EZ_sky130_fd_sc_hd__and3_1 +Processing EZ_sky130_fd_sc_hd__and4_2 +Processing EZ_sky130_fd_sc_hd__dlygate4sd3_1 +Processing EZ_sky130_fd_sc_hd__nand2b_1 +Processing EZ_sky130_fd_sc_hd__xor2_1 +Processing EZ_sky130_fd_sc_hd__and4_4 +Processing EZ_sky130_fd_sc_hd__a21oi_1 +Processing EZ_sky130_fd_sc_hd__nand2_1 +Processing EZ_sky130_fd_sc_hd__a41o_1 +Processing EZ_sky130_fd_sc_hd__nand4_2 +Processing EZ_sky130_fd_sc_hd__xnor2_1 +Processing EZ_sky130_fd_sc_hd__dfxtp_4 +Processing EZ_sky130_fd_sc_hd__a211o_1 +Processing EZ_sky130_fd_sc_hd__a21o_1 +Processing EZ_sky130_fd_sc_hd__xnor2_2 +Processing EZ_sky130_fd_sc_hd__a22o_1 +Processing EZ_sky130_fd_sc_hd__dfxtp_2 +Processing EZ_sky130_fd_sc_hd__a21boi_1 +Processing EZ_sky130_fd_sc_hd__a21bo_1 +Processing EZ_sky130_fd_sc_hd__clkbuf_4 +Processing EZ_sky130_fd_sc_hd__o21a_1 +Processing EZ_sky130_fd_sc_hd__clkbuf_16 +Processing EZ_sky130_fd_sc_hd__a31o_2 +Processing EZ_sky130_fd_sc_hd__and3b_1 +Processing EZ_sky130_fd_sc_hd__buf_4 +Processing EZ_sky130_fd_sc_hd__inv_2 +Processing EZ_sky130_fd_sc_hd__nand2_2 +Processing EZ_sky130_fd_sc_hd__clkbuf_8 +Processing EZ_sky130_fd_sc_hd__dfxtp_1 +Processing EZ_sky130_fd_sc_hd__nor2_1 +Processing EZ_sky130_fd_sc_hd__or3_4 +Processing EZ_sky130_fd_sc_hd__nor2_4 +Processing EZ_sky130_fd_sc_hd__or2_1 +Processing EZ_sky130_fd_sc_hd__o2bb2a_1 +Processing EZ_sky130_fd_sc_hd__and2b_1 +Processing EZ_sky130_fd_sc_hd__or2_2 +Processing EZ_sky130_fd_sc_hd__mux2_1 +Processing EZ_sky130_fd_sc_hd__a41oi_4 +Processing EZ_sky130_fd_sc_hd__a21oi_4 +Processing EZ_sky130_fd_sc_hd__o211ai_4 +Processing EZ_sky130_fd_sc_hd__o31ai_1 +Processing EZ_sky130_fd_sc_hd__a31oi_1 +Processing EZ_sky130_fd_sc_hd__o32a_1 +Processing EZ_sky130_fd_sc_hd__o211a_1 +Processing EZ_sky130_fd_sc_hd__o31a_1 +Processing EZ_sky130_fd_sc_hd__nor2_8 +Processing EZ_sky130_fd_sc_hd__a32o_1 +Processing EZ_sky130_fd_sc_hd__conb_1 +Processing EZ_sky130_fd_sc_hd__buf_8 +Processing EZ_sky130_fd_sc_hd__clkbuf_1 +Processing EZ_sky130_fd_sc_hd__or3b_4 +Processing EZ_sky130_fd_sc_hd__and3b_4 +Processing EZ_sky130_fd_sc_hd__buf_6 +Processing EZ_sky130_fd_sc_hd__and2_2 +Processing EZ_sky130_fd_sc_hd__a41o_4 +Processing EZ_sky130_fd_sc_hd__a31o_4 +Processing EZ_sky130_fd_sc_hd__and2b_2 +Processing EZ_sky130_fd_sc_hd__or3b_2 +Processing EZ_sky130_fd_sc_hd__a32o_4 +Processing EZ_sky130_fd_sc_hd__o21ai_1 +Processing EZ_sky130_fd_sc_hd__a221o_1 +Processing EZ_sky130_fd_sc_hd__nand3b_4 +Processing EZ_sky130_fd_sc_hd__nand2_8 +Processing EZ_sky130_fd_sc_hd__and2_4 +Processing EZ_sky130_fd_sc_hd__nor2_2 +Processing EZ_sky130_fd_sc_hd__buf_2 +Processing user_proj_example +Processing user_project_wrapper +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Extraction style is now "ngspice()" +Extracting EZ_sky130_fd_sc_hd__decap_3 into EZ_sky130_fd_sc_hd__decap_3.ext: +EZ_sky130_fd_sc_hd__decap_3: 2 warnings +Extracting EZ_sky130_fd_sc_hd__fill_2 into EZ_sky130_fd_sc_hd__fill_2.ext: +Extracting EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 into EZ_sky130_fd_sc_hd__tapvpwrvgnd_1.ext: +Extracting EZ_sky130_fd_sc_hd__fill_8 into EZ_sky130_fd_sc_hd__fill_8.ext: +Extracting EZ_sky130_fd_sc_hd__fill_1 into EZ_sky130_fd_sc_hd__fill_1.ext: +Extracting EZ_sky130_ef_sc_hd__decap_40_12 into EZ_sky130_ef_sc_hd__decap_40_12.ext: +EZ_sky130_ef_sc_hd__decap_40_12: 2 warnings +Extracting EZ_sky130_fd_sc_hd__fill_4 into EZ_sky130_fd_sc_hd__fill_4.ext: +Extracting EZ_sky130_fd_sc_hd__buf_12 into EZ_sky130_fd_sc_hd__buf_12.ext: +Extracting EZ_sky130_fd_sc_hd__diode_2 into EZ_sky130_fd_sc_hd__diode_2.ext: +EZ_sky130_fd_sc_hd__diode_2: 1 warning +Extracting EZ_sky130_fd_sc_hd__clkbuf_2 into EZ_sky130_fd_sc_hd__clkbuf_2.ext: +Extracting EZ_sky130_fd_sc_hd__buf_1 into EZ_sky130_fd_sc_hd__buf_1.ext: +Extracting EZ_sky130_fd_sc_hd__and2_1 into EZ_sky130_fd_sc_hd__and2_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_1 into EZ_sky130_fd_sc_hd__and4_1.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_1 into EZ_sky130_fd_sc_hd__a31o_1.ext: +Extracting EZ_sky130_fd_sc_hd__and3_1 into EZ_sky130_fd_sc_hd__and3_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_2 into EZ_sky130_fd_sc_hd__and4_2.ext: +Extracting EZ_sky130_fd_sc_hd__dlygate4sd3_1 into EZ_sky130_fd_sc_hd__dlygate4sd3_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand2b_1 into EZ_sky130_fd_sc_hd__nand2b_1.ext: +Extracting EZ_sky130_fd_sc_hd__xor2_1 into EZ_sky130_fd_sc_hd__xor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__and4_4 into EZ_sky130_fd_sc_hd__and4_4.ext: +Extracting EZ_sky130_fd_sc_hd__a21oi_1 into EZ_sky130_fd_sc_hd__a21oi_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_1 into EZ_sky130_fd_sc_hd__nand2_1.ext: +Extracting EZ_sky130_fd_sc_hd__a41o_1 into EZ_sky130_fd_sc_hd__a41o_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand4_2 into EZ_sky130_fd_sc_hd__nand4_2.ext: +Extracting EZ_sky130_fd_sc_hd__xnor2_1 into EZ_sky130_fd_sc_hd__xnor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_4 into EZ_sky130_fd_sc_hd__dfxtp_4.ext: +Extracting EZ_sky130_fd_sc_hd__a211o_1 into EZ_sky130_fd_sc_hd__a211o_1.ext: +Extracting EZ_sky130_fd_sc_hd__a21o_1 into EZ_sky130_fd_sc_hd__a21o_1.ext: +Extracting EZ_sky130_fd_sc_hd__xnor2_2 into EZ_sky130_fd_sc_hd__xnor2_2.ext: +Extracting EZ_sky130_fd_sc_hd__a22o_1 into EZ_sky130_fd_sc_hd__a22o_1.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_2 into EZ_sky130_fd_sc_hd__dfxtp_2.ext: +Extracting EZ_sky130_fd_sc_hd__a21boi_1 into EZ_sky130_fd_sc_hd__a21boi_1.ext: +Extracting EZ_sky130_fd_sc_hd__a21bo_1 into EZ_sky130_fd_sc_hd__a21bo_1.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_4 into EZ_sky130_fd_sc_hd__clkbuf_4.ext: +Extracting EZ_sky130_fd_sc_hd__o21a_1 into EZ_sky130_fd_sc_hd__o21a_1.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_16 into EZ_sky130_fd_sc_hd__clkbuf_16.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_2 into EZ_sky130_fd_sc_hd__a31o_2.ext: +Extracting EZ_sky130_fd_sc_hd__and3b_1 into EZ_sky130_fd_sc_hd__and3b_1.ext: +Extracting EZ_sky130_fd_sc_hd__buf_4 into EZ_sky130_fd_sc_hd__buf_4.ext: +Extracting EZ_sky130_fd_sc_hd__inv_2 into EZ_sky130_fd_sc_hd__inv_2.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_2 into EZ_sky130_fd_sc_hd__nand2_2.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_8 into EZ_sky130_fd_sc_hd__clkbuf_8.ext: +Extracting EZ_sky130_fd_sc_hd__dfxtp_1 into EZ_sky130_fd_sc_hd__dfxtp_1.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_1 into EZ_sky130_fd_sc_hd__nor2_1.ext: +Extracting EZ_sky130_fd_sc_hd__or3_4 into EZ_sky130_fd_sc_hd__or3_4.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_4 into EZ_sky130_fd_sc_hd__nor2_4.ext: +Extracting EZ_sky130_fd_sc_hd__or2_1 into EZ_sky130_fd_sc_hd__or2_1.ext: +Extracting EZ_sky130_fd_sc_hd__o2bb2a_1 into EZ_sky130_fd_sc_hd__o2bb2a_1.ext: +Extracting EZ_sky130_fd_sc_hd__and2b_1 into EZ_sky130_fd_sc_hd__and2b_1.ext: +Extracting EZ_sky130_fd_sc_hd__or2_2 into EZ_sky130_fd_sc_hd__or2_2.ext: +Extracting EZ_sky130_fd_sc_hd__mux2_1 into EZ_sky130_fd_sc_hd__mux2_1.ext: +Extracting EZ_sky130_fd_sc_hd__a41oi_4 into EZ_sky130_fd_sc_hd__a41oi_4.ext: +Extracting EZ_sky130_fd_sc_hd__a21oi_4 into EZ_sky130_fd_sc_hd__a21oi_4.ext: +Extracting EZ_sky130_fd_sc_hd__o211ai_4 into EZ_sky130_fd_sc_hd__o211ai_4.ext: +Extracting EZ_sky130_fd_sc_hd__o31ai_1 into EZ_sky130_fd_sc_hd__o31ai_1.ext: +Extracting EZ_sky130_fd_sc_hd__a31oi_1 into EZ_sky130_fd_sc_hd__a31oi_1.ext: +Extracting EZ_sky130_fd_sc_hd__o32a_1 into EZ_sky130_fd_sc_hd__o32a_1.ext: +Extracting EZ_sky130_fd_sc_hd__o211a_1 into EZ_sky130_fd_sc_hd__o211a_1.ext: +Extracting EZ_sky130_fd_sc_hd__o31a_1 into EZ_sky130_fd_sc_hd__o31a_1.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_8 into EZ_sky130_fd_sc_hd__nor2_8.ext: +Extracting EZ_sky130_fd_sc_hd__a32o_1 into EZ_sky130_fd_sc_hd__a32o_1.ext: +Extracting EZ_sky130_fd_sc_hd__conb_1 into EZ_sky130_fd_sc_hd__conb_1.ext: +Extracting EZ_sky130_fd_sc_hd__buf_8 into EZ_sky130_fd_sc_hd__buf_8.ext: +Extracting EZ_sky130_fd_sc_hd__clkbuf_1 into EZ_sky130_fd_sc_hd__clkbuf_1.ext: +Extracting EZ_sky130_fd_sc_hd__or3b_4 into EZ_sky130_fd_sc_hd__or3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__and3b_4 into EZ_sky130_fd_sc_hd__and3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__buf_6 into EZ_sky130_fd_sc_hd__buf_6.ext: +Extracting EZ_sky130_fd_sc_hd__and2_2 into EZ_sky130_fd_sc_hd__and2_2.ext: +Extracting EZ_sky130_fd_sc_hd__a41o_4 into EZ_sky130_fd_sc_hd__a41o_4.ext: +Extracting EZ_sky130_fd_sc_hd__a31o_4 into EZ_sky130_fd_sc_hd__a31o_4.ext: +Extracting EZ_sky130_fd_sc_hd__and2b_2 into EZ_sky130_fd_sc_hd__and2b_2.ext: +Extracting EZ_sky130_fd_sc_hd__or3b_2 into EZ_sky130_fd_sc_hd__or3b_2.ext: +Extracting EZ_sky130_fd_sc_hd__a32o_4 into EZ_sky130_fd_sc_hd__a32o_4.ext: +Extracting EZ_sky130_fd_sc_hd__o21ai_1 into EZ_sky130_fd_sc_hd__o21ai_1.ext: +Extracting EZ_sky130_fd_sc_hd__a221o_1 into EZ_sky130_fd_sc_hd__a221o_1.ext: +Extracting EZ_sky130_fd_sc_hd__nand3b_4 into EZ_sky130_fd_sc_hd__nand3b_4.ext: +Extracting EZ_sky130_fd_sc_hd__nand2_8 into EZ_sky130_fd_sc_hd__nand2_8.ext: +Extracting EZ_sky130_fd_sc_hd__and2_4 into EZ_sky130_fd_sc_hd__and2_4.ext: +Extracting EZ_sky130_fd_sc_hd__nor2_2 into EZ_sky130_fd_sc_hd__nor2_2.ext: +Extracting EZ_sky130_fd_sc_hd__buf_2 into EZ_sky130_fd_sc_hd__buf_2.ext: +Extracting user_proj_example into user_proj_example.ext: +Extracting user_project_wrapper into user_project_wrapper.ext: +Total of 5 warnings. + +TIME: extract: 00:07:52 + +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 0 +Devs merged: 28 +Devs merged: 28 +Devs merged: 28 +Devs merged: 28 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 34 +Devs merged: 40 +Devs merged: 40 +Devs merged: 46 +Devs merged: 46 +Devs merged: 46 +Devs merged: 62 +Devs merged: 62 +Devs merged: 73 +Devs merged: 79 +Devs merged: 81 +Devs merged: 81 +Devs merged: 97 +Devs merged: 97 +Devs merged: 97 +Devs merged: 103 +Devs merged: 133 +Devs merged: 133 +Devs merged: 135 +Devs merged: 171 +Devs merged: 173 +Devs merged: 175 +Devs merged: 183 +Devs merged: 183 +Devs merged: 185 +Devs merged: 185 +Devs merged: 191 +Devs merged: 191 +Devs merged: 209 +Devs merged: 209 +Devs merged: 225 +Devs merged: 225 +Devs merged: 227 +Devs merged: 229 +Devs merged: 229 +Devs merged: 233 +Devs merged: 233 +Devs merged: 233 +Devs merged: 235 +Devs merged: 241 +Devs merged: 241 +Devs merged: 259 +Devs merged: 271 +Devs merged: 271 +Devs merged: 299 +Devs merged: 305 +Devs merged: 323 +Devs merged: 327 +Devs merged: 327 +Devs merged: 337 +Devs merged: 365 +Devs merged: 385 +Devs merged: 385 +Devs merged: 387 +Devs merged: 387 +Devs merged: 399 +Devs merged: 401 +Devs merged: 401 +Devs merged: 401 +Devs merged: 401 +exttospice finished. + +TIME: netlist: 00:00:46 + +Using technology "sky130A", version 1.0.493 +END: Tue May 12 08:17:21 2026 +Runtime: 0:09:19 (hh:mm:ss) diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/gds.info b/precheck_results/12_MAY_2026___07_45_39/logs/gds.info new file mode 100644 index 00000000..f4b5e621 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/gds.info @@ -0,0 +1 @@ +user_project_wrapper.gds: 7dedb0577fede3bf2014261de4d5e78fb372daa1 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/hier.log b/precheck_results/12_MAY_2026___07_45_39/logs/hier.log new file mode 100644 index 00000000..731827bb --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/hier.log @@ -0,0 +1,9 @@ +BEGIN: Tue May 12 08:07:53 2026 +Creating /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/verilog.cells from the following files... + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v + /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +[INFO] Changing from /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds + to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/layout.txt +Hierarchy check for user_project_wrapper passed. +END: Tue May 12 08:08:02 2026 +Runtime: 0:00:09 (hh:mm:ss) diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.log new file mode 100644 index 00000000..e41b90fc --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.log @@ -0,0 +1,1197 @@ +"input" in: sky130A_mr.drc:182 + Polygons (raw): 556000 (flat) 203 (hierarchical) + Elapsed: 0.230s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:183 + Polygons (raw): 138456 (flat) 2 (hierarchical) + Elapsed: 0.150s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:184 + Polygons (raw): 555952 (flat) 80 (hierarchical) + Elapsed: 0.140s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:185 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:186 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:187 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:188 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:189 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:190 + Polygons (raw): 555954 (flat) 82 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:191 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:192 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:193 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:194 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:195 + Polygons (raw): 557581 (flat) 460 (hierarchical) + Elapsed: 0.130s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:196 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:197 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:198 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.130s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:199 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:200 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:201 + Polygons (raw): 277696 (flat) 85 (hierarchical) + Elapsed: 0.130s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:202 + Polygons (raw): 2992871 (flat) 2207 (hierarchical) + Elapsed: 0.150s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:204 + Polygons (raw): 2361125 (flat) 3252 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:205 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:206 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:208 + Polygons (raw): 1122452 (flat) 10588 (hierarchical) + Elapsed: 0.120s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:209 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.230s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:211 + Polygons (raw): 21155 (flat) 21155 (hierarchical) + Elapsed: 0.180s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:212 + Polygons (raw): 49591 (flat) 49591 (hierarchical) + Elapsed: 0.190s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:214 + Polygons (raw): 15538 (flat) 15538 (hierarchical) + Elapsed: 0.190s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:215 + Polygons (raw): 48854 (flat) 48854 (hierarchical) + Elapsed: 0.190s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:217 + Polygons (raw): 897 (flat) 897 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:218 + Polygons (raw): 12970 (flat) 12970 (hierarchical) + Elapsed: 0.040s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:220 + Polygons (raw): 173 (flat) 173 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:222 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:223 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:224 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:225 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:226 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:227 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:228 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:229 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:230 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:231 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:232 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:233 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:234 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:235 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:236 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:237 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:238 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:239 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:240 + Polygons (raw): 555952 (flat) 80 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:241 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:242 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:243 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:244 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:245 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:246 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:247 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:248 + Polygons (raw): 2 (flat) 2 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:249 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:250 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:251 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:252 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:253 + Polygons (raw): 644 (flat) 1 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:254 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:255 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:256 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:257 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:258 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:259 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:260 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:261 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:262 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:263 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:264 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:265 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:266 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:267 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:268 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:269 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:270 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:271 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:272 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:273 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:274 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:275 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:276 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:277 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"merged" in: sky130A_mr.drc:279 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +DRC section +BEOL section +START: 67/20 (li) +"outside" in: sky130A_mr.drc:1069 + Polygons (raw): 2361125 (flat) 3252 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"interacting" in: sky130A_mr.drc:1070 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"inside" in: sky130A_mr.drc:1070 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"-" in: sky130A_mr.drc:1070 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"or" in: sky130A_mr.drc:1069 + Polygons (raw): 4495 (flat) 3075 (hierarchical) + Elapsed: 19.640s Memory: 1329.00M +"width" in: sky130A_mr.drc:1072 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 4.260s Memory: 1329.00M +"output" in: sky130A_mr.drc:1072 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1329.00M +"space" in: sky130A_mr.drc:1076 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 6.660s Memory: 1617.00M +"output" in: sky130A_mr.drc:1076 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1617.00M +"-" in: sky130A_mr.drc:1080 + Polygons (raw): 2992871 (flat) 2207 (hierarchical) + Elapsed: 0.000s Memory: 1617.00M +"enclosing" in: sky130A_mr.drc:1082 + Edge pairs: 2919083 (flat) 2912530 (hierarchical) + Elapsed: 138.480s Memory: 2188.00M +"second_edges" in: sky130A_mr.drc:1082 + Edges: 2919083 (flat) 2912530 (hierarchical) + Elapsed: 0.260s Memory: 2232.00M +"width" in: sky130A_mr.drc:1083 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 12.430s Memory: 2805.00M +"polygons" in: sky130A_mr.drc:1084 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 2805.00M +"interacting" in: sky130A_mr.drc:1084 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"output" in: sky130A_mr.drc:1085 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"interacting" in: sky130A_mr.drc:1089 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"-" in: sky130A_mr.drc:1089 + Polygons (raw): 2361125 (flat) 3252 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"with_area" in: sky130A_mr.drc:1090 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 19.560s Memory: 2805.00M +"output" in: sky130A_mr.drc:1090 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 2805.00M +"&" in: sky130A_mr.drc:1094 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"space" in: sky130A_mr.drc:1095 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"output" in: sky130A_mr.drc:1095 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 2805.00M +"width" in: sky130A_mr.drc:1099 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"output" in: sky130A_mr.drc:1099 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +END: 67/20 (li) +START: 67/13 (li_res) +"width" in: sky130A_mr.drc:1107 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"output" in: sky130A_mr.drc:1107 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +END: 67/13 (li_res) +START: 67/44 (mcon) +"-" in: sky130A_mr.drc:1115 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.000s Memory: 2805.00M +"drc" in: sky130A_mr.drc:1117 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 77.700s Memory: 4384.00M +"-" in: sky130A_mr.drc:1118 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.110s Memory: 4384.00M +"outside" in: sky130A_mr.drc:1122 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"non_rectangles" in: sky130A_mr.drc:1123 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 68.230s Memory: 4128.00M +"output" in: sky130A_mr.drc:1123 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4128.00M +"drc" in: sky130A_mr.drc:1128 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 79.370s Memory: 4512.00M +"output" in: sky130A_mr.drc:1128 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4512.00M +"drc" in: sky130A_mr.drc:1132 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 12.210s Memory: 4448.00M +"output" in: sky130A_mr.drc:1132 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4384.00M +"space" in: sky130A_mr.drc:1136 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 14.060s Memory: 4320.00M +"output" in: sky130A_mr.drc:1136 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4064.00M +"width" in: sky130A_mr.drc:1141 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"output" in: sky130A_mr.drc:1141 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"drc" in: sky130A_mr.drc:1145 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.230s Memory: 4064.00M +"output" in: sky130A_mr.drc:1145 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"-" in: sky130A_mr.drc:1149 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"output" in: sky130A_mr.drc:1149 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4064.00M +"-" in: sky130A_mr.drc:1154 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 13.890s Memory: 4320.00M +"output" in: sky130A_mr.drc:1154 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +END: 67/44 (mcon) +START: 68/20 (m1) +"width" in: sky130A_mr.drc:1159 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 20.520s Memory: 4320.00M +"output" in: sky130A_mr.drc:1159 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1160 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.120s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1160 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"snap" in: sky130A_mr.drc:1160 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"&" in: sky130A_mr.drc:1160 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1161 + Edges: 29460 (flat) 28260 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"-" in: sky130A_mr.drc:1161 + Edges: 29460 (flat) 28260 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1162 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.170s Memory: 4320.00M +"merged" in: sky130A_mr.drc:1162 + Polygons (raw): 2817 (flat) 2757 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"outside_part" in: sky130A_mr.drc:1162 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"space" in: sky130A_mr.drc:1164 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"output" in: sky130A_mr.drc:1164 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.170s Memory: 4320.00M +"separation" in: sky130A_mr.drc:1170 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"space" in: sky130A_mr.drc:1171 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.070s Memory: 4320.00M +"+" in: sky130A_mr.drc:1170 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"output" in: sky130A_mr.drc:1172 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"input" in: sky130A_mr.drc:1183 + Polygons (raw): 1122452 (flat) 10588 (hierarchical) + Elapsed: 0.120s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1185 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 96.700s Memory: 4704.00M +"output" in: sky130A_mr.drc:1185 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"-" in: sky130A_mr.drc:1189 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 18.330s Memory: 4320.00M +"output" in: sky130A_mr.drc:1189 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"input" in: sky130A_mr.drc:1203 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.190s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1204 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1204 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1209 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1209 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1214 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.070s Memory: 4320.00M +"output" in: sky130A_mr.drc:1214 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"holes" in: sky130A_mr.drc:1217 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1218 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1219 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1230 + Edge pairs: 5242 (flat) 4882 (hierarchical) + Elapsed: 76.060s Memory: 4320.00M +"second_edges" in: sky130A_mr.drc:1230 + Edges: 5242 (flat) 4882 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"width" in: sky130A_mr.drc:1232 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.500s Memory: 4320.00M +"polygons" in: sky130A_mr.drc:1234 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"interacting" in: sky130A_mr.drc:1234 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1235 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +END: 68/20 (m1) +START: 68/44 (via) +"drc" in: sky130A_mr.drc:1246 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.740s Memory: 4320.00M +"-" in: sky130A_mr.drc:1247 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"-" in: sky130A_mr.drc:1252 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"non_rectangles" in: sky130A_mr.drc:1254 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.540s Memory: 4320.00M +"output" in: sky130A_mr.drc:1254 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"width" in: sky130A_mr.drc:1258 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.110s Memory: 4320.00M +"output" in: sky130A_mr.drc:1258 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1263 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.340s Memory: 4320.00M +"output" in: sky130A_mr.drc:1263 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"space" in: sky130A_mr.drc:1268 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.340s Memory: 4320.00M +"output" in: sky130A_mr.drc:1268 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"width" in: sky130A_mr.drc:1274 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"output" in: sky130A_mr.drc:1274 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1278 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"output" in: sky130A_mr.drc:1278 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1282 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1282 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1289 + Edges: 29460 (flat) 28260 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1290 + Edges: 253616 (flat) 253616 (hierarchical) + Elapsed: 1.410s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1290 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.310s Memory: 4320.00M +"output" in: sky130A_mr.drc:1291 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"squares" in: sky130A_mr.drc:1293 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.040s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1294 + Edges: 253616 (flat) 253616 (hierarchical) + Elapsed: 0.820s Memory: 4320.00M +"-" in: sky130A_mr.drc:1295 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 3.980s Memory: 4320.00M +"output" in: sky130A_mr.drc:1296 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1300 + Edges: 29460 (flat) 28260 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1301 + Edges: 253616 (flat) 253616 (hierarchical) + Elapsed: 0.820s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1301 + Edge pairs: 5284 (flat) 5284 (hierarchical) + Elapsed: 0.360s Memory: 4320.00M +"second_edges" in: sky130A_mr.drc:1302 + Edges: 5284 (flat) 5284 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"width" in: sky130A_mr.drc:1304 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.350s Memory: 4320.00M +"polygons" in: sky130A_mr.drc:1305 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"interacting" in: sky130A_mr.drc:1305 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"output" in: sky130A_mr.drc:1306 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +END: 68/44 (via) +START: 69/20 (m2) +"&" in: sky130A_mr.drc:1315 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"width" in: sky130A_mr.drc:1316 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.410s Memory: 4320.00M +"output" in: sky130A_mr.drc:1316 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1318 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.160s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1318 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"snap" in: sky130A_mr.drc:1318 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"&" in: sky130A_mr.drc:1318 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1319 + Edges: 79508 (flat) 79508 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"-" in: sky130A_mr.drc:1319 + Edges: 79508 (flat) 79508 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1320 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"merged" in: sky130A_mr.drc:1320 + Polygons (raw): 14200 (flat) 14200 (hierarchical) + Elapsed: 0.010s Memory: 4320.00M +"outside_part" in: sky130A_mr.drc:1320 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1321 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.040s Memory: 4320.00M +"space" in: sky130A_mr.drc:1323 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.710s Memory: 4320.00M +"output" in: sky130A_mr.drc:1323 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"separation" in: sky130A_mr.drc:1329 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"space" in: sky130A_mr.drc:1330 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.070s Memory: 4320.00M +"+" in: sky130A_mr.drc:1329 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1331 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1333 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4320.00M +"output" in: sky130A_mr.drc:1333 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"holes" in: sky130A_mr.drc:1335 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1336 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1337 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1345 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.510s Memory: 4320.00M +"output" in: sky130A_mr.drc:1345 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"-" in: sky130A_mr.drc:1349 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.340s Memory: 4320.00M +"output" in: sky130A_mr.drc:1349 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1353 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1353 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1358 + Edge pairs: 29635 (flat) 29635 (hierarchical) + Elapsed: 0.640s Memory: 4320.00M +"second_edges" in: sky130A_mr.drc:1358 + Edges: 29635 (flat) 29635 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"width" in: sky130A_mr.drc:1360 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.500s Memory: 4320.00M +"polygons" in: sky130A_mr.drc:1361 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"interacting" in: sky130A_mr.drc:1361 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1362 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +END: 69/20 (m2) +START: 69/44 (via2) +"drc" in: sky130A_mr.drc:1373 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.640s Memory: 4320.00M +"-" in: sky130A_mr.drc:1374 + Polygons (raw): 49591 (flat) 49591 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"-" in: sky130A_mr.drc:1379 + Polygons (raw): 49591 (flat) 49591 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"non_rectangles" in: sky130A_mr.drc:1380 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.470s Memory: 4320.00M +"output" in: sky130A_mr.drc:1380 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"width" in: sky130A_mr.drc:1384 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.100s Memory: 4320.00M +"output" in: sky130A_mr.drc:1384 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1389 + Edges: 198364 (flat) 198364 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"without_length" in: sky130A_mr.drc:1390 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4320.00M +"output" in: sky130A_mr.drc:1391 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"space" in: sky130A_mr.drc:1392 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.310s Memory: 4320.00M +"output" in: sky130A_mr.drc:1392 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.040s Memory: 4320.00M +"width" in: sky130A_mr.drc:1398 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1398 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"drc" in: sky130A_mr.drc:1402 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"output" in: sky130A_mr.drc:1402 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1406 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1406 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1412 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.420s Memory: 4320.00M +"output" in: sky130A_mr.drc:1412 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1416 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.310s Memory: 4320.00M +"output" in: sky130A_mr.drc:1416 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1419 + Edge pairs: 26290 (flat) 26290 (hierarchical) + Elapsed: 0.530s Memory: 4320.00M +"second_edges" in: sky130A_mr.drc:1419 + Edges: 26290 (flat) 26290 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"width" in: sky130A_mr.drc:1421 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.410s Memory: 4320.00M +"polygons" in: sky130A_mr.drc:1422 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"interacting" in: sky130A_mr.drc:1422 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1423 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +END: 69/44 (via2) +START: 70/20 (m3) +"width" in: sky130A_mr.drc:1432 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.340s Memory: 4320.00M +"output" in: sky130A_mr.drc:1432 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1434 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.130s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1434 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"snap" in: sky130A_mr.drc:1434 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"&" in: sky130A_mr.drc:1434 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1435 + Edges: 56808 (flat) 56808 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"-" in: sky130A_mr.drc:1435 + Edges: 56808 (flat) 56808 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1436 + 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0 (flat) 0 (hierarchical) + Elapsed: 0.410s Memory: 4320.00M +"output" in: sky130A_mr.drc:1454 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"-" in: sky130A_mr.drc:1458 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.280s Memory: 4320.00M +"output" in: sky130A_mr.drc:1458 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1460 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4320.00M +"output" in: sky130A_mr.drc:1460 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"holes" in: sky130A_mr.drc:1462 + Polygons (raw): 1 (flat) 1 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"with_area" in: sky130A_mr.drc:1463 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.240s Memory: 4320.00M +"output" in: sky130A_mr.drc:1464 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +END: 70/20 (m3) +START: 70/44 (via3) +"drc" in: sky130A_mr.drc:1471 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.640s Memory: 4320.00M +"-" in: sky130A_mr.drc:1472 + Polygons (raw): 48854 (flat) 48854 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"-" in: sky130A_mr.drc:1477 + Polygons (raw): 48854 (flat) 48854 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"non_rectangles" in: sky130A_mr.drc:1478 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.460s Memory: 4320.00M +"output" in: sky130A_mr.drc:1478 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"width" in: sky130A_mr.drc:1482 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.110s Memory: 4320.00M +"output" in: sky130A_mr.drc:1482 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"edges" in: sky130A_mr.drc:1487 + Edges: 195416 (flat) 195416 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"without_length" in: sky130A_mr.drc:1488 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.090s Memory: 4320.00M +"output" in: sky130A_mr.drc:1489 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"space" in: sky130A_mr.drc:1491 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.330s Memory: 4320.00M +"output" in: sky130A_mr.drc:1491 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1495 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.410s Memory: 4320.00M +"output" in: sky130A_mr.drc:1495 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4320.00M +"-" in: sky130A_mr.drc:1499 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.290s Memory: 4320.00M +"output" in: sky130A_mr.drc:1499 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"enclosing" in: sky130A_mr.drc:1505 + Edge pairs: 97671 (flat) 97671 (hierarchical) + Elapsed: 0.720s Memory: 4320.00M +"second_edges" in: sky130A_mr.drc:1505 + Edges: 97671 (flat) 97671 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"width" in: sky130A_mr.drc:1507 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.620s Memory: 4320.00M +"polygons" in: sky130A_mr.drc:1508 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4320.00M +"interacting" in: sky130A_mr.drc:1508 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"output" in: sky130A_mr.drc:1509 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +END: 70/44 (via3) +START: 71/20 (m4) +"width" in: sky130A_mr.drc:1518 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.350s Memory: 4320.00M +"output" in: sky130A_mr.drc:1518 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1520 + Polygons (raw): 146 (flat) 146 (hierarchical) + Elapsed: 0.080s Memory: 4320.00M +"sized" in: sky130A_mr.drc:1520 + Polygons (raw): 146 (flat) 146 (hierarchical) + Elapsed: 0.100s Memory: 4320.00M +"snap" in: sky130A_mr.drc:1520 + Polygons (raw): 146 (flat) 146 (hierarchical) + Elapsed: 0.550s Memory: 4296.00M +"&" in: sky130A_mr.drc:1520 + Polygons (raw): 146 (flat) 146 (hierarchical) + Elapsed: 0.090s Memory: 4296.00M +"edges" in: sky130A_mr.drc:1521 + Edges: 2038 (flat) 2038 (hierarchical) + Elapsed: 0.010s Memory: 4296.00M +"-" in: sky130A_mr.drc:1521 + Edges: 1454 (flat) 1454 (hierarchical) + Elapsed: 0.010s Memory: 4296.00M +"edges" in: sky130A_mr.drc:1522 + Edges: 584 (flat) 584 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"merged" in: sky130A_mr.drc:1522 + Polygons (raw): 292 (flat) 292 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"outside_part" in: sky130A_mr.drc:1522 + Edges: 584 (flat) 584 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"space" in: sky130A_mr.drc:1524 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.260s Memory: 4296.00M +"output" in: sky130A_mr.drc:1524 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4296.00M +"with_area" in: sky130A_mr.drc:1529 + Polygons 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Memory: 4296.00M +"width" in: sky130A_mr.drc:1568 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.340s Memory: 4296.00M +"output" in: sky130A_mr.drc:1568 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4296.00M +"drc" in: sky130A_mr.drc:1572 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.110s Memory: 4296.00M +"output" in: sky130A_mr.drc:1572 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"space" in: sky130A_mr.drc:1578 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.110s Memory: 4296.00M +"polygons" in: sky130A_mr.drc:1579 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"output" in: sky130A_mr.drc:1580 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"width" in: sky130A_mr.drc:1583 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"output" in: sky130A_mr.drc:1583 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4296.00M +"drc" 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Memory: 4296.00M +"output" in: sky130A_mr.drc:1606 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"space" in: sky130A_mr.drc:1608 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4296.00M +"output" in: sky130A_mr.drc:1608 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 4296.00M +"enclosing" in: sky130A_mr.drc:1610 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.170s Memory: 4296.00M +"output" in: sky130A_mr.drc:1610 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"-" in: sky130A_mr.drc:1614 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4296.00M +"output" in: sky130A_mr.drc:1614 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"with_area" in: sky130A_mr.drc:1621 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.080s Memory: 4296.00M +"output" in: sky130A_mr.drc:1621 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"holes" in: sky130A_mr.drc:1623 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"with_area" in: sky130A_mr.drc:1624 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"output" in: sky130A_mr.drc:1625 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +END: 72/20 (m5) +START: 76/20 (pad) +"space" in: sky130A_mr.drc:1630 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +"output" in: sky130A_mr.drc:1630 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 4296.00M +END: 76/20 (pad) +START: 81/10 (moduleCut) +"output" in: sky130A_mr.drc:1636 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 4296.00M +END: 81/10 (moduleCut) +Writing report database: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml .. +Total elapsed: 734.910s Memory: 3804.00M +Args: + sram_exclude: false + feol: false + beol: true + floating_met: false + offgrid: false + seal: + +Cell exclusion list: + rule | cell + nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses + +release 2026.03.30_01.00 diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_beol_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.log new file mode 100644 index 00000000..dedb2e80 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.log @@ -0,0 +1,1397 @@ +"input" in: sky130A_mr.drc:182 + Polygons (raw): 556000 (flat) 203 (hierarchical) + Elapsed: 0.230s Memory: 1022.00M +"polygons" in: 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1640.00M +"or" in: sky130A_mr.drc:372 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"&" in: sky130A_mr.drc:372 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"space" in: sky130A_mr.drc:373 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:374 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +END: 124/20 (pwde) +START: 18/20 (htvr) +"width" in: sky130A_mr.drc:379 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:379 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"separation" in: sky130A_mr.drc:383 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:383 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"&" in: sky130A_mr.drc:387 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:387 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +END: 18/20 (htvr) +START: 25/44 (lvtn) +"width" in: sky130A_mr.drc:392 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:392 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"space" in: sky130A_mr.drc:396 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1640.00M +"output" in: sky130A_mr.drc:396 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"interacting" in: sky130A_mr.drc:401 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"not_inside" in: sky130A_mr.drc:402 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"edges" in: sky130A_mr.drc:403 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"&" in: sky130A_mr.drc:404 + Edges: 0 (flat) 0 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1640.00M +"polygons" in: sky130A_mr.drc:420 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"edges" in: sky130A_mr.drc:423 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"outside_part" in: sky130A_mr.drc:424 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"outside" in: sky130A_mr.drc:425 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"edges" in: sky130A_mr.drc:425 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"-" in: sky130A_mr.drc:425 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:426 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"outside" in: sky130A_mr.drc:431 + Polygons (raw): 556000 (flat) 203 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"width" in: sky130A_mr.drc:432 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.230s Memory: 1640.00M +"output" in: sky130A_mr.drc:433 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"inside" in: sky130A_mr.drc:438 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"width" in: sky130A_mr.drc:439 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:440 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +END: 65/20 (diff) +START: 65/44 (tap) +"rectangles" in: sky130A_mr.drc:447 + Polygons (raw): 138456 (flat) 2 (hierarchical) + Elapsed: 0.350s Memory: 1640.00M +"width" in: sky130A_mr.drc:447 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.220s Memory: 1640.00M +"polygons" in: sky130A_mr.drc:447 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"edges" in: sky130A_mr.drc:450 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"outside_part" in: sky130A_mr.drc:451 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s 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80/20 (tunm) +"width" in: sky130A_mr.drc:470 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:470 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"space" in: sky130A_mr.drc:474 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:474 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"output" in: sky130A_mr.drc:478 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +END: 80/20 (tunm) +START: 80/20 (thkox) +"-" in: sky130A_mr.drc:486 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"width" in: sky130A_mr.drc:487 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1640.00M +"output" in: sky130A_mr.drc:487 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"space" in: sky130A_mr.drc:491 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 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1512.00M +END: 74/20 (rdl) +START: 79/20 (urpm) +"width" in: sky130A_mr.drc:582 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:582 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"space" in: sky130A_mr.drc:586 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:586 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1512.00M +END: 79/20 (urpm) +START: 95/20 (npc) +"width" in: sky130A_mr.drc:594 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 2.810s Memory: 1512.00M +"output" in: sky130A_mr.drc:594 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1512.00M +"space" in: sky130A_mr.drc:595 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 3.010s Memory: 1576.00M +"output" in: sky130A_mr.drc:595 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1512.00M +END: 95/20 (npc) +START: 93/44 (nsdm) +"-" in: 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sky130A_mr.drc:660 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:662 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"inside" in: sky130A_mr.drc:664 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"width" in: sky130A_mr.drc:665 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:666 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1512.00M +"inside" in: sky130A_mr.drc:668 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"space" in: sky130A_mr.drc:669 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:670 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"inside" in: sky130A_mr.drc:672 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1512.00M +"space" in: sky130A_mr.drc:673 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"with_internal_angle" in: sky130A_mr.drc:674 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"output" in: sky130A_mr.drc:675 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +END: 93/44 (nsdm) +START: 94/20 (psdm) +"-" in: sky130A_mr.drc:735 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.000s Memory: 1512.00M +"space" in: sky130A_mr.drc:736 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 13.290s Memory: 1768.00M +"output" in: sky130A_mr.drc:737 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.180s Memory: 1640.00M +"outside" in: sky130A_mr.drc:739 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.000s Memory: 1640.00M +"width" in: sky130A_mr.drc:740 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 9.640s Memory: 1658.00M +"output" in: sky130A_mr.drc:741 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.180s Memory: 1658.00M +"width" in: sky130A_mr.drc:743 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 9.600s Memory: 1658.00M +"polygons" in: sky130A_mr.drc:743 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1658.00M +"interacting" in: sky130A_mr.drc:743 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"edges" in: sky130A_mr.drc:745 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"outside_part" in: sky130A_mr.drc:745 + Edges: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"interacting" in: sky130A_mr.drc:744 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:746 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:748 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 13.320s Memory: 1914.00M +"polygons" in: sky130A_mr.drc:748 + Polygons (raw): 0 (flat) 0 (hierarchical) + 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sky130A_mr.drc:912 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"sized" in: sky130A_mr.drc:915 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:919 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:919 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1658.00M +"space" in: sky130A_mr.drc:927 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"with_internal_angle" in: sky130A_mr.drc:927 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:927 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"&" in: sky130A_mr.drc:933 + Polygons (raw): 207684 (flat) 3 (hierarchical) + Elapsed: 1.670s Memory: 1658.00M +"separation" in: sky130A_mr.drc:934 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 1.570s Memory: 1658.00M +"output" in: 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sky130A_mr.drc:976 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +END: 61/20 (nsm) +START: 89/44 (capm) +"width" in: sky130A_mr.drc:981 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:981 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:985 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:985 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"&" in: sky130A_mr.drc:989 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"sized" in: sky130A_mr.drc:989 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"isolated" in: sky130A_mr.drc:991 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"polygons" in: sky130A_mr.drc:992 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"-" in: sky130A_mr.drc:993 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:994 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"not_interacting" in: sky130A_mr.drc:995 + Polygons (raw): 15538 (flat) 15538 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"separation" in: sky130A_mr.drc:995 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:999 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"enclosing" in: sky130A_mr.drc:1004 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1004 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.040s Memory: 1658.00M +"enclosing" in: sky130A_mr.drc:1008 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1008 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"separation" in: sky130A_mr.drc:1012 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1012 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"not_interacting" in: sky130A_mr.drc:1016 + Polygons (raw): 15538 (flat) 15538 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"separation" in: sky130A_mr.drc:1016 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1016 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +END: 89/44 (capm) +START: 97/44 (cap2m) +"width" in: sky130A_mr.drc:1024 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1024 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:1028 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1028 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1658.00M +"interacting" in: sky130A_mr.drc:1033 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"isolated" in: sky130A_mr.drc:1034 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1035 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"interacting" in: sky130A_mr.drc:1036 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"isolated" in: sky130A_mr.drc:1036 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1036 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"&" in: sky130A_mr.drc:1041 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"enclosing" in: sky130A_mr.drc:1042 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1043 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"enclosing" in: sky130A_mr.drc:1044 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1044 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"enclosing" in: sky130A_mr.drc:1048 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1048 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"separation" in: sky130A_mr.drc:1052 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1658.00M +"output" in: sky130A_mr.drc:1052 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"not_interacting" in: sky130A_mr.drc:1056 + Polygons (raw): 897 (flat) 897 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"separation" in: sky130A_mr.drc:1056 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1056 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +END: 97/44 (cap2m) +FEOL section +START: 75/20 (hvi) +"-" in: sky130A_mr.drc:1649 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"width" in: sky130A_mr.drc:1650 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1650 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:1654 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1654 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +END: 75/20 (hvi) +START: 125/20 (hvntm) +"-" in: sky130A_mr.drc:1662 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"width" in: sky130A_mr.drc:1663 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"output" in: sky130A_mr.drc:1663 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +"space" in: sky130A_mr.drc:1667 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.070s Memory: 1658.00M +"output" in: sky130A_mr.drc:1667 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1658.00M +END: 125/20 (hvntm) +Writing report database: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml .. +Total elapsed: 286.650s Memory: 1634.00M +Args: + sram_exclude: false + feol: true + beol: false + floating_met: false + offgrid: false + seal: + +Cell exclusion list: + rule | cell + nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses + +release 2026.03.30_01.00 diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_feol_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.log new file mode 100644 index 00000000..5187633f --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.log @@ -0,0 +1,79 @@ +"polygons" in: met_min_ca_density.lydrc:35 + Polygons (raw): 2373996 (flat) 3848 (hierarchical) + Elapsed: 0.220s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:36 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.120s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:38 + Polygons (raw): 2234360 (flat) 10752 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:39 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.200s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:41 + Polygons (raw): 22178 (flat) 22178 (hierarchical) + Elapsed: 0.200s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:42 + Polygons (raw): 49591 (flat) 49591 (hierarchical) + Elapsed: 0.190s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:44 + Polygons (raw): 15693 (flat) 15693 (hierarchical) + Elapsed: 0.170s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:45 + Polygons (raw): 48854 (flat) 48854 (hierarchical) + Elapsed: 0.220s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:47 + Polygons (raw): 1081 (flat) 1081 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:48 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:49 + Polygons (raw): 12970 (flat) 12970 (hierarchical) + Elapsed: 0.010s Memory: 1022.00M +"polygons" in: met_min_ca_density.lydrc:51 + Polygons (raw): 345 (flat) 345 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"input" in: met_min_ca_density.lydrc:53 + Polygons (raw): 2 (flat) 2 (hierarchical) + Elapsed: 0.150s Memory: 1022.00M +"area" in: met_min_ca_density.lydrc:55 + Elapsed: 0.300s Memory: 1005.00M +"polygons" in: met_min_ca_density.lydrc:59 + Polygons (raw): 2373996 (flat) 3848 (hierarchical) + Elapsed: 0.140s Memory: 1005.00M +"area" in: met_min_ca_density.lydrc:59 + Elapsed: 20.490s Memory: 1328.00M +li1_ca_density is 0.8063325962284986 +"polygons" in: met_min_ca_density.lydrc:69 + Polygons (raw): 2234360 (flat) 10752 (hierarchical) + Elapsed: 0.150s Memory: 1328.00M +"area" in: met_min_ca_density.lydrc:69 + Elapsed: 21.070s Memory: 1328.00M +m1_ca_density is 0.9156508587620642 +"polygons" in: met_min_ca_density.lydrc:79 + Polygons (raw): 22178 (flat) 22178 (hierarchical) + Elapsed: 0.200s Memory: 1328.00M +"area" in: met_min_ca_density.lydrc:79 + Elapsed: 0.420s Memory: 1361.00M +m2_ca_density is 0.9986061017181662 +"polygons" in: met_min_ca_density.lydrc:89 + Polygons (raw): 15693 (flat) 15693 (hierarchical) + Elapsed: 0.190s Memory: 1361.00M +"area" in: met_min_ca_density.lydrc:89 + Elapsed: 0.330s Memory: 1361.00M +m3_ca_density is 0.9983377085879125 +"polygons" in: met_min_ca_density.lydrc:99 + Polygons (raw): 1081 (flat) 1081 (hierarchical) + Elapsed: 0.180s Memory: 1361.00M +"area" in: met_min_ca_density.lydrc:99 + Elapsed: 0.340s Memory: 1361.00M +m4_ca_density is 0.8357823108509106 +"polygons" in: met_min_ca_density.lydrc:109 + Polygons (raw): 345 (flat) 345 (hierarchical) + Elapsed: 0.020s Memory: 1361.00M +"area" in: met_min_ca_density.lydrc:109 + Elapsed: 0.230s Memory: 1361.00M +m5_ca_density is 0.8441720672478207 +Writing report database: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml .. +Total elapsed: 50.510s Memory: 1337.00M diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_met_min_ca_density_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.log new file mode 100644 index 00000000..56f84a3e --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.log @@ -0,0 +1,773 @@ +"input" in: sky130A_mr.drc:182 + Polygons (raw): 556000 (flat) 203 (hierarchical) + Elapsed: 0.250s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:183 + Polygons (raw): 138456 (flat) 2 (hierarchical) + Elapsed: 0.150s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:184 + Polygons (raw): 555952 (flat) 80 (hierarchical) + Elapsed: 0.130s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:185 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:186 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:187 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:188 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:189 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:190 + Polygons (raw): 555954 (flat) 82 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:191 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:192 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:193 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:194 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:195 + Polygons (raw): 557581 (flat) 460 (hierarchical) + Elapsed: 0.140s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:196 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:197 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:198 + Polygons (raw): 625180 (flat) 81 (hierarchical) + Elapsed: 0.140s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:199 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:200 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:201 + Polygons (raw): 277696 (flat) 85 (hierarchical) + Elapsed: 0.140s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:202 + Polygons (raw): 2992871 (flat) 2207 (hierarchical) + Elapsed: 0.150s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:204 + Polygons (raw): 2361125 (flat) 3252 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:205 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:206 + Polygons (raw): 7749718 (flat) 3616 (hierarchical) + Elapsed: 0.110s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:208 + Polygons (raw): 1122452 (flat) 10588 (hierarchical) + Elapsed: 0.130s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:209 + Polygons (raw): 63404 (flat) 63404 (hierarchical) + Elapsed: 0.230s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:211 + Polygons (raw): 21155 (flat) 21155 (hierarchical) + Elapsed: 0.170s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:212 + Polygons (raw): 49591 (flat) 49591 (hierarchical) + Elapsed: 0.210s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:214 + Polygons (raw): 15538 (flat) 15538 (hierarchical) + Elapsed: 0.160s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:215 + Polygons (raw): 48854 (flat) 48854 (hierarchical) + Elapsed: 0.190s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:217 + Polygons (raw): 897 (flat) 897 (hierarchical) + Elapsed: 0.180s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:218 + Polygons (raw): 12970 (flat) 12970 (hierarchical) + Elapsed: 0.020s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:220 + Polygons (raw): 173 (flat) 173 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:222 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:223 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:224 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:225 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"polygons" in: sky130A_mr.drc:226 + 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Memory: 1022.00M +DRC section +OFFGRID-ANGLES section +"ongrid" in: sky130A_mr.drc:1677 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"output" in: sky130A_mr.drc:1677 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"with_angle" in: sky130A_mr.drc:1681 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"output" in: sky130A_mr.drc:1681 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1022.00M +"ongrid" in: sky130A_mr.drc:1685 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 9.410s Memory: 1177.00M +"output" in: sky130A_mr.drc:1685 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1177.00M +"with_angle" in: sky130A_mr.drc:1686 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1177.00M +"output" in: sky130A_mr.drc:1686 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 1177.00M +"ongrid" in: sky130A_mr.drc:1690 + Edge pairs: 0 (flat) 0 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0.000s Memory: 1218.00M +"with_angle" in: sky130A_mr.drc:1721 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"output" in: sky130A_mr.drc:1721 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"ongrid" in: sky130A_mr.drc:1722 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 1.130s Memory: 1218.00M +"output" in: sky130A_mr.drc:1722 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1218.00M +"with_angle" in: sky130A_mr.drc:1723 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"output" in: sky130A_mr.drc:1723 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"ongrid" in: sky130A_mr.drc:1724 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"output" in: sky130A_mr.drc:1724 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1218.00M +"with_angle" in: sky130A_mr.drc:1725 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s 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1218.00M +"ongrid" in: sky130A_mr.drc:1730 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 9.430s Memory: 1242.00M +"output" in: sky130A_mr.drc:1730 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1242.00M +"with_angle" in: sky130A_mr.drc:1731 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 1242.00M +"output" in: sky130A_mr.drc:1731 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1242.00M +"ongrid" in: sky130A_mr.drc:1732 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 1.400s Memory: 1242.00M +"output" in: sky130A_mr.drc:1732 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 1242.00M +"with_angle" in: sky130A_mr.drc:1733 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1242.00M +"output" in: sky130A_mr.drc:1733 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 1242.00M +"ongrid" in: sky130A_mr.drc:1737 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 19.930s Memory: 1370.00M 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+"with_angle" in: sky130A_mr.drc:1742 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1742 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1743 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 20.680s Memory: 3248.00M +"output" in: sky130A_mr.drc:1743 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1744 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"output" in: sky130A_mr.drc:1744 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1745 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.690s Memory: 3248.00M +"output" in: sky130A_mr.drc:1745 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1746 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 3248.00M +"output" in: sky130A_mr.drc:1746 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1747 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.470s Memory: 3248.00M +"output" in: sky130A_mr.drc:1747 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1748 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"output" in: sky130A_mr.drc:1748 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1749 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.610s Memory: 3248.00M +"output" in: sky130A_mr.drc:1749 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1750 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"output" in: sky130A_mr.drc:1750 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1751 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.400s Memory: 3248.00M +"output" in: sky130A_mr.drc:1751 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1752 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1752 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1753 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.600s Memory: 3248.00M +"output" in: sky130A_mr.drc:1753 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1754 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"output" in: sky130A_mr.drc:1754 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1755 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1755 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1756 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1756 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1757 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.400s Memory: 3248.00M +"output" in: sky130A_mr.drc:1757 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1758 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1758 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1759 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.370s Memory: 3248.00M +"output" in: sky130A_mr.drc:1759 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1760 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"output" in: sky130A_mr.drc:1760 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1761 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.300s Memory: 3248.00M +"output" in: sky130A_mr.drc:1761 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.020s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1762 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1762 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1763 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1763 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1764 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1764 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1765 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1765 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1766 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1766 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1767 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1767 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1768 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1768 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1769 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1769 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.030s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1770 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1770 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1774 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1774 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1775 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1775 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1776 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1776 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.010s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1777 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1777 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1778 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1778 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"with_angle" in: sky130A_mr.drc:1782 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1782 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"ongrid" in: sky130A_mr.drc:1786 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +"output" in: sky130A_mr.drc:1786 + Edge pairs: 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 3248.00M +Writing report database: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml .. +Total elapsed: 182.180s Memory: 3097.00M +Args: + sram_exclude: false + feol: false + beol: false + floating_met: false + offgrid: true + seal: + +Cell exclusion list: + rule | cell + nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses + +release 2026.03.30_01.00 diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_offgrid_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.log new file mode 100644 index 00000000..1ec32f29 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.log @@ -0,0 +1,29 @@ +Running pin_label_purposes_overlapping_drawing.rb.drc on file=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml + deep:true tiled:false threads:2 +--- #err|description, table for cell: user_project_wrapper +NO-Check ---- pwell:64/44/EMP 122/16/dat 64/59/EMP 44/16/EMP 44/5/EMP + ---- nwell:64/20/dat 64/16/dat 64/5/EMP + ---- diff:65/20/dat 65/16/EMP 65/6/EMP + ---- tap:65/44/dat 65/48/EMP 65/5/EMP + ---- poly:66/20/dat 66/16/EMP 66/5/EMP + ---- licon1:66/44/dat 66/58/EMP + ---- li1:67/20/dat 67/16/dat 67/5/EMP + ---- mcon:67/44/dat 67/48/EMP + ---- met1:68/20/dat 68/16/dat 68/5/EMP + ---- via:68/44/dat 68/58/EMP + ---- met2:69/20/dat 69/16/dat 69/5/EMP + ---- via2:69/44/dat 69/58/EMP + ---- met3:70/20/dat 70/16/dat 70/5/EMP + ---- via3:70/44/dat 70/48/EMP + ---- met4:71/20/dat 71/16/dat 71/5/EMP + ---- via4:71/44/dat 71/48/EMP + ---- met5:72/20/dat 72/16/dat 72/5/EMP + ---- pad:76/20/EMP 76/5/EMP 76/16/EMP + ---- pnp:82/44/EMP 82/59/EMP + ---- npn:82/20/EMP 82/5/EMP + ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP + ---- inductor:82/24/EMP 82/25/EMP + 0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper +Writing report... +VmPeak: 1669612 kB +VmHWM: 1207572 kB diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_pin_label_purposes_overlapping_drawing_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.log new file mode 100644 index 00000000..2cd28472 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.log @@ -0,0 +1,6 @@ +writing to /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_no_zero_areas.gds +0 zero-area shapes +0 zero-length paths, 0 zero-length paths deleted. +0 total zero-area objects, 0 total objects deleted. +VmPeak: 1428224 kB +VmHWM: 1231716 kB diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/klayout_zeroarea_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/lvs.log b/precheck_results/12_MAY_2026___07_45_39/logs/lvs.log new file mode 100644 index 00000000..db3a34d0 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/lvs.log @@ -0,0 +1,2549 @@ +BEGIN: Tue May 12 08:17:26 2026 +Netgen 1.5.272 compiled on Wed Apr 22 16:24:02 UTC 2026 +Warning: netgen command 'format' use fully-qualified name '::netgen::format' +Warning: netgen command 'global' use fully-qualified name '::netgen::global' +Reading layout /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/ext/user_project_wrapper.gds.spice... +Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__nfet_01v8 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__diode_pw2nd_05v5 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__res_generic_po +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_nfet_01v8 +Creating placeholder cell definition. +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice... +Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__nfet_01v8 +Creating placeholder cell definition. +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_20_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_40_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_60_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_80_12.spice... +Reading source /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice... +Call to undefined subcircuit sky130_fd_pr__res_generic_po +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_nfet_01v8 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__diode_pw2nd_05v5 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_pr__special_pfet_01v8_hvt +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_sc_hd__nand2_2 +Creating placeholder cell definition. +Call to undefined subcircuit sky130_fd_sc_hd__nor2_2 +Creating placeholder cell definition. +Reading source /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v... +Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. +Note: Implicit pin HI in instance user_proj_example_142 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_143 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_144 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_145 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_146 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_147 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_148 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_149 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_150 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_151 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_152 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_153 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_154 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_155 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_156 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_157 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_158 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_159 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_160 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_161 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_162 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_163 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_164 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_165 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_166 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_167 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_168 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_169 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_170 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_171 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_172 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_173 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_174 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_175 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_176 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_177 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_178 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_179 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_180 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_181 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_182 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_183 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_184 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_185 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_186 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_187 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_188 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_189 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_190 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_191 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_192 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_193 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_194 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_195 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_196 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_197 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_198 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_199 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_200 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_201 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_202 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_203 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_204 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_205 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_206 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_207 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_208 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_209 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_210 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_211 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_212 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_213 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_214 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_215 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_216 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_217 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_218 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_219 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_220 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_221 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_222 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_223 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_224 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_225 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_226 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_227 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_228 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_229 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_230 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_231 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_232 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_233 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_234 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_235 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_236 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_237 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_238 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_239 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_240 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_241 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_242 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_243 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_244 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_245 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_246 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_247 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_248 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_249 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_250 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_251 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_252 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_253 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_254 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_255 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_256 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_257 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_258 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_259 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_260 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_261 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_262 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_263 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_264 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_265 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_266 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_267 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_268 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_269 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_270 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_271 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin HI in instance user_proj_example_141 of sky130_fd_sc_hd__conb_1 in cell user_proj_example +Note: Implicit pin X in instance clkload0 of sky130_fd_sc_hd__clkbuf_8 in cell user_proj_example +Note: Implicit pin X in instance clkload1 of sky130_fd_sc_hd__clkbuf_4 in cell user_proj_example +Note: Implicit pin X in instance clkload2 of sky130_fd_sc_hd__clkbuf_4 in cell user_proj_example +Reading source /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v... +Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. +Treating empty subcircuits as black-box cells +Generating JSON file result + +Reading setup file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/sky130A_setup.tcl + +Model sky130_fd_pr__res_generic_po pin 1 == 2 +No property value found for device sky130_fd_pr__res_generic_po +No property mult found for device sky130_fd_pr__res_generic_po +Model sky130_fd_pr__res_generic_po pin 1 == 2 +No property value found for device sky130_fd_pr__res_generic_po +No property mult found for device sky130_fd_pr__res_generic_po +Model sky130_fd_pr__nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__nfet_01v8 +No property sa found for device sky130_fd_pr__nfet_01v8 +No property sb found for device sky130_fd_pr__nfet_01v8 +No property sd found for device sky130_fd_pr__nfet_01v8 +No property nf found for device sky130_fd_pr__nfet_01v8 +No property nrd found for device sky130_fd_pr__nfet_01v8 +No property nrs found for device sky130_fd_pr__nfet_01v8 +No property area found for device sky130_fd_pr__nfet_01v8 +No property perim found for device sky130_fd_pr__nfet_01v8 +No property topography found for device sky130_fd_pr__nfet_01v8 +Model sky130_fd_pr__nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__nfet_01v8 +No property sa found for device sky130_fd_pr__nfet_01v8 +No property sb found for device sky130_fd_pr__nfet_01v8 +No property sd found for device sky130_fd_pr__nfet_01v8 +No property nf found for device sky130_fd_pr__nfet_01v8 +No property nrd found for device sky130_fd_pr__nfet_01v8 +No property nrs found for device sky130_fd_pr__nfet_01v8 +No property area found for device sky130_fd_pr__nfet_01v8 +No property perim found for device sky130_fd_pr__nfet_01v8 +No property topography found for device sky130_fd_pr__nfet_01v8 +Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3 +No property mult found for device sky130_fd_pr__pfet_01v8_hvt +No property sa found for device sky130_fd_pr__pfet_01v8_hvt +No property sb found for device sky130_fd_pr__pfet_01v8_hvt +No property sd found for device sky130_fd_pr__pfet_01v8_hvt +No property nf found for device sky130_fd_pr__pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__pfet_01v8_hvt +No property area found for device sky130_fd_pr__pfet_01v8_hvt +No property perim found for device sky130_fd_pr__pfet_01v8_hvt +No property topography found for device sky130_fd_pr__pfet_01v8_hvt +Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3 +No property mult found for device sky130_fd_pr__pfet_01v8_hvt +No property sa found for device sky130_fd_pr__pfet_01v8_hvt +No property sb found for device sky130_fd_pr__pfet_01v8_hvt +No property sd found for device sky130_fd_pr__pfet_01v8_hvt +No property nf found for device sky130_fd_pr__pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__pfet_01v8_hvt +No property area found for device sky130_fd_pr__pfet_01v8_hvt +No property perim found for device sky130_fd_pr__pfet_01v8_hvt +No property topography found for device sky130_fd_pr__pfet_01v8_hvt +Model sky130_fd_pr__special_nfet_01v8 pin 1 == 3 +No property mult found for device sky130_fd_pr__special_nfet_01v8 +No property sa found for device sky130_fd_pr__special_nfet_01v8 +No property sb found for device sky130_fd_pr__special_nfet_01v8 +No property sd found for device sky130_fd_pr__special_nfet_01v8 +No property nf found for device sky130_fd_pr__special_nfet_01v8 +No property nrd found for device sky130_fd_pr__special_nfet_01v8 +No property nrs found for device sky130_fd_pr__special_nfet_01v8 +No property area found for device sky130_fd_pr__special_nfet_01v8 +No property perim found for device sky130_fd_pr__special_nfet_01v8 +No property topography found for device sky130_fd_pr__special_nfet_01v8 +Model sky130_fd_pr__special_nfet_01v8 pin 1 == 3 +No property as found for device sky130_fd_pr__special_nfet_01v8 +No property ad found for device sky130_fd_pr__special_nfet_01v8 +No property ps found for device sky130_fd_pr__special_nfet_01v8 +No property pd found for device sky130_fd_pr__special_nfet_01v8 +No property mult found for device sky130_fd_pr__special_nfet_01v8 +No property sa found for device sky130_fd_pr__special_nfet_01v8 +No property sb found for device sky130_fd_pr__special_nfet_01v8 +No property sd found for device sky130_fd_pr__special_nfet_01v8 +No property nf found for device sky130_fd_pr__special_nfet_01v8 +No property nrd found for device sky130_fd_pr__special_nfet_01v8 +No property nrs found for device sky130_fd_pr__special_nfet_01v8 +No property area found for device sky130_fd_pr__special_nfet_01v8 +No property perim found for device sky130_fd_pr__special_nfet_01v8 +No property topography found for device sky130_fd_pr__special_nfet_01v8 +Model sky130_fd_pr__special_pfet_01v8_hvt pin 1 == 3 +No property as found for device sky130_fd_pr__special_pfet_01v8_hvt +No property ad found for device sky130_fd_pr__special_pfet_01v8_hvt +No property ps found for device sky130_fd_pr__special_pfet_01v8_hvt +No property pd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property mult found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sa found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sb found for device sky130_fd_pr__special_pfet_01v8_hvt +No property sd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nf found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nrd found for device sky130_fd_pr__special_pfet_01v8_hvt +No property nrs found for device sky130_fd_pr__special_pfet_01v8_hvt +No property area found for device sky130_fd_pr__special_pfet_01v8_hvt +No property perim found for device sky130_fd_pr__special_pfet_01v8_hvt +No property topography found for device sky130_fd_pr__special_pfet_01v8_hvt +No property value found for device sky130_fd_pr__diode_pw2nd_05v5 +No property mult found for device sky130_fd_pr__diode_pw2nd_05v5 +No property value found for device sky130_fd_pr__diode_pw2nd_05v5 +No property mult found for device sky130_fd_pr__diode_pw2nd_05v5 +Matching pins of sky130_fd_pr__nfet_01v8 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__pfet_01v8_hvt in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__diode_pw2nd_05v5 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__diode_pw2nd_05v5 |Circuit 2: sky130_fd_pr__diode_pw2nd_05v5 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__res_generic_po in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__res_generic_po |Circuit 2: sky130_fd_pr__res_generic_po +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Matching pins of sky130_fd_pr__special_nfet_01v8 in circuits 1 and 2 + +Subcircuit pins: +Circuit 1: sky130_fd_pr__special_nfet_01v8 |Circuit 2: sky130_fd_pr__special_nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_sc_hd__and3_1 and EZ_sky130_fd_sc_hd__and3_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3_1 in circuit 1 and sky130_fd_sc_hd__and3_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2b_1 and EZ_sky130_fd_sc_hd__and2b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2b_1 in circuit 1 and sky130_fd_sc_hd__and2b_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2b_2 and EZ_sky130_fd_sc_hd__and2b_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2b_2 in circuit 1 and sky130_fd_sc_hd__and2b_2 in circuit 2 +Device classes sky130_fd_sc_hd__a21bo_1 and EZ_sky130_fd_sc_hd__a21bo_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21bo_1 in circuit 1 and sky130_fd_sc_hd__a21bo_1 in circuit 2 +Device classes sky130_fd_sc_hd__tapvpwrvgnd_1 and EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit 1 and sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2_1 and EZ_sky130_fd_sc_hd__and2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_1 in circuit 1 and sky130_fd_sc_hd__and2_1 in circuit 2 +Device classes sky130_fd_sc_hd__and2_2 and EZ_sky130_fd_sc_hd__and2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_2 in circuit 1 and sky130_fd_sc_hd__and2_2 in circuit 2 +Device classes sky130_fd_sc_hd__and2_4 and EZ_sky130_fd_sc_hd__and2_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and2_4 in circuit 1 and sky130_fd_sc_hd__and2_4 in circuit 2 +Device classes sky130_fd_sc_hd__decap_3 and EZ_sky130_fd_sc_hd__decap_3 are equivalent. +Equating EZ_sky130_fd_sc_hd__decap_3 in circuit 1 and sky130_fd_sc_hd__decap_3 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_1 and EZ_sky130_fd_sc_hd__clkbuf_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_1 in circuit 1 and sky130_fd_sc_hd__clkbuf_1 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_2 and EZ_sky130_fd_sc_hd__clkbuf_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_2 in circuit 1 and sky130_fd_sc_hd__clkbuf_2 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_4 and EZ_sky130_fd_sc_hd__clkbuf_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_4 in circuit 1 and sky130_fd_sc_hd__clkbuf_4 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_8 and EZ_sky130_fd_sc_hd__clkbuf_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_8 in circuit 1 and sky130_fd_sc_hd__clkbuf_8 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_1 and EZ_sky130_fd_sc_hd__nand2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_1 in circuit 1 and sky130_fd_sc_hd__nand2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_2 and EZ_sky130_fd_sc_hd__nand2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_2 in circuit 1 and sky130_fd_sc_hd__nand2_2 in circuit 2 +Device classes sky130_fd_sc_hd__nand2_8 and EZ_sky130_fd_sc_hd__nand2_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2_8 in circuit 1 and sky130_fd_sc_hd__nand2_8 in circuit 2 +Device classes sky130_fd_sc_hd__conb_1 and EZ_sky130_fd_sc_hd__conb_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__conb_1 in circuit 1 and sky130_fd_sc_hd__conb_1 in circuit 2 +Device classes sky130_fd_sc_hd__buf_12 and EZ_sky130_fd_sc_hd__buf_12 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_12 in circuit 1 and sky130_fd_sc_hd__buf_12 in circuit 2 +Device classes sky130_fd_sc_hd__a21boi_1 and EZ_sky130_fd_sc_hd__a21boi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21boi_1 in circuit 1 and sky130_fd_sc_hd__a21boi_1 in circuit 2 +Device classes sky130_fd_sc_hd__o211ai_4 and EZ_sky130_fd_sc_hd__o211ai_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__o211ai_4 in circuit 1 and sky130_fd_sc_hd__o211ai_4 in circuit 2 +Device classes sky130_ef_sc_hd__decap_40_12 and EZ_sky130_ef_sc_hd__decap_40_12 are equivalent. +Equating EZ_sky130_ef_sc_hd__decap_40_12 in circuit 1 and sky130_ef_sc_hd__decap_40_12 in circuit 2 +Device classes sky130_fd_sc_hd__a32o_1 and EZ_sky130_fd_sc_hd__a32o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a32o_1 in circuit 1 and sky130_fd_sc_hd__a32o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a32o_4 and EZ_sky130_fd_sc_hd__a32o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a32o_4 in circuit 1 and sky130_fd_sc_hd__a32o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a22o_1 and EZ_sky130_fd_sc_hd__a22o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a22o_1 in circuit 1 and sky130_fd_sc_hd__a22o_1 in circuit 2 +Device classes sky130_fd_sc_hd__xnor2_1 and EZ_sky130_fd_sc_hd__xnor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__xnor2_1 in circuit 1 and sky130_fd_sc_hd__xnor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__xnor2_2 and EZ_sky130_fd_sc_hd__xnor2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__xnor2_2 in circuit 1 and sky130_fd_sc_hd__xnor2_2 in circuit 2 +Device classes sky130_fd_sc_hd__buf_1 and EZ_sky130_fd_sc_hd__buf_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_1 in circuit 1 and sky130_fd_sc_hd__buf_1 in circuit 2 +Device classes sky130_fd_sc_hd__buf_2 and EZ_sky130_fd_sc_hd__buf_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_2 in circuit 1 and sky130_fd_sc_hd__buf_2 in circuit 2 +Device classes sky130_fd_sc_hd__buf_4 and EZ_sky130_fd_sc_hd__buf_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_4 in circuit 1 and sky130_fd_sc_hd__buf_4 in circuit 2 +Device classes sky130_fd_sc_hd__buf_6 and EZ_sky130_fd_sc_hd__buf_6 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_6 in circuit 1 and sky130_fd_sc_hd__buf_6 in circuit 2 +Device classes sky130_fd_sc_hd__buf_8 and EZ_sky130_fd_sc_hd__buf_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__buf_8 in circuit 1 and sky130_fd_sc_hd__buf_8 in circuit 2 +Device classes sky130_fd_sc_hd__o211a_1 and EZ_sky130_fd_sc_hd__o211a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o211a_1 in circuit 1 and sky130_fd_sc_hd__o211a_1 in circuit 2 +Device classes sky130_fd_sc_hd__mux2_1 and EZ_sky130_fd_sc_hd__mux2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__mux2_1 in circuit 1 and sky130_fd_sc_hd__mux2_1 in circuit 2 +Device classes sky130_fd_sc_hd__diode_2 and EZ_sky130_fd_sc_hd__diode_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__diode_2 in circuit 1 and sky130_fd_sc_hd__diode_2 in circuit 2 +Device classes sky130_fd_sc_hd__a221o_1 and EZ_sky130_fd_sc_hd__a221o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a221o_1 in circuit 1 and sky130_fd_sc_hd__a221o_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand3b_4 and EZ_sky130_fd_sc_hd__nand3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand3b_4 in circuit 1 and sky130_fd_sc_hd__nand3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__a211o_1 and EZ_sky130_fd_sc_hd__a211o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a211o_1 in circuit 1 and sky130_fd_sc_hd__a211o_1 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_1 and EZ_sky130_fd_sc_hd__nor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_1 in circuit 1 and sky130_fd_sc_hd__nor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_2 and EZ_sky130_fd_sc_hd__nor2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_2 in circuit 1 and sky130_fd_sc_hd__nor2_2 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_4 and EZ_sky130_fd_sc_hd__nor2_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_4 in circuit 1 and sky130_fd_sc_hd__nor2_4 in circuit 2 +Device classes sky130_fd_sc_hd__inv_2 and EZ_sky130_fd_sc_hd__inv_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__inv_2 in circuit 1 and sky130_fd_sc_hd__inv_2 in circuit 2 +Device classes sky130_fd_sc_hd__nor2_8 and EZ_sky130_fd_sc_hd__nor2_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__nor2_8 in circuit 1 and sky130_fd_sc_hd__nor2_8 in circuit 2 +Device classes sky130_fd_sc_hd__a41o_1 and EZ_sky130_fd_sc_hd__a41o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41o_1 in circuit 1 and sky130_fd_sc_hd__a41o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a41o_4 and EZ_sky130_fd_sc_hd__a41o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41o_4 in circuit 1 and sky130_fd_sc_hd__a41o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_1 and EZ_sky130_fd_sc_hd__a31o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_1 in circuit 1 and sky130_fd_sc_hd__a31o_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_2 and EZ_sky130_fd_sc_hd__a31o_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_2 in circuit 1 and sky130_fd_sc_hd__a31o_2 in circuit 2 +Device classes sky130_fd_sc_hd__o32a_1 and EZ_sky130_fd_sc_hd__o32a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o32a_1 in circuit 1 and sky130_fd_sc_hd__o32a_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31o_4 and EZ_sky130_fd_sc_hd__a31o_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31o_4 in circuit 1 and sky130_fd_sc_hd__a31o_4 in circuit 2 +Device classes sky130_fd_sc_hd__a21o_1 and EZ_sky130_fd_sc_hd__a21o_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21o_1 in circuit 1 and sky130_fd_sc_hd__a21o_1 in circuit 2 +Device classes sky130_fd_sc_hd__or3_4 and EZ_sky130_fd_sc_hd__or3_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3_4 in circuit 1 and sky130_fd_sc_hd__or3_4 in circuit 2 +Device classes sky130_fd_sc_hd__a41oi_4 and EZ_sky130_fd_sc_hd__a41oi_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a41oi_4 in circuit 1 and sky130_fd_sc_hd__a41oi_4 in circuit 2 +Device classes sky130_fd_sc_hd__dlygate4sd3_1 and EZ_sky130_fd_sc_hd__dlygate4sd3_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__dlygate4sd3_1 in circuit 1 and sky130_fd_sc_hd__dlygate4sd3_1 in circuit 2 +Device classes sky130_fd_sc_hd__o21ai_1 and EZ_sky130_fd_sc_hd__o21ai_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o21ai_1 in circuit 1 and sky130_fd_sc_hd__o21ai_1 in circuit 2 +Device classes sky130_fd_sc_hd__a21oi_1 and EZ_sky130_fd_sc_hd__a21oi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21oi_1 in circuit 1 and sky130_fd_sc_hd__a21oi_1 in circuit 2 +Device classes sky130_fd_sc_hd__a21oi_4 and EZ_sky130_fd_sc_hd__a21oi_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__a21oi_4 in circuit 1 and sky130_fd_sc_hd__a21oi_4 in circuit 2 +Device classes sky130_fd_sc_hd__xor2_1 and EZ_sky130_fd_sc_hd__xor2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__xor2_1 in circuit 1 and sky130_fd_sc_hd__xor2_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand2b_1 and EZ_sky130_fd_sc_hd__nand2b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand2b_1 in circuit 1 and sky130_fd_sc_hd__nand2b_1 in circuit 2 +Device classes sky130_fd_sc_hd__or3b_2 and EZ_sky130_fd_sc_hd__or3b_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3b_2 in circuit 1 and sky130_fd_sc_hd__or3b_2 in circuit 2 +Device classes sky130_fd_sc_hd__or3b_4 and EZ_sky130_fd_sc_hd__or3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__or3b_4 in circuit 1 and sky130_fd_sc_hd__or3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__and4_1 and EZ_sky130_fd_sc_hd__and4_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_1 in circuit 1 and sky130_fd_sc_hd__and4_1 in circuit 2 +Device classes sky130_fd_sc_hd__clkbuf_16 and EZ_sky130_fd_sc_hd__clkbuf_16 are equivalent. +Equating EZ_sky130_fd_sc_hd__clkbuf_16 in circuit 1 and sky130_fd_sc_hd__clkbuf_16 in circuit 2 +Device classes sky130_fd_sc_hd__and4_2 and EZ_sky130_fd_sc_hd__and4_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_2 in circuit 1 and sky130_fd_sc_hd__and4_2 in circuit 2 +Device classes sky130_fd_sc_hd__and4_4 and EZ_sky130_fd_sc_hd__and4_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and4_4 in circuit 1 and sky130_fd_sc_hd__and4_4 in circuit 2 +Device classes sky130_fd_sc_hd__o31a_1 and EZ_sky130_fd_sc_hd__o31a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o31a_1 in circuit 1 and sky130_fd_sc_hd__o31a_1 in circuit 2 +Device classes sky130_fd_sc_hd__o21a_1 and EZ_sky130_fd_sc_hd__o21a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o21a_1 in circuit 1 and sky130_fd_sc_hd__o21a_1 in circuit 2 +Device classes sky130_fd_sc_hd__o2bb2a_1 and EZ_sky130_fd_sc_hd__o2bb2a_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o2bb2a_1 in circuit 1 and sky130_fd_sc_hd__o2bb2a_1 in circuit 2 +Device classes sky130_fd_sc_hd__or2_1 and EZ_sky130_fd_sc_hd__or2_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__or2_1 in circuit 1 and sky130_fd_sc_hd__or2_1 in circuit 2 +Device classes sky130_fd_sc_hd__or2_2 and EZ_sky130_fd_sc_hd__or2_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__or2_2 in circuit 1 and sky130_fd_sc_hd__or2_2 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_1 and EZ_sky130_fd_sc_hd__dfxtp_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_1 in circuit 1 and sky130_fd_sc_hd__dfxtp_1 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_2 and EZ_sky130_fd_sc_hd__dfxtp_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_2 in circuit 1 and sky130_fd_sc_hd__dfxtp_2 in circuit 2 +Device classes sky130_fd_sc_hd__dfxtp_4 and EZ_sky130_fd_sc_hd__dfxtp_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__dfxtp_4 in circuit 1 and sky130_fd_sc_hd__dfxtp_4 in circuit 2 +Device classes sky130_fd_sc_hd__o31ai_1 and EZ_sky130_fd_sc_hd__o31ai_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__o31ai_1 in circuit 1 and sky130_fd_sc_hd__o31ai_1 in circuit 2 +Device classes sky130_fd_sc_hd__a31oi_1 and EZ_sky130_fd_sc_hd__a31oi_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__a31oi_1 in circuit 1 and sky130_fd_sc_hd__a31oi_1 in circuit 2 +Device classes sky130_fd_sc_hd__nand4_2 and EZ_sky130_fd_sc_hd__nand4_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__nand4_2 in circuit 1 and sky130_fd_sc_hd__nand4_2 in circuit 2 +Device classes sky130_fd_sc_hd__and3b_1 and EZ_sky130_fd_sc_hd__and3b_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3b_1 in circuit 1 and sky130_fd_sc_hd__and3b_1 in circuit 2 +Device classes sky130_fd_sc_hd__and3b_4 and EZ_sky130_fd_sc_hd__and3b_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__and3b_4 in circuit 1 and sky130_fd_sc_hd__and3b_4 in circuit 2 +Device classes sky130_fd_sc_hd__fill_1 and EZ_sky130_fd_sc_hd__fill_1 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_1 in circuit 1 and sky130_fd_sc_hd__fill_1 in circuit 2 +Device classes sky130_fd_sc_hd__fill_2 and EZ_sky130_fd_sc_hd__fill_2 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_2 in circuit 1 and sky130_fd_sc_hd__fill_2 in circuit 2 +Device classes sky130_fd_sc_hd__fill_4 and EZ_sky130_fd_sc_hd__fill_4 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_4 in circuit 1 and sky130_fd_sc_hd__fill_4 in circuit 2 +Device classes sky130_fd_sc_hd__fill_8 and EZ_sky130_fd_sc_hd__fill_8 are equivalent. +Equating EZ_sky130_fd_sc_hd__fill_8 in circuit 1 and sky130_fd_sc_hd__fill_8 in circuit 2 +Comparison output logged to file /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report +Logging to file "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report" enabled +Circuit sky130_fd_pr__pfet_01v8_hvt contains no devices. +Circuit sky130_fd_pr__nfet_01v8 contains no devices. +Circuit sky130_fd_pr__diode_pw2nd_05v5 contains no devices. +Circuit sky130_fd_pr__res_generic_po contains no devices. +Circuit sky130_fd_pr__special_nfet_01v8 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_4' +Circuit EZ_sky130_fd_sc_hd__fill_4 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_4' +Circuit sky130_fd_sc_hd__fill_4 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_4 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_ef_sc_hd__decap_40_12' +Circuit EZ_sky130_ef_sc_hd__decap_40_12 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. +Contents of circuit 2: Circuit: 'sky130_ef_sc_hd__decap_40_12' +Circuit sky130_ef_sc_hd__decap_40_12 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_1' +Circuit EZ_sky130_fd_sc_hd__fill_1 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_1' +Circuit sky130_fd_sc_hd__fill_1 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_1 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_2' +Circuit EZ_sky130_fd_sc_hd__fill_2 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_2' +Circuit sky130_fd_sc_hd__fill_2 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_2 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__decap_3' +Circuit EZ_sky130_fd_sc_hd__decap_3 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_3' +Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 4 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__tapvpwrvgnd_1' +Circuit EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. +Circuit contains 0 nets, and 2 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1' +Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. +Circuit contains 0 nets, and 2 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__diode_2' +Circuit EZ_sky130_fd_sc_hd__diode_2 contains 1 device instances. + Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1 +Circuit contains 2 nets, and 3 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__diode_2' +Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances. + Class: sky130_fd_pr__diode_pw2nd_05v5 instances: 1 +Circuit contains 2 nets, and 3 disconnected pins. + +Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. +Circuit 1 contains 2 nets, Circuit 2 contains 2 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__mux2_1' +Circuit EZ_sky130_fd_sc_hd__mux2_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__mux2_1' +Circuit sky130_fd_sc_hd__mux2_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__fill_8' +Circuit EZ_sky130_fd_sc_hd__fill_8 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__fill_8' +Circuit sky130_fd_sc_hd__fill_8 contains 0 device instances. +Circuit contains 0 nets, and 4 disconnected pins. + +Circuit EZ_sky130_fd_sc_hd__fill_8 contains no devices. + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dlygate4sd3_1' +Circuit EZ_sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dlygate4sd3_1' +Circuit sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o21ai_1' +Circuit EZ_sky130_fd_sc_hd__o21ai_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21ai_1' +Circuit sky130_fd_sc_hd__o21ai_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_1' +Circuit EZ_sky130_fd_sc_hd__nor2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_1' +Circuit sky130_fd_sc_hd__nor2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__conb_1' +Circuit EZ_sky130_fd_sc_hd__conb_1 contains 2 device instances. + Class: sky130_fd_pr__res_generic_po instances: 2 +Circuit contains 4 nets, and 2 disconnected pins. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__conb_1' +Circuit sky130_fd_sc_hd__conb_1 contains 2 device instances. + Class: sky130_fd_pr__res_generic_po instances: 2 +Circuit contains 4 nets, and 2 disconnected pins. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 4 nets, Circuit 2 contains 4 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_12' +Circuit EZ_sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_12' +Circuit sky130_fd_sc_hd__buf_12 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_12' +Circuit EZ_sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_12' +Circuit sky130_fd_sc_hd__buf_12 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o31ai_1' +Circuit EZ_sky130_fd_sc_hd__o31ai_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o31ai_1' +Circuit sky130_fd_sc_hd__o31ai_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_1' +Circuit EZ_sky130_fd_sc_hd__dfxtp_1 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_1' +Circuit sky130_fd_sc_hd__dfxtp_1 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_1' +Circuit EZ_sky130_fd_sc_hd__and2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_1' +Circuit sky130_fd_sc_hd__and2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_4' +Circuit EZ_sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_4' +Circuit sky130_fd_sc_hd__buf_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_4' +Circuit EZ_sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_4' +Circuit sky130_fd_sc_hd__buf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_1' +Circuit EZ_sky130_fd_sc_hd__a32o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_1' +Circuit sky130_fd_sc_hd__a32o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a221o_1' +Circuit EZ_sky130_fd_sc_hd__a221o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a221o_1' +Circuit sky130_fd_sc_hd__a221o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xor2_1' +Circuit EZ_sky130_fd_sc_hd__xor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xor2_1' +Circuit sky130_fd_sc_hd__xor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_1' +Circuit EZ_sky130_fd_sc_hd__buf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_1' +Circuit sky130_fd_sc_hd__buf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_1' +Circuit EZ_sky130_fd_sc_hd__and3b_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_1' +Circuit sky130_fd_sc_hd__and3b_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_4' +Circuit EZ_sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_4' +Circuit sky130_fd_sc_hd__and3b_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3b_4' +Circuit EZ_sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3b_4' +Circuit sky130_fd_sc_hd__and3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and3_1' +Circuit EZ_sky130_fd_sc_hd__and3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3_1' +Circuit sky130_fd_sc_hd__and3_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_4' +Circuit EZ_sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_4' +Circuit sky130_fd_sc_hd__dfxtp_4 contains 30 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 11 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 15 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_4' +Circuit EZ_sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_4' +Circuit sky130_fd_sc_hd__dfxtp_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21boi_1' +Circuit EZ_sky130_fd_sc_hd__a21boi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21boi_1' +Circuit sky130_fd_sc_hd__a21boi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_1' +Circuit EZ_sky130_fd_sc_hd__a31o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_1' +Circuit sky130_fd_sc_hd__a31o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_8' +Circuit EZ_sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8' +Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 10 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 10 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_8' +Circuit EZ_sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8' +Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_1' +Circuit EZ_sky130_fd_sc_hd__a21oi_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_1' +Circuit sky130_fd_sc_hd__a21oi_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_4' +Circuit EZ_sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_4' +Circuit sky130_fd_sc_hd__a31o_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 12 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_4' +Circuit EZ_sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_4' +Circuit sky130_fd_sc_hd__a31o_4 contains 13 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 15 nets. + +Circuit 1 contains 13 devices, Circuit 2 contains 13 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_4' +Circuit EZ_sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_4' +Circuit sky130_fd_sc_hd__clkbuf_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_4' +Circuit EZ_sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_4' +Circuit sky130_fd_sc_hd__clkbuf_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_2' +Circuit EZ_sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_2' +Circuit sky130_fd_sc_hd__dfxtp_2 contains 26 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 9 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 13 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__dfxtp_2' +Circuit EZ_sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_2' +Circuit sky130_fd_sc_hd__dfxtp_2 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 + Class: sky130_fd_pr__special_nfet_01v8 instances: 4 +Circuit contains 18 nets. + +Circuit 1 contains 24 devices, Circuit 2 contains 24 devices. +Circuit 1 contains 18 nets, Circuit 2 contains 18 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21bo_1' +Circuit EZ_sky130_fd_sc_hd__a21bo_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21bo_1' +Circuit sky130_fd_sc_hd__a21bo_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_4' +Circuit EZ_sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_4' +Circuit sky130_fd_sc_hd__a41o_4 contains 28 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 14 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 14 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_4' +Circuit EZ_sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_4' +Circuit sky130_fd_sc_hd__a41o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o2bb2a_1' +Circuit EZ_sky130_fd_sc_hd__o2bb2a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o2bb2a_1' +Circuit sky130_fd_sc_hd__o2bb2a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a211o_1' +Circuit EZ_sky130_fd_sc_hd__a211o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a211o_1' +Circuit sky130_fd_sc_hd__a211o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_4' +Circuit EZ_sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_4' +Circuit sky130_fd_sc_hd__or3b_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_4' +Circuit EZ_sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_4' +Circuit sky130_fd_sc_hd__or3b_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41oi_4' +Circuit EZ_sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41oi_4' +Circuit sky130_fd_sc_hd__a41oi_4 contains 40 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 20 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 20 +Circuit contains 14 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41oi_4' +Circuit EZ_sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41oi_4' +Circuit sky130_fd_sc_hd__a41oi_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 14 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a22o_1' +Circuit EZ_sky130_fd_sc_hd__a22o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a22o_1' +Circuit sky130_fd_sc_hd__a22o_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_2' +Circuit EZ_sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_2' +Circuit sky130_fd_sc_hd__and2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_2' +Circuit EZ_sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_2' +Circuit sky130_fd_sc_hd__and2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_16' +Circuit EZ_sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16' +Circuit sky130_fd_sc_hd__clkbuf_16 contains 40 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 20 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 20 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_16' +Circuit EZ_sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16' +Circuit sky130_fd_sc_hd__clkbuf_16 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_2' +Circuit EZ_sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_2' +Circuit sky130_fd_sc_hd__clkbuf_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_2' +Circuit EZ_sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_2' +Circuit sky130_fd_sc_hd__clkbuf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_2' +Circuit EZ_sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_2' +Circuit sky130_fd_sc_hd__or2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_2' +Circuit EZ_sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_2' +Circuit sky130_fd_sc_hd__or2_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand4_2' +Circuit EZ_sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand4_2' +Circuit sky130_fd_sc_hd__nand4_2 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand4_2' +Circuit EZ_sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand4_2' +Circuit sky130_fd_sc_hd__nand4_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_1' +Circuit EZ_sky130_fd_sc_hd__and4_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_1' +Circuit sky130_fd_sc_hd__and4_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__inv_2' +Circuit EZ_sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_2' +Circuit sky130_fd_sc_hd__inv_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 6 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__inv_2' +Circuit EZ_sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_2' +Circuit sky130_fd_sc_hd__inv_2 contains 2 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 1 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 1 +Circuit contains 6 nets. + +Circuit 1 contains 2 devices, Circuit 2 contains 2 devices. +Circuit 1 contains 6 nets, Circuit 2 contains 6 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2b_1' +Circuit EZ_sky130_fd_sc_hd__nand2b_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2b_1' +Circuit sky130_fd_sc_hd__nand2b_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3_4' +Circuit EZ_sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3_4' +Circuit sky130_fd_sc_hd__or3_4 contains 14 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 7 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 7 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3_4' +Circuit EZ_sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3_4' +Circuit sky130_fd_sc_hd__or3_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or2_1' +Circuit EZ_sky130_fd_sc_hd__or2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_1' +Circuit sky130_fd_sc_hd__or2_1 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_4' +Circuit EZ_sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_4' +Circuit sky130_fd_sc_hd__a21oi_4 contains 24 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 12 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 12 +Circuit contains 10 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21oi_4' +Circuit EZ_sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_4' +Circuit sky130_fd_sc_hd__a21oi_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 10 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_1' +Circuit EZ_sky130_fd_sc_hd__nand2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_1' +Circuit sky130_fd_sc_hd__nand2_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_4' +Circuit EZ_sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4' +Circuit sky130_fd_sc_hd__a32o_4 contains 28 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 14 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 14 +Circuit contains 15 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a32o_4' +Circuit EZ_sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4' +Circuit sky130_fd_sc_hd__a32o_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a21o_1' +Circuit EZ_sky130_fd_sc_hd__a21o_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21o_1' +Circuit sky130_fd_sc_hd__a21o_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_2' +Circuit EZ_sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_2' +Circuit sky130_fd_sc_hd__a31o_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31o_2' +Circuit EZ_sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31o_2' +Circuit sky130_fd_sc_hd__a31o_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_2' +Circuit EZ_sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_2' +Circuit sky130_fd_sc_hd__and4_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_2' +Circuit EZ_sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_2' +Circuit sky130_fd_sc_hd__and4_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_1' +Circuit EZ_sky130_fd_sc_hd__xnor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_1' +Circuit sky130_fd_sc_hd__xnor2_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_2' +Circuit EZ_sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_2' +Circuit sky130_fd_sc_hd__nand2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_2' +Circuit EZ_sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_2' +Circuit sky130_fd_sc_hd__nand2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__clkbuf_1' +Circuit EZ_sky130_fd_sc_hd__clkbuf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_1' +Circuit sky130_fd_sc_hd__clkbuf_1 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o32a_1' +Circuit EZ_sky130_fd_sc_hd__o32a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o32a_1' +Circuit sky130_fd_sc_hd__o32a_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_2' +Circuit EZ_sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_2' +Circuit sky130_fd_sc_hd__buf_2 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_2' +Circuit EZ_sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_2' +Circuit sky130_fd_sc_hd__buf_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_4' +Circuit EZ_sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_4' +Circuit sky130_fd_sc_hd__and4_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 13 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and4_4' +Circuit EZ_sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_4' +Circuit sky130_fd_sc_hd__and4_4 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o21a_1' +Circuit EZ_sky130_fd_sc_hd__o21a_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21a_1' +Circuit sky130_fd_sc_hd__o21a_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_8' +Circuit EZ_sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_8' +Circuit sky130_fd_sc_hd__buf_8 contains 22 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 11 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 11 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_8' +Circuit EZ_sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_8' +Circuit sky130_fd_sc_hd__buf_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_6' +Circuit EZ_sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_6' +Circuit sky130_fd_sc_hd__buf_6 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 7 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__buf_6' +Circuit EZ_sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_6' +Circuit sky130_fd_sc_hd__buf_6 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 7 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 7 nets, Circuit 2 contains 7 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a41o_1' +Circuit EZ_sky130_fd_sc_hd__a41o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_1' +Circuit sky130_fd_sc_hd__a41o_1 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 15 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 15 nets, Circuit 2 contains 15 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_8' +Circuit EZ_sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_8' +Circuit sky130_fd_sc_hd__nand2_8 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand2_8' +Circuit EZ_sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_8' +Circuit sky130_fd_sc_hd__nand2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_4' +Circuit EZ_sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4' +Circuit sky130_fd_sc_hd__and2_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 9 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2_4' +Circuit EZ_sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4' +Circuit sky130_fd_sc_hd__and2_4 contains 6 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 3 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 3 +Circuit contains 9 nets. + +Circuit 1 contains 6 devices, Circuit 2 contains 6 devices. +Circuit 1 contains 9 nets, Circuit 2 contains 9 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand3b_4' +Circuit EZ_sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand3b_4' +Circuit sky130_fd_sc_hd__nand3b_4 contains 26 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 13 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 13 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nand3b_4' +Circuit EZ_sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand3b_4' +Circuit sky130_fd_sc_hd__nand3b_4 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 11 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_2' +Circuit EZ_sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_2' +Circuit sky130_fd_sc_hd__nor2_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_2' +Circuit EZ_sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_2' +Circuit sky130_fd_sc_hd__nor2_2 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_1' +Circuit EZ_sky130_fd_sc_hd__and2b_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_1' +Circuit sky130_fd_sc_hd__and2b_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_2' +Circuit EZ_sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_2' +Circuit sky130_fd_sc_hd__xnor2_2 contains 20 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 10 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 10 +Circuit contains 11 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__xnor2_2' +Circuit EZ_sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__xnor2_2' +Circuit sky130_fd_sc_hd__xnor2_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 11 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 11 nets, Circuit 2 contains 11 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_8' +Circuit EZ_sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_8' +Circuit sky130_fd_sc_hd__nor2_8 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_8' +Circuit EZ_sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_8' +Circuit sky130_fd_sc_hd__nor2_8 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211ai_4' +Circuit EZ_sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211ai_4' +Circuit sky130_fd_sc_hd__o211ai_4 contains 32 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 16 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 16 +Circuit contains 14 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211ai_4' +Circuit EZ_sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211ai_4' +Circuit sky130_fd_sc_hd__o211ai_4 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 14 nets. + +Circuit 1 contains 12 devices, Circuit 2 contains 12 devices. +Circuit 1 contains 14 nets, Circuit 2 contains 14 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o211a_1' +Circuit EZ_sky130_fd_sc_hd__o211a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o211a_1' +Circuit sky130_fd_sc_hd__o211a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_2' +Circuit EZ_sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_2' +Circuit sky130_fd_sc_hd__or3b_2 contains 12 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 6 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 6 +Circuit contains 12 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__or3b_2' +Circuit EZ_sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3b_2' +Circuit sky130_fd_sc_hd__or3b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 12 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__o31a_1' +Circuit EZ_sky130_fd_sc_hd__o31a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o31a_1' +Circuit sky130_fd_sc_hd__o31a_1 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 13 nets. + +Circuit 1 contains 10 devices, Circuit 2 contains 10 devices. +Circuit 1 contains 13 nets, Circuit 2 contains 13 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_4' +Circuit EZ_sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_4' +Circuit sky130_fd_sc_hd__nor2_4 contains 16 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 8 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 8 +Circuit contains 8 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__nor2_4' +Circuit EZ_sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_4' +Circuit sky130_fd_sc_hd__nor2_4 contains 4 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 2 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 2 +Circuit contains 8 nets. + +Circuit 1 contains 4 devices, Circuit 2 contains 4 devices. +Circuit 1 contains 8 nets, Circuit 2 contains 8 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_2' +Circuit EZ_sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_2' +Circuit sky130_fd_sc_hd__and2b_2 contains 10 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 5 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 5 +Circuit contains 10 nets. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__and2b_2' +Circuit EZ_sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2b_2' +Circuit sky130_fd_sc_hd__and2b_2 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 10 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 10 nets, Circuit 2 contains 10 nets. + + +Contents of circuit 1: Circuit: 'EZ_sky130_fd_sc_hd__a31oi_1' +Circuit EZ_sky130_fd_sc_hd__a31oi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. +Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a31oi_1' +Circuit sky130_fd_sc_hd__a31oi_1 contains 8 device instances. + Class: sky130_fd_pr__nfet_01v8 instances: 4 + Class: sky130_fd_pr__pfet_01v8_hvt instances: 4 +Circuit contains 12 nets. + +Circuit 1 contains 8 devices, Circuit 2 contains 8 devices. +Circuit 1 contains 12 nets, Circuit 2 contains 12 nets. + + +Contents of circuit 1: Circuit: 'user_proj_example' +Circuit user_proj_example contains 555952 device instances. + Class: EZ_sky130_fd_sc_hd__and3_1 instances: 6 + Class: EZ_sky130_fd_sc_hd__and2b_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 69228 + Class: EZ_sky130_fd_sc_hd__and2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__and2_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__decap_3 instances: 1278 + Class: EZ_sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: EZ_sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: EZ_sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: EZ_sky130_fd_sc_hd__nand2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nand2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand2_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__conb_1 instances: 131 + Class: EZ_sky130_fd_sc_hd__buf_12 instances: 81 + Class: EZ_sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: EZ_sky130_ef_sc_hd__decap_40_12 instances: 275484 + Class: EZ_sky130_fd_sc_hd__a32o_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__a32o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a22o_1 instances: 7 + Class: EZ_sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__buf_1 instances: 35 + Class: EZ_sky130_fd_sc_hd__buf_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__buf_4 instances: 18 + Class: EZ_sky130_fd_sc_hd__buf_6 instances: 3 + Class: EZ_sky130_fd_sc_hd__buf_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__o211a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__mux2_1 instances: 17 + Class: EZ_sky130_fd_sc_hd__diode_2 instances: 644 + Class: EZ_sky130_fd_sc_hd__a221o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a211o_1 instances: 8 + Class: EZ_sky130_fd_sc_hd__nor2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nor2_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__inv_2 instances: 7 + Class: EZ_sky130_fd_sc_hd__nor2_8 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__a31o_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__o32a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21o_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or3_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: EZ_sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: EZ_sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__xor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or3b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__or3b_4 instances: 7 + Class: EZ_sky130_fd_sc_hd__and4_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: EZ_sky130_fd_sc_hd__and4_2 instances: 3 + Class: EZ_sky130_fd_sc_hd__and4_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__o31a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o21a_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or2_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: EZ_sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: EZ_sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: EZ_sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand4_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__fill_1 instances: 69626 + Class: EZ_sky130_fd_sc_hd__fill_2 instances: 69894 + Class: EZ_sky130_fd_sc_hd__fill_4 instances: 68575 + Class: EZ_sky130_fd_sc_hd__fill_8 instances: 505 +Circuit contains 910 nets, and 286 disconnected pins. +Contents of circuit 2: Circuit: 'user_proj_example' +Circuit user_proj_example contains 555952 device instances. + Class: sky130_fd_sc_hd__a41o_1 instances: 1 + Class: sky130_fd_sc_hd__a41o_4 instances: 1 + Class: sky130_fd_sc_hd__a31o_1 instances: 5 + Class: sky130_fd_sc_hd__a31o_2 instances: 1 + Class: sky130_fd_sc_hd__a31o_4 instances: 1 + Class: sky130_fd_sc_hd__a21o_1 instances: 2 + Class: sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_1 instances: 35 + Class: sky130_fd_sc_hd__nand4_2 instances: 1 + Class: sky130_fd_sc_hd__buf_2 instances: 2 + Class: sky130_fd_sc_hd__buf_4 instances: 18 + Class: sky130_fd_sc_hd__buf_6 instances: 3 + Class: sky130_fd_sc_hd__buf_8 instances: 2 + Class: sky130_fd_sc_hd__and3b_1 instances: 1 + Class: sky130_fd_sc_hd__and3b_4 instances: 2 + Class: sky130_fd_sc_hd__xor2_1 instances: 3 + Class: sky130_fd_sc_hd__and4_1 instances: 3 + Class: sky130_fd_sc_hd__and4_2 instances: 3 + Class: sky130_fd_sc_hd__and4_4 instances: 1 + Class: sky130_fd_sc_hd__inv_2 instances: 7 + Class: sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: sky130_fd_sc_hd__or3_4 instances: 1 + Class: sky130_fd_sc_hd__and2b_1 instances: 2 + Class: sky130_fd_sc_hd__conb_1 instances: 131 + Class: sky130_fd_sc_hd__and2b_2 instances: 1 + Class: sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_12 instances: 81 + Class: sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: sky130_fd_sc_hd__and3_1 instances: 6 + Class: sky130_fd_sc_hd__decap_3 instances: 1278 + Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: sky130_fd_sc_hd__or2_1 instances: 2 + Class: sky130_fd_sc_hd__or2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_1 instances: 5 + Class: sky130_fd_sc_hd__nand2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_8 instances: 2 + Class: sky130_fd_sc_hd__mux2_1 instances: 17 + Class: sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: sky130_fd_sc_hd__and2_1 instances: 3 + Class: sky130_fd_sc_hd__and2_2 instances: 2 + Class: sky130_fd_sc_hd__and2_4 instances: 2 + Class: sky130_fd_sc_hd__o32a_1 instances: 1 + Class: sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: sky130_fd_sc_hd__o211a_1 instances: 1 + Class: sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: sky130_fd_sc_hd__diode_2 instances: 644 + Class: sky130_fd_sc_hd__a221o_1 instances: 1 + Class: sky130_fd_sc_hd__a211o_1 instances: 8 + Class: sky130_fd_sc_hd__or3b_2 instances: 1 + Class: sky130_fd_sc_hd__or3b_4 instances: 7 + Class: sky130_fd_sc_hd__a32o_1 instances: 3 + Class: sky130_fd_sc_hd__a32o_4 instances: 1 + Class: sky130_fd_sc_hd__a22o_1 instances: 7 + Class: sky130_fd_sc_hd__o31a_1 instances: 1 + Class: sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: sky130_fd_sc_hd__o21a_1 instances: 2 + Class: sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 69228 + Class: sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: sky130_fd_sc_hd__fill_1 instances: 69626 + Class: sky130_fd_sc_hd__fill_2 instances: 69894 + Class: sky130_fd_sc_hd__fill_4 instances: 68575 + Class: sky130_fd_sc_hd__fill_8 instances: 505 + Class: sky130_ef_sc_hd__decap_40_12 instances: 275484 + Class: sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_1 instances: 5 + Class: sky130_fd_sc_hd__nor2_2 instances: 1 + Class: sky130_fd_sc_hd__nor2_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. + +Circuit was modified by parallel/series device merging. +New circuit summary: + +Contents of circuit 1: Circuit: 'user_proj_example' +Circuit user_proj_example contains 944 device instances. + Class: EZ_sky130_fd_sc_hd__and3_1 instances: 6 + Class: EZ_sky130_fd_sc_hd__and2b_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__and2_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__and2_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__decap_3 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: EZ_sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: EZ_sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: EZ_sky130_fd_sc_hd__nand2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nand2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand2_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__conb_1 instances: 131 + Class: EZ_sky130_fd_sc_hd__buf_12 instances: 81 + Class: EZ_sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: EZ_sky130_ef_sc_hd__decap_40_12 instances: 1 + Class: EZ_sky130_fd_sc_hd__a32o_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__a32o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a22o_1 instances: 7 + Class: EZ_sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__buf_1 instances: 35 + Class: EZ_sky130_fd_sc_hd__buf_2 instances: 2 + Class: EZ_sky130_fd_sc_hd__buf_4 instances: 18 + Class: EZ_sky130_fd_sc_hd__buf_6 instances: 3 + Class: EZ_sky130_fd_sc_hd__buf_8 instances: 2 + Class: EZ_sky130_fd_sc_hd__o211a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__mux2_1 instances: 17 + Class: EZ_sky130_fd_sc_hd__diode_2 instances: 219 + Class: EZ_sky130_fd_sc_hd__a221o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a211o_1 instances: 8 + Class: EZ_sky130_fd_sc_hd__nor2_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__nor2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__nor2_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__inv_2 instances: 7 + Class: EZ_sky130_fd_sc_hd__nor2_8 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_1 instances: 5 + Class: EZ_sky130_fd_sc_hd__a31o_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__o32a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31o_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21o_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or3_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: EZ_sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: EZ_sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__xor2_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or3b_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__or3b_4 instances: 7 + Class: EZ_sky130_fd_sc_hd__and4_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: EZ_sky130_fd_sc_hd__and4_2 instances: 3 + Class: EZ_sky130_fd_sc_hd__and4_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__o31a_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__o21a_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: EZ_sky130_fd_sc_hd__or2_1 instances: 2 + Class: EZ_sky130_fd_sc_hd__or2_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: EZ_sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: EZ_sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: EZ_sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__nand4_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__and3b_4 instances: 2 + Class: EZ_sky130_fd_sc_hd__fill_1 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_2 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_4 instances: 1 + Class: EZ_sky130_fd_sc_hd__fill_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. +Contents of circuit 2: Circuit: 'user_proj_example' +Circuit user_proj_example contains 944 device instances. + Class: sky130_fd_sc_hd__a41o_1 instances: 1 + Class: sky130_fd_sc_hd__a41o_4 instances: 1 + Class: sky130_fd_sc_hd__a31o_1 instances: 5 + Class: sky130_fd_sc_hd__a31o_2 instances: 1 + Class: sky130_fd_sc_hd__a31o_4 instances: 1 + Class: sky130_fd_sc_hd__a21o_1 instances: 2 + Class: sky130_fd_sc_hd__clkbuf_16 instances: 5 + Class: sky130_fd_sc_hd__dfxtp_1 instances: 13 + Class: sky130_fd_sc_hd__dfxtp_2 instances: 5 + Class: sky130_fd_sc_hd__o31ai_1 instances: 1 + Class: sky130_fd_sc_hd__dfxtp_4 instances: 15 + Class: sky130_fd_sc_hd__a31oi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_1 instances: 35 + Class: sky130_fd_sc_hd__nand4_2 instances: 1 + Class: sky130_fd_sc_hd__buf_2 instances: 2 + Class: sky130_fd_sc_hd__buf_4 instances: 18 + Class: sky130_fd_sc_hd__buf_6 instances: 3 + Class: sky130_fd_sc_hd__buf_8 instances: 2 + Class: sky130_fd_sc_hd__and3b_1 instances: 1 + Class: sky130_fd_sc_hd__and3b_4 instances: 2 + Class: sky130_fd_sc_hd__xor2_1 instances: 3 + Class: sky130_fd_sc_hd__and4_1 instances: 3 + Class: sky130_fd_sc_hd__and4_2 instances: 3 + Class: sky130_fd_sc_hd__and4_4 instances: 1 + Class: sky130_fd_sc_hd__inv_2 instances: 7 + Class: sky130_fd_sc_hd__clkbuf_1 instances: 14 + Class: sky130_fd_sc_hd__clkbuf_2 instances: 1 + Class: sky130_fd_sc_hd__clkbuf_4 instances: 17 + Class: sky130_fd_sc_hd__clkbuf_8 instances: 9 + Class: sky130_fd_sc_hd__or3_4 instances: 1 + Class: sky130_fd_sc_hd__and2b_1 instances: 2 + Class: sky130_fd_sc_hd__conb_1 instances: 131 + Class: sky130_fd_sc_hd__and2b_2 instances: 1 + Class: sky130_fd_sc_hd__a21boi_1 instances: 1 + Class: sky130_fd_sc_hd__buf_12 instances: 81 + Class: sky130_fd_sc_hd__a21bo_1 instances: 1 + Class: sky130_fd_sc_hd__and3_1 instances: 6 + Class: sky130_fd_sc_hd__decap_3 instances: 1 + Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 218 + Class: sky130_fd_sc_hd__or2_1 instances: 2 + Class: sky130_fd_sc_hd__or2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_1 instances: 5 + Class: sky130_fd_sc_hd__nand2_2 instances: 1 + Class: sky130_fd_sc_hd__nand2_8 instances: 2 + Class: sky130_fd_sc_hd__mux2_1 instances: 17 + Class: sky130_fd_sc_hd__nand3b_4 instances: 1 + Class: sky130_fd_sc_hd__and2_1 instances: 3 + Class: sky130_fd_sc_hd__and2_2 instances: 2 + Class: sky130_fd_sc_hd__and2_4 instances: 2 + Class: sky130_fd_sc_hd__o32a_1 instances: 1 + Class: sky130_fd_sc_hd__xnor2_1 instances: 3 + Class: sky130_fd_sc_hd__xnor2_2 instances: 1 + Class: sky130_fd_sc_hd__o211a_1 instances: 1 + Class: sky130_fd_sc_hd__nand2b_1 instances: 3 + Class: sky130_fd_sc_hd__diode_2 instances: 219 + Class: sky130_fd_sc_hd__a221o_1 instances: 1 + Class: sky130_fd_sc_hd__a211o_1 instances: 8 + Class: sky130_fd_sc_hd__or3b_2 instances: 1 + Class: sky130_fd_sc_hd__or3b_4 instances: 7 + Class: sky130_fd_sc_hd__a32o_1 instances: 3 + Class: sky130_fd_sc_hd__a32o_4 instances: 1 + Class: sky130_fd_sc_hd__a22o_1 instances: 7 + Class: sky130_fd_sc_hd__o31a_1 instances: 1 + Class: sky130_fd_sc_hd__o2bb2a_1 instances: 3 + Class: sky130_fd_sc_hd__o21a_1 instances: 2 + Class: sky130_fd_sc_hd__a41oi_4 instances: 1 + Class: sky130_fd_sc_hd__o21ai_1 instances: 1 + Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1 + Class: sky130_fd_sc_hd__a21oi_1 instances: 11 + Class: sky130_fd_sc_hd__a21oi_4 instances: 2 + Class: sky130_fd_sc_hd__fill_1 instances: 1 + Class: sky130_fd_sc_hd__fill_2 instances: 1 + Class: sky130_fd_sc_hd__fill_4 instances: 1 + Class: sky130_fd_sc_hd__fill_8 instances: 1 + Class: sky130_ef_sc_hd__decap_40_12 instances: 1 + Class: sky130_fd_sc_hd__o211ai_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_1 instances: 5 + Class: sky130_fd_sc_hd__nor2_2 instances: 1 + Class: sky130_fd_sc_hd__nor2_4 instances: 1 + Class: sky130_fd_sc_hd__nor2_8 instances: 1 +Circuit contains 910 nets, and 286 disconnected pins. + +Circuit 1 contains 944 devices, Circuit 2 contains 944 devices. +Circuit 1 contains 910 nets, Circuit 2 contains 910 nets. + + +Contents of circuit 1: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 543 nets, and 102 disconnected pins. +Contents of circuit 2: Circuit: 'user_project_wrapper' +Circuit user_project_wrapper contains 1 device instances. + Class: user_proj_example instances: 1 +Circuit contains 543 nets, and 102 disconnected pins. + +Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. +Circuit 1 contains 543 nets, Circuit 2 contains 543 nets. + + +Final result: +Circuits match uniquely. +. +Logging to file "/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/tmp/lvs.report" disabled +LVS Done. +END: Tue May 12 08:19:35 2026 +Runtime: 0:02:09 (hh:mm:ss) diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/pdks.info b/precheck_results/12_MAY_2026___07_45_39/logs/pdks.info new file mode 100644 index 00000000..20b346e5 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/pdks.info @@ -0,0 +1,2 @@ +Open PDKs 3e0e31dcce8519a7dbb82590346db16d91b7244f +SKY130A PDK unknown \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/precheck.log b/precheck_results/12_MAY_2026___07_45_39/logs/precheck.log new file mode 100644 index 00000000..a2072320 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/precheck.log @@ -0,0 +1,50 @@ +2026-05-12 07:45:39 [INFO] Extracting compressed files in: /tmp/tmp5bbb3lz4/repo +2026-05-12 07:45:39 [INFO] make uncompress produced 2 gds/*.gds file(s): user_proj_example.gds, user_project_wrapper.gds (make exit 0) +2026-05-12 07:45:39 [INFO] Project type: digital +2026-05-12 07:45:39 [INFO] GDS hash (user_project_wrapper): 7dedb0577fede3bf2014261de4d5e78fb372daa1 +2026-05-12 07:45:39 [INFO] Tools: KLayout v0.29.2 | Magic v8.3.471 +2026-05-12 07:45:39 [INFO] PDK: SKY130A unknown +2026-05-12 07:45:40 [INFO] Running 13 checks: [topcell_check, gpio_defines, xor, klayout_feol, klayout_beol, klayout_offgrid, klayout_met_min_ca_density, klayout_pin_label_purposes_overlapping_drawing, klayout_zeroarea, spike_check, illegal_cellname_check, lvs, oeb] +2026-05-12 07:45:42 [INFO] Single top cell 'user_project_wrapper' found +2026-05-12 07:45:42 [INFO] GPIO defines: parsing verilog/rtl/user_defines.v +2026-05-12 07:45:43 [ERROR] GPIO defines: Invalid directives (33): USER_CONFIG_GPIO_5_INIT=13'hXXXX USER_CONFIG_GPIO_6_INIT=13'hXXXX USER_CONFIG_GPIO_7_INIT=13'hXXXX USER_CONFIG_GPIO_8_INIT=13'hXXXX USER_CONFIG_GPIO_9_INIT=13'hXXXX USER_CONFIG_GPIO_10_INIT=13'hXXXX USER_CONFIG_GPIO_11_INIT=13'hXXXX USER_CONFIG_GPIO_12_INIT=13'hXXXX USER_CONFIG_GPIO_13_INIT=13'hXXXX USER_CONFIG_GPIO_25_INIT=13'hXXXX USER_CONFIG_GPIO_26_INIT=13'hXXXX USER_CONFIG_GPIO_27_INIT=13'hXXXX USER_CONFIG_GPIO_28_INIT=13'hXXXX USER_CONFIG_GPIO_29_INIT=13'hXXXX USER_CONFIG_GPIO_30_INIT=13'hXXXX USER_CONFIG_GPIO_31_INIT=13'hXXXX USER_CONFIG_GPIO_32_INIT=13'hXXXX USER_CONFIG_GPIO_33_INIT=13'hXXXX USER_CONFIG_GPIO_34_INIT=13'hXXXX USER_CONFIG_GPIO_35_INIT=13'hXXXX USER_CONFIG_GPIO_36_INIT=13'hXXXX USER_CONFIG_GPIO_37_INIT=13'hXXXX USER_CONFIG_GPIO_14_INIT=13'hXXXX USER_CONFIG_GPIO_15_INIT=13'hXXXX USER_CONFIG_GPIO_16_INIT=13'hXXXX USER_CONFIG_GPIO_17_INIT=13'hXXXX USER_CONFIG_GPIO_18_INIT=13'hXXXX USER_CONFIG_GPIO_19_INIT=13'hXXXX USER_CONFIG_GPIO_20_INIT=13'hXXXX USER_CONFIG_GPIO_21_INIT=13'hXXXX USER_CONFIG_GPIO_22_INIT=13'hXXXX USER_CONFIG_GPIO_23_INIT=13'hXXXX USER_CONFIG_GPIO_24_INIT=13'hXXXX +2026-05-12 07:46:00 [INFO] Total XOR differences: 0 +2026-05-12 07:46:00 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml -rd thr=2 -rd feol=true +2026-05-12 07:50:48 [INFO] No DRC violations found +2026-05-12 07:50:48 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml -rd thr=2 -rd beol=true +2026-05-12 08:03:04 [INFO] No DRC violations found +2026-05-12 08:03:04 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml -rd thr=2 -rd offgrid=true +2026-05-12 08:06:08 [INFO] No DRC violations found +2026-05-12 08:06:08 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/met_min_ca_density.lydrc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml -rd thr=2 +2026-05-12 08:07:02 [INFO] No DRC violations found +2026-05-12 08:07:02 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/pin_label_purposes_overlapping_drawing.rb.drc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd thr=2 -rd top_cell_name=user_project_wrapper +2026-05-12 08:07:35 [INFO] No DRC violations found +2026-05-12 08:07:35 [INFO] Running: klayout -b -r /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/zeroarea.rb.drc -rd input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_zeroarea_check.xml -rd thr=2 -rd cleaned_output=/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_no_zero_areas.gds +2026-05-12 08:07:44 [INFO] No DRC violations found +2026-05-12 08:07:44 [INFO] Running: bash /usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/gdsArea0 -V -m /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +2026-05-12 08:07:51 [INFO] No spikes found +2026-05-12 08:07:53 [INFO] Loading LVS environment from /tmp/tmp5bbb3lz4/repo/lvs/user_project_wrapper/lvs_config.json +2026-05-12 08:07:53 [INFO] EXTRACT_FLATGLOB: +2026-05-12 08:07:53 [INFO] EXTRACT_ABSTRACT: *__fill_* *__fakediode_* *__tapvpwrvgnd_* +2026-05-12 08:07:53 [INFO] EXTRACT_CREATE_SUBCUT: +2026-05-12 08:07:53 [INFO] LVS_FLATTEN: +2026-05-12 08:07:53 [INFO] LVS_NOFLATTEN: +2026-05-12 08:07:53 [INFO] LVS_IGNORE: +2026-05-12 08:07:53 [INFO] LVS_SPICE_FILES: /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap*.spice /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice +2026-05-12 08:07:53 [INFO] LVS_VERILOG_FILES: /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +2026-05-12 08:07:53 [INFO] LAYOUT_FILE: /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +2026-05-12 08:07:53 [INFO] Running: run_be_checks --nooeb +2026-05-12 08:07:53 [INFO] LVS output directory: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39 +2026-05-12 08:19:43 [INFO] Loading LVS environment from /tmp/tmp5bbb3lz4/repo/lvs/user_project_wrapper/lvs_config.json +2026-05-12 08:19:43 [INFO] EXTRACT_FLATGLOB: +2026-05-12 08:19:43 [INFO] EXTRACT_ABSTRACT: *__fill_* *__fakediode_* *__tapvpwrvgnd_* +2026-05-12 08:19:43 [INFO] EXTRACT_CREATE_SUBCUT: +2026-05-12 08:19:43 [INFO] LVS_FLATTEN: +2026-05-12 08:19:43 [INFO] LVS_NOFLATTEN: +2026-05-12 08:19:43 [INFO] LVS_IGNORE: +2026-05-12 08:19:43 [INFO] LVS_SPICE_FILES: /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap*.spice /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice +2026-05-12 08:19:43 [INFO] LVS_VERILOG_FILES: /tmp/tmp5bbb3lz4/repo/verilog/gl/user_proj_example.v /tmp/tmp5bbb3lz4/repo/verilog/gl/user_project_wrapper.v +2026-05-12 08:19:43 [INFO] LAYOUT_FILE: /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds +2026-05-12 08:19:43 [INFO] Running: run_oeb_check --noextract +2026-05-12 08:19:43 [INFO] OEB output directory: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39 +2026-05-12 08:19:51 [ERROR] OEB FAILED (stat=6), see /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/logs/OEB_check.log diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/spike_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/spike_check.log new file mode 100644 index 00000000..f1a7780b --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/spike_check.log @@ -0,0 +1,14 @@ +Running gdsArea0 on file=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds (passive, no gdsFileOut) + args: '-V','-m','/tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml','/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds' +dbu=0.001 Float inv:1000.0 +number shapes: box=234494 path=159 poly=790 +writing marker-DB: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml ... + 0 area-zero shapes, 0 zero-area shapes deleted. + 0 zero-length paths, 0 zero-length paths deleted. + 0 path spikes + 0 path octagonal acute angles + 0 path any-angle acute angles + 0 paths2poly + 0 total errors, 0 total shapes deleted, 0 exit-status. +VmPeak: 1017880 kB +VmHWM: 821568 kB diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/tools.info b/precheck_results/12_MAY_2026___07_45_39/logs/tools.info new file mode 100644 index 00000000..6ad3efd3 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/tools.info @@ -0,0 +1,2 @@ +KLayout: 0.29.2 +Magic: 8.3.471 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.log b/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.log new file mode 100644 index 00000000..9313c0c1 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.log @@ -0,0 +1,378 @@ +Reading file /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds for cell user_project_wrapper +dbu=0.001 +cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950) +cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950) +cell user_project_wrapper dbu-size(width,height)=(3006880,3596220) +cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003) +cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003) +Done. + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design .magicrc for technology sky130A ... +2 Magic internal units = 1 Lambda +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading sky130A Device Generator Menu ... +Loading "/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/erase_box.tcl" from command line. +Input style sky130(vendor): scaleFactor=2, multiplier=2 +CIF input style is now "sky130(vendor)" +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "EZ_sky130_ef_sc_hd__decap_40_12". +Reading "EZ_sky130_fd_sc_hd__decap_3". +Reading "EZ_sky130_fd_sc_hd__fill_1". +Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1". +Reading "EZ_sky130_fd_sc_hd__fill_2". +Reading "EZ_sky130_fd_sc_hd__fill_4". +Reading "EZ_sky130_fd_sc_hd__buf_4". +Reading "EZ_sky130_fd_sc_hd__fill_8". +Reading "EZ_sky130_fd_sc_hd__diode_2". +Reading "EZ_sky130_fd_sc_hd__buf_12". +Reading "EZ_sky130_fd_sc_hd__clkbuf_8". +Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1". +Reading "EZ_sky130_fd_sc_hd__clkbuf_4". +Reading "EZ_sky130_fd_sc_hd__buf_2". +Reading "EZ_sky130_fd_sc_hd__dfxtp_1". +Reading "EZ_sky130_fd_sc_hd__mux2_1". +Reading "EZ_sky130_fd_sc_hd__dfxtp_2". +Reading "EZ_sky130_fd_sc_hd__conb_1". +Reading "EZ_sky130_fd_sc_hd__and2_4". +Reading "EZ_sky130_fd_sc_hd__and2_2". +Reading "EZ_sky130_fd_sc_hd__nand2_8". +Reading "EZ_sky130_fd_sc_hd__nor2_2". +Reading "EZ_sky130_fd_sc_hd__inv_2". +Reading "EZ_sky130_fd_sc_hd__buf_6". +Reading "EZ_sky130_fd_sc_hd__nand3b_4". +Reading "EZ_sky130_fd_sc_hd__a211o_1". +Reading "EZ_sky130_fd_sc_hd__nor2_1". +Reading "EZ_sky130_fd_sc_hd__and3_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_4". +Reading "EZ_sky130_fd_sc_hd__and2b_1". +Reading "EZ_sky130_fd_sc_hd__buf_1". +Reading "EZ_sky130_fd_sc_hd__a22o_1". +Reading "EZ_sky130_fd_sc_hd__a31o_1". +Reading "EZ_sky130_fd_sc_hd__o21a_1". +Reading "EZ_sky130_fd_sc_hd__a221o_1". +Reading "EZ_sky130_fd_sc_hd__a32o_1". +Reading "EZ_sky130_fd_sc_hd__and2_1". +Reading "EZ_sky130_fd_sc_hd__nand2_1". +Reading "EZ_sky130_fd_sc_hd__o2bb2a_1". +Reading "EZ_sky130_fd_sc_hd__a21oi_1". +Reading "EZ_sky130_fd_sc_hd__o21ai_1". +Reading "EZ_sky130_fd_sc_hd__a32o_4". +Reading "EZ_sky130_fd_sc_hd__a21o_1". +Reading "EZ_sky130_fd_sc_hd__or3b_2". +Reading "EZ_sky130_fd_sc_hd__and2b_2". +Reading "EZ_sky130_fd_sc_hd__a31o_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_1". +Reading "EZ_sky130_fd_sc_hd__or3b_4". +Reading "EZ_sky130_fd_sc_hd__and4_1". +Reading "EZ_sky130_fd_sc_hd__a41o_4". +Reading "EZ_sky130_fd_sc_hd__and3b_4". +Reading "EZ_sky130_fd_sc_hd__buf_8". +Reading "EZ_sky130_fd_sc_hd__clkbuf_16". +Reading "EZ_sky130_fd_sc_hd__dfxtp_4". +Reading "EZ_sky130_fd_sc_hd__nor2_8". +Reading "EZ_sky130_fd_sc_hd__or2_1". +Reading "EZ_sky130_fd_sc_hd__o31a_1". +Reading "EZ_sky130_fd_sc_hd__o211a_1". +Reading "EZ_sky130_fd_sc_hd__o32a_1". +Reading "EZ_sky130_fd_sc_hd__a31oi_1". +Reading "EZ_sky130_fd_sc_hd__o31ai_1". +Reading "EZ_sky130_fd_sc_hd__o211ai_4". +Reading "EZ_sky130_fd_sc_hd__a41oi_4". +Reading "EZ_sky130_fd_sc_hd__and4_2". +Reading "EZ_sky130_fd_sc_hd__xor2_1". +Reading "EZ_sky130_fd_sc_hd__or2_2". +Reading "EZ_sky130_fd_sc_hd__nor2_4". +Reading "EZ_sky130_fd_sc_hd__or3_4". +Reading "EZ_sky130_fd_sc_hd__nand2_2". +Reading "EZ_sky130_fd_sc_hd__xnor2_1". +Reading "EZ_sky130_fd_sc_hd__and3b_1". +Reading "EZ_sky130_fd_sc_hd__a31o_2". +Reading "EZ_sky130_fd_sc_hd__a21bo_1". +Reading "EZ_sky130_fd_sc_hd__a21boi_1". +Reading "EZ_sky130_fd_sc_hd__nand2b_1". +Reading "EZ_sky130_fd_sc_hd__xnor2_2". +Reading "EZ_sky130_fd_sc_hd__nand4_2". +Reading "EZ_sky130_fd_sc_hd__a41o_1". +Reading "EZ_sky130_fd_sc_hd__and4_4". +Reading "EZ_sky130_fd_sc_hd__clkbuf_2". +Reading "user_proj_example". + 5000 uses + 10000 uses + 15000 uses + 20000 uses + 25000 uses + 30000 uses + 35000 uses + 40000 uses + 45000 uses + 50000 uses + 55000 uses + 60000 uses + 65000 uses + 70000 uses + 75000 uses + 80000 uses + 85000 uses + 90000 uses + 95000 uses + 100000 uses + 105000 uses + 110000 uses + 115000 uses + 120000 uses + 125000 uses + 130000 uses + 135000 uses + 140000 uses + 145000 uses + 150000 uses + 155000 uses + 160000 uses + 165000 uses + 170000 uses + 175000 uses + 180000 uses + 185000 uses + 190000 uses + 195000 uses + 200000 uses + 205000 uses + 210000 uses + 215000 uses + 220000 uses + 225000 uses + 230000 uses + 235000 uses + 240000 uses + 245000 uses + 250000 uses + 255000 uses + 260000 uses + 265000 uses + 270000 uses + 275000 uses + 280000 uses + 285000 uses + 290000 uses + 295000 uses + 300000 uses + 305000 uses + 310000 uses + 315000 uses + 320000 uses + 325000 uses + 330000 uses + 335000 uses + 340000 uses + 345000 uses + 350000 uses + 355000 uses + 360000 uses + 365000 uses + 370000 uses + 375000 uses + 380000 uses + 385000 uses + 390000 uses + 395000 uses + 400000 uses + 405000 uses + 410000 uses + 415000 uses + 420000 uses + 425000 uses + 430000 uses + 435000 uses + 440000 uses + 445000 uses + 450000 uses + 455000 uses + 460000 uses + 465000 uses + 470000 uses + 475000 uses + 480000 uses + 485000 uses + 490000 uses + 495000 uses + 500000 uses + 505000 uses + 510000 uses + 515000 uses + 520000 uses + 525000 uses + 530000 uses + 535000 uses + 540000 uses + 545000 uses + 550000 uses + 555000 uses +Reading "user_project_wrapper". +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 43.630 x 3520.000 (-43.630, 0.000), ( 0.000, 3520.000) 153577.594 +lambda: 4363.00 x 352000.00 (-4363.00, 0.00 ), ( 0.00, 352000.00) 1535776000.00 +internal: 8726 x 704000 ( -8726, 0 ), ( 0, 704000) 6143104000 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 43.250 x 3520.000 ( 2920.000, 0.000), ( 2963.250, 3520.000) 152240.000 +lambda: 4325.00 x 352000.00 ( 292000.00, 0.00 ), ( 296325.00, 352000.00) 1522400000.00 +internal: 8650 x 704000 ( 584000, 0 ), ( 592650, 704000) 6089600000 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 3006.880 x 38.270 (-43.630, -38.270), ( 2963.250, 0.000) 115073.289 +lambda: 300688.00 x 3827.00 (-4363.00, -3827.00), ( 296325.00, 0.00 ) 1150732928.00 +internal: 601376 x 7654 ( -8726, -7654 ), ( 592650, 0 ) 4602931904 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 3006.880 x 37.950 (-43.630, 3520.000), ( 2963.250, 3557.950) 114111.086 +lambda: 300688.00 x 3795.00 (-4363.00, 352000.00), ( 296325.00, 355795.00) 1141110912.00 +internal: 601376 x 7590 ( -8726, 704000), ( 592650, 711590) 4564443840 + Generating output for cell xor_target + +Magic 8.3 revision 471 - Compiled on Wed Apr 22 16:23:58 UTC 2026. +Starting magic under Tcl interpreter +Using the terminal as the console. +Using NULL graphics device. +Processing system .magicrc file +Sourcing design .magicrc for technology sky130A ... +2 Magic internal units = 1 Lambda +Input style sky130(): scaleFactor=2, multiplier=2 +The following types are not handled by extraction and will be treated as non-electrical types: + ubm +Scaled tech values by 2 / 1 to match internal grid scaling +Loading sky130A Device Generator Menu ... +Loading "/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/erase_box.tcl" from command line. +Input style sky130(vendor): scaleFactor=2, multiplier=2 +CIF input style is now "sky130(vendor)" +Warning: Calma reading is not undoable! I hope that's OK. +Library written using GDS-II Release 3.0 +Library name: user_project_wrapper +Reading "user_project_wrapper". +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 43.630 x 3520.000 (-43.630, 0.000), ( 0.000, 3520.000) 153577.594 +lambda: 4363.00 x 352000.00 (-4363.00, 0.00 ), ( 0.00, 352000.00) 1535776000.00 +internal: 8726 x 704000 ( -8726, 0 ), ( 0, 704000) 6143104000 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 43.250 x 3520.000 ( 2920.000, 0.000), ( 2963.250, 3520.000) 152240.000 +lambda: 4325.00 x 352000.00 ( 292000.00, 0.00 ), ( 296325.00, 352000.00) 1522400000.00 +internal: 8650 x 704000 ( 584000, 0 ), ( 592650, 704000) 6089600000 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 3006.880 x 38.270 (-43.630, -38.270), ( 2963.250, 0.000) 115073.289 +lambda: 300688.00 x 3827.00 (-4363.00, -3827.00), ( 296325.00, 0.00 ) 1150732928.00 +internal: 601376 x 7654 ( -8726, -7654 ), ( 592650, 0 ) 4602931904 +Root cell box: + width x height ( llx, lly ), ( urx, ury ) area (units^2) + +microns: 3006.880 x 37.950 (-43.630, 3520.000), ( 2963.250, 3557.950) 114111.086 +lambda: 300688.00 x 3795.00 (-4363.00, 352000.00), ( 296325.00, 355795.00) 1141110912.00 +internal: 601376 x 7590 ( -8726, 704000), ( 592650, 711590) 4564443840 + Generating output for cell xor_target +Reading /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_erased.gds .. +Reading /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper_empty_erased.gds .. +--- Running XOR for 69/20 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 530 (flat) 530 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 530 (flat) 530 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +--- Running XOR for 70/20 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 107 (flat) 107 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 107 (flat) 107 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +--- Running XOR for 71/20 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 16 (flat) 16 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 16 (flat) 16 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +--- Running XOR for 71/44 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 128 (flat) 128 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 128 (flat) 128 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 570.00M +--- Running XOR for 72/20 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 16 (flat) 16 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 16 (flat) 16 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +--- Running XOR for 81/14 --- +"input" in: xor.rb.drc:39 + Polygons (raw): 1 (flat) 1 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +"input" in: xor.rb.drc:39 + Polygons (raw): 1 (flat) 1 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +"^" in: xor.rb.drc:39 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +XOR differences: 0 +"output" in: xor.rb.drc:43 + Polygons (raw): 0 (flat) 0 (hierarchical) + Elapsed: 0.000s Memory: 571.00M +Writing layout file: /tmp/tmp5bbb3lz4/repo/precheck_results/12_MAY_2026___07_45_39/outputs/user_project_wrapper.xor.gds .. +Total elapsed: 0.090s Memory: 571.00M diff --git a/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.total b/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.total new file mode 100644 index 00000000..c2270834 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/logs/xor_check.total @@ -0,0 +1 @@ +0 \ No newline at end of file diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.error.gz b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.error.gz new file mode 100644 index 0000000000000000000000000000000000000000..f2a2d1224666ca0eecc8d6e58af1e45b2c5f0016 GIT binary patch literal 319 zcmV-F0l@wriwFP!000001GSUSPQx$^hwpm|?*%%+kt+i(Lz+P1o;Ge0EvqX#ZQ<=% z*@jS;^v{7?BY*yWiE6Lmy>p?kAeK1DYPE)ES2?k$`|mdtCxIBAn2B%7d+LxkFHB9P zp;o~{u&0BuP&R@?I?FO>$p>W+lxI}>3k1Uud$d>_TxFmn?i6dtof6QFGy?uy;{ld% zQFnDD0ilKq+-O#=f>zFgXv91`on%zNzU8bK$ru5n_IlYn=Hcn2Iq#SP|JrwCTydE_ zxErnBCvUdfZZ84-D8TVF0RA@We`ob0H$W}&wFiIqWd@Qk%Cs?s#Ep8|m_*`6Gi^*F zQR8d>^J1Q1A-!ugiMZS&cvOdxRZDZ}`JdsQ;G*unrSzmie{faZglo?NENaHj8jFA$ RTICxYg5UQ`yMX=$003V+n92YE literal 0 HcmV?d00001 diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.oeb.report b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.oeb.report new file mode 100644 index 00000000..8b6566bb --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/cvc.oeb.report @@ -0,0 +1,84 @@ + gpio/user/analog | in | out | analog | oeb min/sim/max | configuration + 0 / 0 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 1 / 1 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 2 / 2 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 3 / 3 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_PULLUP 2 warnings/errors + 4 / 4 / | | 2 | | vssd*/ /vccd* | FIXED_STD_INPUT_NOPULL 2 warnings/errors + 5 / 5 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 6 / 6 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 7 / 7 / 0 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 8 / 8 / 1 | | | | / / | INVALID missing mode 1 warnings/errors + 9 / 9 / 2 | | | | / / | INVALID missing mode 1 warnings/errors + 10 / 10 / 3 | | | | / / | INVALID missing mode 1 warnings/errors + 11 / 11 / 4 | | | | / / | INVALID missing mode 1 warnings/errors + 12 / 12 / 5 | | | | / / | INVALID missing mode 1 warnings/errors + 13 / 13 / 6 | | | | / / | INVALID missing mode 1 warnings/errors + 14 / 14 / 7 | | | | / / | INVALID missing mode 1 warnings/errors + 15 / 15 / 8 | | | | / / | INVALID missing mode 1 warnings/errors + 16 / 16 / 9 | | | | / / | INVALID missing mode 1 warnings/errors + 17 / 17 / 10 | | | | / / | INVALID missing mode 1 warnings/errors + 18 / 18 / 11 | | | | / / | INVALID missing mode 1 warnings/errors + 19 / 19 / 12 | | | | / / | INVALID missing mode 1 warnings/errors + 20 / 20 / 13 | | | | / / | INVALID missing mode 1 warnings/errors + 21 / 21 / 14 | | | | / / | INVALID missing mode 1 warnings/errors + 22 / 22 / 15 | | | | / / | INVALID missing mode 1 warnings/errors + 23 / 23 / 16 | | | | / / | INVALID missing mode 1 warnings/errors + 24 / 24 / 17 | | | | / / | INVALID missing mode 1 warnings/errors + 25 / 25 / 18 | | | | / / | INVALID missing mode 1 warnings/errors + 26 / 26 / 19 | | | | / / | INVALID missing mode 1 warnings/errors + 27 / 27 / 20 | | | | / / | INVALID missing mode 1 warnings/errors + 28 / 28 / 21 | | | | / / | INVALID missing mode 1 warnings/errors + 29 / 29 / 22 | | | | / / | INVALID missing mode 1 warnings/errors + 30 / 30 / 23 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 31 / 31 / 24 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 32 / 32 / 25 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 33 / 33 / 26 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 34 / 34 / 27 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 35 / 35 / 28 | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 36 / 36 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + 37 / 37 / | | 2 | | vssd*/ /vccd* | INVALID missing mode 1 warnings/errors + +*** Detected the following warnings and/or errors: *** +GPIO 0: Warning: user output connection to fixed input gpio - firmware override required +GPIO 0: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 1: Warning: user output connection to fixed input gpio - firmware override required +GPIO 1: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 2: Warning: user output connection to fixed input gpio - firmware override required +GPIO 2: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 3: Warning: user output connection to fixed input gpio - firmware override required +GPIO 3: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 4: Warning: user output connection to fixed input gpio - firmware override required +GPIO 4: Warning: user oeb connection to fixed input gpio - firmware override required +GPIO 5: ERROR: missing gpio configuration +GPIO 6: ERROR: missing gpio configuration +GPIO 7: ERROR: missing gpio configuration +GPIO 8: ERROR: missing gpio configuration +GPIO 9: ERROR: missing gpio configuration +GPIO 10: ERROR: missing gpio configuration +GPIO 11: ERROR: missing gpio configuration +GPIO 12: ERROR: missing gpio configuration +GPIO 13: ERROR: missing gpio configuration +GPIO 14: ERROR: missing gpio configuration +GPIO 15: ERROR: missing gpio configuration +GPIO 16: ERROR: missing gpio configuration +GPIO 17: ERROR: missing gpio configuration +GPIO 18: ERROR: missing gpio configuration +GPIO 19: ERROR: missing gpio configuration +GPIO 20: ERROR: missing gpio configuration +GPIO 21: ERROR: missing gpio configuration +GPIO 22: ERROR: missing gpio configuration +GPIO 23: ERROR: missing gpio configuration +GPIO 24: ERROR: missing gpio configuration +GPIO 25: ERROR: missing gpio configuration +GPIO 26: ERROR: missing gpio configuration +GPIO 27: ERROR: missing gpio configuration +GPIO 28: ERROR: missing gpio configuration +GPIO 29: ERROR: missing gpio configuration +GPIO 30: ERROR: missing gpio configuration +GPIO 31: ERROR: missing gpio configuration +GPIO 32: ERROR: missing gpio configuration +GPIO 33: ERROR: missing gpio configuration +GPIO 34: ERROR: missing gpio configuration +GPIO 35: ERROR: missing gpio configuration +GPIO 36: ERROR: missing gpio configuration +GPIO 37: ERROR: missing gpio configuration diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/hier.csv b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/hier.csv new file mode 100644 index 00000000..aac5e3e8 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/hier.csv @@ -0,0 +1 @@ +verilog,,layout diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml new file mode 100644 index 00000000..c3f8bb2e --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_beol_check.xml @@ -0,0 +1,574 @@ + + + SKY130 DRC runset + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc' + user_project_wrapper + + + + + li.1 + li.1 : min. li width outside or crossing areaid:ce : 0.17um + + + + + li.3 + li.3 : min. li spacing outside or crossing areaid:ce : 0.17um + + + + + li.5 + li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um + + + + + li.6 + li.6 : min. li area : 0.0561um² + + + + + li.7 + li.7 : min. li core spacing : 0.14um + + + + + li.8 + li.8 : min. li core width : 0.14um + + + + + MR_li.WID.4 + MR_li.WID.4 : li:res minimum width : 0.29um + + + + + MR_mcon.ANG.1 + MR_mcon.ANG.1: mcon must be rectangular + + + + + MR_mcon.WID.1 + MR_mcon.WID.1 : minimum width of mcon : 0.17um + + + + + MR_mcon.LEN.1 + MR_mcon.LEN.1 : maximum length of mcon : 0.17um + + + + + MR_mcon.SP.1 + MR_mcon.SP.1 : min. mcon spacing : 0.19um + + + + + MR_mcon.WID.2 + MR_mcon.WID.2 : min. width of ring-shaped mcon : 0.17um + + + + + MR_mcon.WID.3 + MR_mcon.WID.3 : max. width of ring-shaped mcon : 0.175um + + + + + MR_mcon.CON.1 + MR_mcon.CON.1: ring-shaped mcon must be enclosed by areaid_sl + + + + + MR_mcon.CON.10 + MR_mcon.CON.10 : mcon should covered by li + + + + + MR_met1.WID.1 + MR_met1.WID.1 : min. m1 width : 0.14um + + + + + MR_met1.SP.1 + MR_met1.SP.1 : min. m1 spacing : 0.14um + + + + + MRW_met1.SP.2 + MRW_met1.SP.2 : min. 3um.m1 spacing m1 : 0.28um + + + + + MR_met1.ENC.1 + MR_met1.ENC.1 : min. m1 enclosure of mcon : 0.03um + + + + + MR_met1.CON.1 + MR_met1.CON.1 : mcon periphery must be enclosed by m1 + + + + + m1.4a + m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um + + + + + m1.4a_a + m1.4a_a : mcon periph must be enclosed by met1 for specific cells + + + + + MR_met1.AR.1 + MR_met1.AR.1 : min. m1 area : 0.083um² + + + + + MR_met1.AR.2 + MR_met1.AR.2 : min. m1 with holes area : 0.14um² + + + + + m1.5 + m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um + + + + + via.1a + via.1a : via outside of moduleCut should be rectangular + + + + + via.1a_a + via.1a_a : min. width of via outside of moduleCut : 0.15um + + + + + via.1a_b + via.1a_b : maximum length of via : 0.15um + + + + + via.2 + via.2 : min. via spacing : 0.17um + + + + + via.3 + via.3 : min. width of ring-shaped via : 0.2um + + + + + via.3_a + via.3_a : max. width of ring-shaped via : 0.205um + + + + + via.3_b + via.3_b: ring-shaped via must be enclosed by areaid_sl + + + + + MR_via1.ENC.1 + MR_via1.ENC.1 : min. m1 enclosure of 0.15um via : 0.055um + + + + + MR_via1.CON.1 + MR_via1.CON.1 : 0.15um via must be enclosed by met1 + + + + + via.5a + via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um + + + + + MR_met2.WID.1 + MR_met2.WID.1 : min. m2 width : 0.14um + + + + + m2.2 + m2.2 : min. m2 spacing : 0.14um + + + + + MRW_met2.SP.2 + MRW_met2.SP.2 : min. 3um.m2 spacing m2 : 0.28um + + + + + MR_met2.AR.1 + MR_met2.AR.1 : min. m2 area : 0.0676um² + + + + + MR_met2.AR.2 + MR_met2.AR.2 : min. m2 holes area : 0.14um² + + + + + m2.4 + m2.4 : min. m2 enclosure of via : 0.055um + + + + + m2.4_a + m2.4_a : via in periphery must be enclosed by met2 + + + + + m2.4_b + m2.4_B : min. m2 enclosure of via inside areaid:core : 0.045um + + + + + m2.5 + m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um + + + + + via2.1a + via2.1a : via2 outside of moduleCut should be rectangular + + + + + via2.1a_a + via2.1a_a : min. width of via2 outside of moduleCut : 0.2um + + + + + MR_via2.LEN.1 + MR_via2.LEN.1 : maximum length of via2 : 0.2um + + + + + via2.2 + via2.2 : min. via2 spacing : 0.2um + + + + + via2.3 + via2.3 : min. width of ring-shaped via2 : 0.2um + + + + + via2.3_a + via2.3_a : max. width of ring-shaped via2 : 0.205um + + + + + via2.3_b + via2.3_b: ring-shaped via2 must be enclosed by areaid_sl + + + + + via2.4 + via2.4 : min. m2 enclosure of via2 : 0.04um + + + + + MR_via2.CON.1 + MR_via2.CON.1 : via must be enclosed by met2 + + + + + via2.5 + via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um + + + + + MR_met3.WID.1 + MR_met3.WID.1 : min. m3 width : 0.3um + + + + + m3.2 + m3.2 : min. m3 spacing : 0.3um + + + + + MRW_met3.SP.2 + MRW_met3.SP.2 : min. 3um.m3 spacing m3 : 0.4um + + + + + m3.4 + m3.4 : min. m3 enclosure of via2 : 0.065um + + + + + MR_met3.CON.1 + MR_met3.CON.1 : via2 must be enclosed by met3 + + + + + MR_met3.AR.1 + MR_met3.AR.1 : min. m3 area : 0.240um² + + + + + MR_met3.AR.2 + MR_met3.AR.2 : min. m3 holes area : 0.2um² + + + + + via3.1 + via3.1 : via3 outside of moduleCut should be rectangular + + + + + via3.1_a + via3.1_a : min. width of via3 outside of moduleCut : 0.2um + + + + + MR_via3.LEN.1 + MR_via3.LEN.1 : maximum length of via3 : 0.2um + + + + + via3.2 + via3.2 : min. via3 spacing : 0.2um + + + + + via3.4 + via3.4 : min. m3 enclosure of via3 : 0.06um + + + + + via3.4_a + via3.4_a : non-ring via3 must be enclosed by met3 + + + + + via3.5 + via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um + + + + + MR_met4.WID.1 + MR_met4.WID.1 : min. m4 width : 0.3um + + + + + m4.2 + m4.2 : min. m4 spacing : 0.3um + + + + + MR_met4.AR.1 + MR_met4.AR.1 : min. m4 area : 0.240um² + + + + + MRW_met4.SP.2 + MRW_met4.SP.2 : min. 3um.m4 spacing m4 : 0.4um + + + + + m4.3 + m4.3 : min. m4 enclosure of via3 : 0.065um + + + + + MR_met4.CON.1 + MR_met4.CON.1 : via3 must be enclosed by met4 + + + + + MR_met4.AR.2 + MR_met4.AR.2 : min. m4 holes area : 0.2um² + + + + + via4.1 + via4.1 : via4 outside of moduleCut should be rectangular + + + + + via4.1_a + via4.1_a : min. width of via4 outside of moduleCut : 0.8um + + + + + via4.1_b + via4.1_b : maximum length of via4 : 0.8um + + + + + MR_via4.SP.1 + MR_via4.SP.1 : min. via4 spacing : 0.8um + + + + + via4.3 + via4.3 : min. width of ring-shaped via4 : 0.8um + + + + + via4.3_a + via4.3_a : max. width of ring-shaped via4 : 0.805um + + + + + via4.3_b + via4.3_b: ring-shaped via4 must be enclosed by areaid_sl + + + + + via4.4 + via4.4 : min. m4 enclosure of via4 : 0.19um + + + + + MR_via4.CON.1 + MR_via4.CON.1 : m4 must enclose all via4 + + + + + MR_met5.WID.1 + MR_met5.WID.1 : min. m5 width : 1.6um + + + + + MR_met5.SP.1 + MR_met5.SP.1 : min. m5 spacing : 1.6um + + + + + m5.3 + m5.3 : min. m5 enclosure of via4 : 0.31um + + + + + MR_met5.CON.1 + MR_met5.CON.1 : via must be enclosed by m5 + + + + + MR_met5.AR.1 + MR_met5.AR.1 : min. m5 area : 4.0um² + + + + + MR_met5.AR.2 + MR_met5.AR.2 : min. m5 holes area : 0.14um² + + + + + pad.2 + pad.2 : min. pad spacing : 1.27um + + + + + moduleCut.1 + moduleCut.1 : moduleCut layer is for SkyWater use only + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml new file mode 100644 index 00000000..96d2c09c --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_feol_check.xml @@ -0,0 +1,622 @@ + + + SKY130 DRC runset + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc' + user_project_wrapper + + + + + MRW_dnwell.WID.1 + MRW_dnwell.WID.1: min. dnwell width : 3.0um + + + + + MRW_dnwell.SP.1 + MRW_dnwell.SP.1 : min. dnwell spacing : 6.3um + + + + + MR_nwell.WID.1 + MR_nwell.WID.1 : min. nwell width : 0.84um + + + + + MR_nwell.SP.1 + MR_nwell.SP.1 : min. nwell spacing (merged if less) : 1.27um + + + + + MR_nwell.ENC.1 + MR_nwell.ENC.1 : min enclosure of nwellHole by dnwell : 1.03um + + + + + MR_nwell.CON.1 + MR_nwell.CON.1 : HVnwell must be enclosed by hv marker + + + + + MR_hvtp.WID.1 + MR_hvtp.WID.1 : min. hvtp width : 0.38um + + + + + MR_hvtp.SP.1 + MR_hvtp.SP.1 : min. hvtp spacing : 0.38um + + + + + pwde.1 + pwde.1 : min. pwde width : 0.84um + + + + + MR_pwde.SP.1 + MR_pwde.SP.1 : min. pwde inside v20 spacing : 1.27um + + + + + hvtr.1 + hvtr.1 : min. hvtr width : 0.38um + + + + + hvtr.2 + hvtr.2 : min. hvtr spacing : 0.38um + + + + + MR_hvtr.CON.1 + MR_hvtr.CON.1 : hvtr must not overlap hvtp + + + + + lvtn.1a + lvtn.1a : min. lvtn width : 0.38um + + + + + lvtn.2 + lvtn.2 : min. lvtn spacing : 0.38um + + + + + MR_lvtn.OVL.2 + MR_lvtn.OVL.2 : lvtn must not straddle nwell + + + + + MR_ncm.WID.1 + MR_ncm.WID.1 : min. ncm width : 0.38um + + + + + ncm.2a + ncm.2a : min. ncm spacing : 0.38um + + + + + difftap.1 + difftap.1 : min. diff width across areaid:ce : 0.15um + + + + + difftap.1_a + difftap.1_a : min. diff width in periphery : 0.15um + + + + + difftap.2 + difftap.2 : min. diff width inside areadid:ce : 0.14um + + + + + difftap.1_b + difftap.1_b : min. tap width across areaid:ce : 0.15um + + + + + MR_diff.WID.2 + MR_diff.WID.2 : min. tap width in periphery : 0.15um + + + + + difftap.3 + difftap.3 : min. difftap spacing : 0.27um + + + + + tunm.1 + tunm.1 : min. tunm width : 0.41um + + + + + tunm.2 + tunm.2 : min. tunm spacing : 0.5um + + + + + MR_tunm.CON.1 + MR_tunm.CON.1 : use of layer tunm is prohibited + + + + + thkox.1 + thkox.1 : min. thkox width inside periphery : 0.6um + + + + + thkox.2 + thkox.2 : min. thkox spacing inside periphery : 0.7um + + + + + MR_thkox.CON.1 + MR_thkox.CON.1 : thkox must not straddle diff + + + + + MR_hv.SP.10 + MR_hv.SP.10 : ndiff inside (v12, v20 and thkox) minimum spacing when non-abutting ptap : 1.07um + + + + + MR_poly.WID.2 + MR_poly.WID.2 : min. poly width : 0.15um + + + + + MR_poly.SP.1 + MR_poly.SP.1 : min. poly spacing : 0.21um + + + + + MR_poly.SP.4 + MR_poly.SP.4 : min. poly spacing inside areaid:core : 0.16um + + + + + MR_poly.LEN.2 + MR_poly.LEN.2 : poly:res minimum length for rpoly_hp and rpoly_hp2K resistors : 0.66um + + + + + MR_poly.WID.3 + MR_poly.WID.3 : poly:res minimum width : 0.33um + + + + + ldntm.1 + ldntm.1 : min. ldntm width inside areaid:core : 0.7um + + + + + ldntm.2 + ldntm.2 : min. ldntm spacing inside areaid:core : 0.7um + + + + + MR_rpm.WID.1 + MR_rpm.WID.1 : min. rpm width : 1.27um + + + + + MR_rpm.SP.1 + MR_rpm.SP.1 : min. rpm spacing : 0.84um + + + + + MR_rdl.WID.1 + MR_rdl.WID.1 : min. rdl width : 10um + + + + + MR_rdl.SP.1 + MR_rdl.SP.1 : min. rdl spacing : 10um + + + + + MR_rdl.CON.1 + MR_rdl.CON.1 : use of rdl layer is prohibited + + + + + MR_urpm.WID.1 + MR_urpm.WID.1 : min. rpm width : 1.27um + + + + + MR_urpm.SP.1 + MR_urpm.SP.1 : min. rpm spacing : 0.84um + + + + + MR_npc.WID.1 + MR_npc.WID.1 : min. npc width : 0.27um + + + + + npc.2 + npc.2 : min. npc spacing, should be manually merged if less than : 0.27um + + + + + MR_nsdm.SP.1 + MR_nsdm.SP.1 : min. nsdm spacing in periphery : 0.38um + + + + + MR_nsdm.WID.2 + MR_nsdm.WID.2 : min. nsdm width in periphery : 0.38um + + + + + MR_nsdm.WID.1 + MR_nsdm.WID.1 : min. diff width across areaid:ce : 0.38um + + + + + MR_nsdm.SP.2 + MR_nsdm.SP.2 : min. spacing across areaid:ce : 0.38um + + + + + MR_nsdm.WID.3 + MR_nsdm.WID.3 : min. nsdm width in areaid:ce : 0.29um + + + + + MR_nsdm.SP.3 + MR_nsdm.SP.3 : min. nsdm spacing in areaid:ce : 0.29um + + + + + nsdm.6a + nsdm.6a : min. nsdm spacing on parallel edges in areaid:ce : 0.38um + + + + + MR_psdm.SP.1 + MR_psdm.SP.1 : min. psdm spacing in periphery : 0.38um + + + + + MR_psdm.WID.2 + MR_psdm.WID.2 : min. psdm width in periphery : 0.38um + + + + + MR_psdm.WID.1 + MR_psdm.WID.1 : min. diff width across areaid:ce : 0.38um + + + + + MR_psdm.SP.2 + MR_psdm.SP.2 : min. spacing across areaid:ce : 0.38um + + + + + MR_psdm.WID.3 + MR_psdm.WID.3 : min. psdm width in areaid:ce : 0.29um + + + + + MR_psdm.SP.3 + MR_psdm.SP.3 : min. psdm spacing in areaid:ce : 0.29um + + + + + psdm.6a + psdm.6a : min. psdm spacing on parallel edges in areaid:ce : 0.38um + + + + + nsdm_psdm_overlap + nsdm_psdm_overlap : nsdm overlaps psdm over active + + + + + licon.1_c + licon.1_c : licon should be rectangle + + + + + MR_licon.SP.1 + MR_licon.SP.1: min. licon spacing in periphery : 0.17um + + + + + licon.1 + licon.1: min/max. licon length : 0.17um + + + + + licon.13 + licon.13: min. licon on diff spacing to npc in periphery : 0.09um + + + + + licon.13_a + licon.13_a: licon on diff in periphery can't overlap npc + + + + + licon.17 + licon.17 : Licons may not overlap both poly and (diff or tap) + + + + + licon.6 + licon.6 : npc min enclosure of poly_licon inside areaid:core : 0.045um + + + + + MR_licon.ANG.1 + MR_licon.ANG.1 : licon outside areaid:seal must be orthogonal + + + + + MR_licon.CON.13 + MR_licon.CON.13 : licon bar outside prec_resistor is prohibited + + + + + MR_licon.CON.xx + MR_licon.CON.xx : licon square interacting with rpm/urpm is prohibited + + + + + MR_licon.SP.2 + MR_licon.SP.2 : licon bar end to end minimum spacing : 0.35um + + + + + MR_licon.SP.3 + MR_licon.SP.3 : licon bar side to side minimum spacing : 0.51um + + + + + MR_licon.SP.4 + MR_licon.SP.4 : licon bar minimum space to licon square : 0.51um + + + + + MRW_licon.SP.15 + MRW_licon.SP.15 : 0.25 um width bar licons (post-maskgen) spacing < 0.58um + + + + + MRW_licon.SP.16 + MRW_licon.SP.16 : 0.19 um width bar licons (post-maskgen) side-to-side spacing < 0.51um + + + + + MR_licon.SP.5 + MR_licon.SP.5 : tap_licon minimum space to tap edge abutting diff : 0.06um + + + + + MR_licon.SP.6 + MR_licon.SP.6 : poly_licon minimum space to psdm (overlap prohibited) : 0.11um + + + + + MR_licon.SP.8 + MR_licon.SP.8 : licon on diff minimum space to gate outside areaid:standardc (overlap prohibited) : 0.055um + + + + + MR_licon.WID.1 + MR_licon.WID.1 : licon (non-bar) minimum/maximum width : 0.17um + + + + + MR_licon.WID.2 + MR_licon.WID.2 : licon bar exact length : 2.0um + + + + + MR_nsm.SP.1 + MR_nsm.SP.1 : nsm min. spacing : 4.0um + + + + + MR_nsm.WID.1 + MR_nsm.WID.1 : nsm min. width : 3.0um + + + + + MR_capm.WID.1 + MR_capm.WID.1 : min. capm width : 1.0um + + + + + MR_capm.SP.1 + MR_capm.SP.1 : min. capm spacing : 0.84um + + + + + MR_capm.SP.2 + MR_capm.SP.2 : Min spacing of capm and met3 not overlapping capm : 0.5um + + + + + MR_capm.ENC.1 + MR_capm.ENC.1 : min. m3 enclosure of capm : 0.14um + + + + + MR_capm.ENC.2 + MR_capm.ENC.2 : min. capm enclosure of via3 : 0.14um + + + + + MR_capm.SP.3 + MR_capm.SP.3 : min. capm spacing to via3 : 0.14um + + + + + MR_cap2m.WID.1 + MR_cap2m.WID.1 : min. cap2m width : 1.0um + + + + + MR_cap2m.SP.1 + MR_cap2m.SP.1 : min. cap2m spacing : 0.84um + + + + + MR_cap2m.SP.2 + MR_cap2m.SP.2 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um + + + + + MR_cap2m.ENC.1 + MR_cap2m.ENC.1 : min. m4 enclosure of cap2m : 0.14um + + + + + MR_cap2m.ENC.2 + MR_cap2m.ENC.2 : min. cap2m enclosure of via4 : 0.2um + + + + + MR_cap2m.SP.3 + MR_cap2m.SP.3 : min. cap2m spacing to via4 : 0.2um + + + + + hvi.1 + hvi.1 : min. hvi width : 0.6um + + + + + hvi.2a + hvi.2a : min. hvi spacing : 0.7um + + + + + hvntm.1 + hvntm.1 : min. hvntm width : 0.7um + + + + + hvntm.2 + hvntm.2 : min. hvntm spacing : 0.7um + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml new file mode 100644 index 00000000..ef1509be --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_met_min_ca_density_check.xml @@ -0,0 +1,22 @@ + + + Density Checks + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/met_min_ca_density.lydrc' + user_project_wrapper + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml new file mode 100644 index 00000000..8585537f --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_offgrid_check.xml @@ -0,0 +1,472 @@ + + + SKY130 DRC runset + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/sky130A_mr.drc' + user_project_wrapper + + + + + dnwell_OFFGRID + x.1b : OFFGRID vertex on dnwell + + + + + dnwell_angle + x.3a : non 45 degree angle dnwell + + + + + nwell_OFFGRID + x.1b : OFFGRID vertex on nwell + + + + + nwell_angle + x.3a : non 45 degree angle nwell + + + + + pwbm_OFFGRID + x.1b : OFFGRID vertex on pwbm + + + + + pwbm_angle + x.3a : non 45 degree angle pwbm + + + + + pwde_OFFGRID + x.1b : OFFGRID vertex on pwde + + + + + pwde_angle + x.3a : non 45 degree angle pwde + + + + + hvtp_OFFGRID + x.1b : OFFGRID vertex on hvtp + + + + + hvtp_angle + x.3a : non 45 degree angle hvtp + + + + + hvtr_OFFGRID + x.1b : OFFGRID vertex on hvtr + + + + + hvtr_angle + x.3a : non 45 degree angle hvtr + + + + + lvtn_OFFGRID + x.1b : OFFGRID vertex on lvtn + + + + + lvtn_angle + x.3a : non 45 degree angle lvtn + + + + + ncm_OFFGRID + x.1b : OFFGRID vertex on ncm + + + + + ncm_angle + x.3a : non 45 degree angle ncm + + + + + diff_OFFGRID + x.1b : OFFGRID vertex on diff + + + + + tap_OFFGRID + x.1b : OFFGRID vertex on tap + + + + + diff_angle + x.2c : non 45 degree angle diff + + + + + tap_angle + x.2c : non 45 degree angle tap + + + + + tunm_OFFGRID + x.1b : OFFGRID vertex on tunm + + + + + tunm_angle + x.3a : non 45 degree angle tunm + + + + + poly_OFFGRID + x.1b : OFFGRID vertex on poly + + + + + poly_angle + x.2 : non 90 degree angle poly + + + + + rpm_OFFGRID + x.1b : OFFGRID vertex on rpm + + + + + rpm_angle + x.3a : non 45 degree angle rpm + + + + + npc_OFFGRID + x.1b : OFFGRID vertex on npc + + + + + npc_angle + x.3a : non 45 degree angle npc + + + + + nsdm_OFFGRID + x.1b : OFFGRID vertex on nsdm + + + + + nsdm_angle + x.3a : non 45 degree angle nsdm + + + + + psdm_OFFGRID + x.1b : OFFGRID vertex on psdm + + + + + psdm_angle + x.3a : non 45 degree angle psdm + + + + + licon_OFFGRID + x.1b : OFFGRID vertex on licon + + + + + licon_angle + x.2 : non 90 degree angle licon + + + + + li_OFFGRID + x.1b : OFFGRID vertex on li + + + + + li_angle + x.3a : non 45 degree angle li + + + + + ct_OFFGRID + x.1b : OFFGRID vertex on mcon + + + + + ct_angle + x.2 : non 90 degree angle mcon + + + + + vpp_OFFGRID + x.1b : OFFGRID vertex on vpp + + + + + vpp_angle + x.3a : non 45 degree angle vpp + + + + + m1_OFFGRID + x.1b : OFFGRID vertex on m1 + + + + + m1_angle + x.3a : non 45 degree angle m1 + + + + + via_OFFGRID + x.1b : OFFGRID vertex on via + + + + + via_angle + x.2 : non 90 degree angle via + + + + + m2_OFFGRID + x.1b : OFFGRID vertex on m2 + + + + + m2_angle + x.3a : non 45 degree angle m2 + + + + + via2_OFFGRID + x.1b : OFFGRID vertex on via2 + + + + + via2_angle + x.2 : non 90 degree angle via2 + + + + + m3_OFFGRID + x.1b : OFFGRID vertex on m3 + + + + + m3_angle + x.3a : non 45 degree angle m3 + + + + + via3_OFFGRID + x.1b : OFFGRID vertex on via3 + + + + + via3_angle + x.2 : non 90 degree angle via3 + + + + + nsm_OFFGRID + x.1b : OFFGRID vertex on nsm + + + + + nsm_angle + x.3a : non 45 degree angle nsm + + + + + m4_OFFGRID + x.1b : OFFGRID vertex on m4 + + + + + m4_angle + x.3a : non 45 degree angle m4 + + + + + via4_OFFGRID + x.1b : OFFGRID vertex on via4 + + + + + via4_angle + x.2 : non 90 degree angle via4 + + + + + m5_OFFGRID + x.1b : OFFGRID vertex on m5 + + + + + m5_angle + x.3a : non 45 degree angle m5 + + + + + pad_OFFGRID + x.1b : OFFGRID vertex on pad + + + + + pad_angle + x.3a : non 45 degree angle pad + + + + + mf_OFFGRID + x.1b : OFFGRID vertex on mf + + + + + mf_angle + x.2 : non 90 degree angle mf + + + + + hvi_OFFGRID + x.1b : OFFGRID vertex on hvi + + + + + hvi_angle + x.3a : non 45 degree angle hvi + + + + + hvntm_OFFGRID + x.1b : OFFGRID vertex on hvntm + + + + + hvntm_angle + x.3a : non 45 degree angle hvntm + + + + + vhvi_OFFGRID + x.1b : OFFGRID vertex on vhvi + + + + + vhvi_angle + x.3a : non 45 degree angle vhvi + + + + + uhvi_OFFGRID + x.1b : OFFGRID vertex on uhvi + + + + + uhvi_angle + x.3a : non 45 degree angle uhvi + + + + + pwell_rs_OFFGRID + x.1b : OFFGRID vertex on pwell_rs + + + + + pwell_rs_angle + x.3a : non 45 degree angle pwell_rs + + + + + areaid_re_OFFGRID + x.1b : OFFGRID vertex on areaid.re + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml new file mode 100644 index 00000000..f44e7238 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml @@ -0,0 +1,22 @@ + + + pin_label_purposes_overlapping_drawing.rb.drc, input=/tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds, topcell=user_project_wrapper + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/pin_label_purposes_overlapping_drawing.rb.drc' + user_project_wrapper + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_zeroarea_check.xml new file mode 100644 index 00000000..7c81a104 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/klayout_zeroarea_check.xml @@ -0,0 +1,22 @@ + + + zero area check + + drc: script='/usr/local/lib/python3.9/site-packages/cf_precheck/drc_scripts/zeroarea.rb.drc' + user_project_wrapper + + + + + + + user_project_wrapper + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.report b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.report new file mode 100644 index 00000000..05a7b91c --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.report @@ -0,0 +1,4707 @@ + +Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent. + +Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent. + +Circuit 1 cell sky130_fd_pr__diode_pw2nd_05v5 and Circuit 2 cell sky130_fd_pr__diode_pw2nd_05v5 are black boxes. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__diode_pw2nd_05v5 |Circuit 2: sky130_fd_pr__diode_pw2nd_05v5 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__diode_pw2nd_05v5 and sky130_fd_pr__diode_pw2nd_05v5 are equivalent. + +Circuit 1 cell sky130_fd_pr__res_generic_po and Circuit 2 cell sky130_fd_pr__res_generic_po are black boxes. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__res_generic_po |Circuit 2: sky130_fd_pr__res_generic_po +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__res_generic_po and sky130_fd_pr__res_generic_po are equivalent. + +Circuit 1 cell sky130_fd_pr__special_nfet_01v8 and Circuit 2 cell sky130_fd_pr__special_nfet_01v8 are black boxes. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__special_nfet_01v8 |Circuit 2: sky130_fd_pr__special_nfet_01v8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__special_nfet_01v8 and sky130_fd_pr__special_nfet_01v8 are equivalent. + +Cell EZ_sky130_fd_sc_hd__fill_4 (0) disconnected node: VGND +Cell EZ_sky130_fd_sc_hd__fill_4 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__fill_4 (0) disconnected node: VPB +Cell EZ_sky130_fd_sc_hd__fill_4 (0) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_4 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__fill_4 (1) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_4 (1) disconnected node: VPB +Cell sky130_fd_sc_hd__fill_4 (1) disconnected node: VPWR + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__fill_4 |Circuit 2: sky130_fd_sc_hd__fill_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__fill_4 and sky130_fd_sc_hd__fill_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_ef_sc_hd__decap_40_12 |Circuit 2: sky130_ef_sc_hd__decap_40_12 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1) +sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1) +Number of devices: 2 |Number of devices: 2 +Number of nets: 4 |Number of nets: 4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_ef_sc_hd__decap_40_12 |Circuit 2: sky130_ef_sc_hd__decap_40_12 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_ef_sc_hd__decap_40_12 and sky130_ef_sc_hd__decap_40_12 are equivalent. + +Cell EZ_sky130_fd_sc_hd__fill_1 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__fill_1 (0) disconnected node: VGND +Cell EZ_sky130_fd_sc_hd__fill_1 (0) disconnected node: VPB +Cell EZ_sky130_fd_sc_hd__fill_1 (0) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_1 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__fill_1 (1) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_1 (1) disconnected node: VPB +Cell sky130_fd_sc_hd__fill_1 (1) disconnected node: VPWR + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__fill_1 |Circuit 2: sky130_fd_sc_hd__fill_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VGND |VGND +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__fill_1 and sky130_fd_sc_hd__fill_1 are equivalent. + +Cell EZ_sky130_fd_sc_hd__fill_2 (0) disconnected node: VGND +Cell EZ_sky130_fd_sc_hd__fill_2 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__fill_2 (0) disconnected node: VPB +Cell EZ_sky130_fd_sc_hd__fill_2 (0) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_2 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__fill_2 (1) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_2 (1) disconnected node: VPB +Cell sky130_fd_sc_hd__fill_2 (1) disconnected node: VPWR + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__fill_2 |Circuit 2: sky130_fd_sc_hd__fill_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__fill_2 and sky130_fd_sc_hd__fill_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1) +sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1) +Number of devices: 2 |Number of devices: 2 +Number of nets: 4 |Number of nets: 4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent. + +Cell EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 (0) disconnected node: VGND +Cell sky130_fd_sc_hd__tapvpwrvgnd_1 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__tapvpwrvgnd_1 (1) disconnected node: VPWR + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 |Circuit 2: sky130_fd_sc_hd__tapvpwrvgnd_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 and sky130_fd_sc_hd__tapvpwrvgnd_1 are equivalent. + +Cell EZ_sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND +Cell EZ_sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB +Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB +Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1) +Number of devices: 1 |Number of devices: 1 +Number of nets: 2 |Number of nets: 2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +DIODE |DIODE +VGND |VGND +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 14 |Number of nets: 14 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +A0 |A0 +A1 |A1 +X |X +VPWR |VPWR +S |S +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent. + +Cell EZ_sky130_fd_sc_hd__fill_8 (0) disconnected node: VGND +Cell EZ_sky130_fd_sc_hd__fill_8 (0) disconnected node: VPWR +Cell EZ_sky130_fd_sc_hd__fill_8 (0) disconnected node: VPB +Cell EZ_sky130_fd_sc_hd__fill_8 (0) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_8 (1) disconnected node: VGND +Cell sky130_fd_sc_hd__fill_8 (1) disconnected node: VNB +Cell sky130_fd_sc_hd__fill_8 (1) disconnected node: VPB +Cell sky130_fd_sc_hd__fill_8 (1) disconnected node: VPWR + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__fill_8 |Circuit 2: sky130_fd_sc_hd__fill_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__fill_8 and sky130_fd_sc_hd__fill_8 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A |A +X |X +VGND |VGND +VNB |VNB +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__dlygate4sd3_1 and sky130_fd_sc_hd__dlygate4sd3_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3) +sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 10 |Number of nets: 10 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A2 |A2 +B1 |B1 +VPWR |VPWR +A1 |A1 +VGND |VGND +Y |Y +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o21ai_1 and sky130_fd_sc_hd__o21ai_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2) +sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +A |A +VPB |VPB +VGND |VGND +VNB |VNB +B |B +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nor2_1 and sky130_fd_sc_hd__nor2_1 are equivalent. + +Cell EZ_sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB +Cell EZ_sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB +Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB +Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2) +Number of devices: 2 |Number of devices: 2 +Number of nets: 4 |Number of nets: 4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Resolving symmetries by property value. +Resolving symmetries by pin name. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +LO |LO +HI |HI +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent. + +Class sky130_fd_sc_hd__buf_12 (1): Merged 28 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2) +sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +VPWR |VPWR +VPB |VPB +VGND |VGND +VNB |VNB +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +A3 |A3 +B1 |B1 +VPWR |VPWR +A1 |A1 +A2 |A2 +Y |Y +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o31ai_1 and sky130_fd_sc_hd__o31ai_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (8) |sky130_fd_pr__nfet_01v8 (8) +sky130_fd_pr__special_nfet_01v8 (4) |sky130_fd_pr__special_nfet_01v8 (4) +sky130_fd_pr__pfet_01v8_hvt (12) |sky130_fd_pr__pfet_01v8_hvt (12) +Number of devices: 24 |Number of devices: 24 +Number of nets: 18 |Number of nets: 18 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +VGND |VGND +VPWR |VPWR +D |D +Q |Q +CLK |CLK +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3) +sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +X |X +A |A +B |B +VNB |VNB +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent. + +Class sky130_fd_sc_hd__buf_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2) +sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +VGND |VGND +VNB |VNB +VPWR |VPWR +VPB |VPB +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +B2 |B2 +X |X +B1 |B1 +A2 |A2 +A3 |A3 +A1 |A1 +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a32o_1 and sky130_fd_sc_hd__a32o_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +VPB |VPB +VNB |VNB +X |X +B1 |B1 +A1 |A1 +C1 |C1 +A2 |A2 +B2 |B2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a221o_1 and sky130_fd_sc_hd__a221o_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A |A +VGND |VGND +B |B +VNB |VNB +VPB |VPB +X |X +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__xor2_1 and sky130_fd_sc_hd__xor2_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_1 |Circuit 2: sky130_fd_sc_hd__buf_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2) +sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_1 |Circuit 2: sky130_fd_sc_hd__buf_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +X |X +VNB |VNB +A |A +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_1 and sky130_fd_sc_hd__buf_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPWR |VPWR +VPB |VPB +VGND |VGND +X |X +A_N |A_N +C |C +B |B +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and3b_1 and sky130_fd_sc_hd__and3b_1 are equivalent. + +Class sky130_fd_sc_hd__and3b_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5) +sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPWR |VPWR +VPB |VPB +VGND |VGND +X |X +C |C +B |B +A_N |A_N +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and3b_4 and sky130_fd_sc_hd__and3b_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +A |A +B |B +C |C +X |X +VNB |VNB +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and3_1 and sky130_fd_sc_hd__and3_1 are equivalent. + +Class sky130_fd_sc_hd__dfxtp_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (15->12) |sky130_fd_pr__pfet_01v8_hvt (15->12) +sky130_fd_pr__special_nfet_01v8 (4) |sky130_fd_pr__special_nfet_01v8 (4) +sky130_fd_pr__nfet_01v8 (11->8) |sky130_fd_pr__nfet_01v8 (11->8) +Number of devices: 24 |Number of devices: 24 +Number of nets: 18 |Number of nets: 18 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +VGND |VGND +VPWR |VPWR +Q |Q +D |D +CLK |CLK +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__dfxtp_4 and sky130_fd_sc_hd__dfxtp_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A1 |A1 +A2 |A2 +B1_N |B1_N +VNB |VNB +VPB |VPB +VGND |VGND +Y |Y +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a21boi_1 and sky130_fd_sc_hd__a21boi_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +B1 |B1 +X |X +A2 |A2 +A1 |A1 +A3 |A3 +VNB |VNB +VPB |VPB +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a31o_1 and sky130_fd_sc_hd__a31o_1 are equivalent. + +Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2) +sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +VGND |VGND +VNB |VNB +A |A +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3) +sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 10 |Number of nets: 10 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPB |VPB +Y |Y +A2 |A2 +VGND |VGND +A1 |A1 +VPWR |VPWR +B1 |B1 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a21oi_1 and sky130_fd_sc_hd__a21oi_1 are equivalent. + +Class sky130_fd_sc_hd__a31o_4 (1): Merged 11 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5) +sky130_fd_pr__nfet_01v8 (12->8) |sky130_fd_pr__nfet_01v8 (12->8) +Number of devices: 13 |Number of devices: 13 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Resolving symmetries by property value. +Resolving symmetries by pin name. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +A2 |A2 +A1 |A1 +A3 |A3 +VPB |VPB +B1 |B1 +X |X +VGND |VGND +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a31o_4 and sky130_fd_sc_hd__a31o_4 are equivalent. + +Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2) +sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +X |X +VPB |VPB +A |A +VGND |VGND +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent. + +Class sky130_fd_sc_hd__dfxtp_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (9->8) |sky130_fd_pr__nfet_01v8 (9->8) +sky130_fd_pr__pfet_01v8_hvt (13->12) |sky130_fd_pr__pfet_01v8_hvt (13->12) +sky130_fd_pr__special_nfet_01v8 (4) |sky130_fd_pr__special_nfet_01v8 (4) +Number of devices: 24 |Number of devices: 24 +Number of nets: 18 |Number of nets: 18 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +VGND |VGND +VPWR |VPWR +D |D +Q |Q +CLK |CLK +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__dfxtp_2 and sky130_fd_sc_hd__dfxtp_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +A2 |A2 +A1 |A1 +B1_N |B1_N +VPB |VPB +VNB |VNB +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a21bo_1 and sky130_fd_sc_hd__a21bo_1 are equivalent. + +Class sky130_fd_sc_hd__a41o_4 (1): Merged 16 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6) +sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPB |VPB +VNB |VNB +VPWR |VPWR +A3 |A3 +A2 |A2 +A1 |A1 +B1 |B1 +X |X +A4 |A4 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a41o_4 and sky130_fd_sc_hd__a41o_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 14 |Number of nets: 14 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPB |VPB +A1_N |A1_N +A2_N |A2_N +X |X +B1 |B1 +B2 |B2 +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o2bb2a_1 and sky130_fd_sc_hd__o2bb2a_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPB |VPB +A2 |A2 +X |X +A1 |A1 +B1 |B1 +C1 |C1 +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a211o_1 and sky130_fd_sc_hd__a211o_1 are equivalent. + +Class sky130_fd_sc_hd__or3b_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5) +sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VGND |VGND +VNB |VNB +VPB |VPB +X |X +B |B +C_N |C_N +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__or3b_4 and sky130_fd_sc_hd__or3b_4 are equivalent. + +Class sky130_fd_sc_hd__a41oi_4 (1): Merged 30 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5) +sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 14 |Number of nets: 14 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +VPB |VPB +VNB |VNB +A1 |A1 +VGND |VGND +B1 |B1 +A3 |A3 +A4 |A4 +A2 |A2 +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a41oi_4 and sky130_fd_sc_hd__a41oi_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +A2 |A2 +A1 |A1 +B1 |B1 +X |X +B2 |B2 +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a22o_1 and sky130_fd_sc_hd__a22o_1 are equivalent. + +Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3) +sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VPB |VPB +VNB |VNB +X |X +A |A +B |B +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent. + +Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2) +sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +X |X +VPB |VPB +VGND |VGND +VNB |VNB +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent. + +Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2) +sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A |A +VPWR |VPWR +VPB |VPB +VGND |VGND +VNB |VNB +X |X +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent. + +Class sky130_fd_sc_hd__or2_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3) +sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VGND |VGND +VNB |VNB +B |B +X |X +VPWR |VPWR +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__or2_2 and sky130_fd_sc_hd__or2_2 are equivalent. + +Class sky130_fd_sc_hd__nand4_2 (1): Merged 8 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4) +sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +Y |Y +B |B +C |C +A |A +D |D +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand4_2 and sky130_fd_sc_hd__nand4_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPWR |VPWR +VPB |VPB +VGND |VGND +X |X +D |D +B |B +C |C +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and4_1 and sky130_fd_sc_hd__and4_1 are equivalent. + +Class sky130_fd_sc_hd__inv_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1) +sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1) +Number of devices: 2 |Number of devices: 2 +Number of nets: 6 |Number of nets: 6 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPWR |VPWR +VPB |VPB +Y |Y +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3) +sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +VNB |VNB +VPWR |VPWR +VPB |VPB +A_N |A_N +VGND |VGND +B |B +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent. + +Class sky130_fd_sc_hd__or3_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__or3_4 |Circuit 2: sky130_fd_sc_hd__or3_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4) +sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__or3_4 |Circuit 2: sky130_fd_sc_hd__or3_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPB |VPB +X |X +VPWR |VPWR +B |B +A |A +C |C +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__or3_4 and sky130_fd_sc_hd__or3_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3) +sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A |A +VPWR |VPWR +X |X +B |B +VPB |VPB +VGND |VGND +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__or2_1 and sky130_fd_sc_hd__or2_1 are equivalent. + +Class sky130_fd_sc_hd__a21oi_4 (1): Merged 18 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3) +sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 10 |Number of nets: 10 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +A2 |A2 +VGND |VGND +B1 |B1 +VPWR |VPWR +A1 |A1 +VNB |VNB +Y |Y +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a21oi_4 and sky130_fd_sc_hd__a21oi_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2) +sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +Y |Y +A |A +VPWR |VPWR +VPB |VPB +B |B +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent. + +Class sky130_fd_sc_hd__a32o_4 (1): Merged 16 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6) +sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VPB |VPB +VNB |VNB +B2 |B2 +A1 |A1 +B1 |B1 +A3 |A3 +A2 |A2 +X |X +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a32o_4 and sky130_fd_sc_hd__a32o_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPB |VPB +VGND |VGND +VPWR |VPWR +A2 |A2 +X |X +B1 |B1 +A1 |A1 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a21o_1 and sky130_fd_sc_hd__a21o_1 are equivalent. + +Class sky130_fd_sc_hd__a31o_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5) +sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPB |VPB +A2 |A2 +A1 |A1 +B1 |B1 +A3 |A3 +X |X +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a31o_2 and sky130_fd_sc_hd__a31o_2 are equivalent. + +Class sky130_fd_sc_hd__and4_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5) +sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VPB |VPB +VNB |VNB +VGND |VGND +X |X +A |A +C |C +B |B +D |D +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +VGND |VGND +VPB |VPB +VNB |VNB +VPWR |VPWR +A |A +B |B +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__xnor2_1 and sky130_fd_sc_hd__xnor2_1 are equivalent. + +Class sky130_fd_sc_hd__nand2_2 (1): Merged 4 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2) +sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +Y |Y +A |A +VNB |VNB +B |B +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand2_2 and sky130_fd_sc_hd__nand2_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2) +sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +A |A +VNB |VNB +X |X +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VPWR |VPWR +X |X +A1 |A1 +B1 |B1 +A2 |A2 +B2 |B2 +A3 |A3 +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o32a_1 and sky130_fd_sc_hd__o32a_1 are equivalent. + +Class sky130_fd_sc_hd__buf_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2) +sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +VGND |VGND +VNB |VNB +A |A +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent. + +Class sky130_fd_sc_hd__and4_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5) +sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +X |X +C |C +D |D +B |B +A |A +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and4_4 and sky130_fd_sc_hd__and4_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +A1 |A1 +B1 |B1 +X |X +A2 |A2 +VPWR |VPWR +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o21a_1 and sky130_fd_sc_hd__o21a_1 are equivalent. + +Class sky130_fd_sc_hd__buf_8 (1): Merged 18 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (11->2) |sky130_fd_pr__nfet_01v8 (11->2) +sky130_fd_pr__pfet_01v8_hvt (11->2) |sky130_fd_pr__pfet_01v8_hvt (11->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +X |X +VGND |VGND +VNB |VNB +VPWR |VPWR +VPB |VPB +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent. + +Class sky130_fd_sc_hd__buf_6 (1): Merged 12 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2) +sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 7 |Number of nets: 7 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +X |X +VNB |VNB +A |A +VPWR |VPWR +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6) +sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6) +Number of devices: 12 |Number of devices: 12 +Number of nets: 15 |Number of nets: 15 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VGND |VGND +VNB |VNB +VPB |VPB +B1 |B1 +A4 |A4 +A3 |A3 +A2 |A2 +A1 |A1 +X |X +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a41o_1 and sky130_fd_sc_hd__a41o_1 are equivalent. + +Class sky130_fd_sc_hd__nand2_8 (1): Merged 28 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2) +sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +VGND |VGND +A |A +VPWR |VPWR +VPB |VPB +B |B +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent. + +Class sky130_fd_sc_hd__and2_4 (1): Merged 6 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3) +sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3) +Number of devices: 6 |Number of devices: 6 +Number of nets: 9 |Number of nets: 9 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +B |B +A |A +VGND |VGND +X |X +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent. + +Class sky130_fd_sc_hd__nand3b_4 (1): Merged 18 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4) +sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +VPWR |VPWR +Y |Y +VPB |VPB +B |B +C |C +VGND |VGND +A_N |A_N +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nand3b_4 and sky130_fd_sc_hd__nand3b_4 are equivalent. + +Class sky130_fd_sc_hd__nor2_2 (1): Merged 4 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2) +sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +B |B +VGND |VGND +VNB |VNB +A |A +VPB |VPB +Y |Y +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nor2_2 and sky130_fd_sc_hd__nor2_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 10 |Number of nets: 10 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +B |B +X |X +A_N |A_N +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and2b_1 and sky130_fd_sc_hd__and2b_1 are equivalent. + +Class sky130_fd_sc_hd__xnor2_2 (1): Merged 10 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5) +sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 11 |Number of nets: 11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +Y |Y +VPWR |VPWR +B |B +A |A +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__xnor2_2 and sky130_fd_sc_hd__xnor2_2 are equivalent. + +Class sky130_fd_sc_hd__nor2_8 (1): Merged 28 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2) +sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +A |A +VPB |VPB +VGND |VGND +VNB |VNB +B |B +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nor2_8 and sky130_fd_sc_hd__nor2_8 are equivalent. + +Class sky130_fd_sc_hd__o211ai_4 (1): Merged 20 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4) +sky130_fd_pr__nfet_01v8 (16->8) |sky130_fd_pr__nfet_01v8 (16->8) +Number of devices: 12 |Number of devices: 12 +Number of nets: 14 |Number of nets: 14 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Resolving symmetries by property value. +Resolving symmetries by pin name. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VNB |VNB +Y |Y +B1 |B1 +C1 |C1 +VPB |VPB +A1 |A1 +VGND |VGND +A2 |A2 +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o211ai_4 and sky130_fd_sc_hd__o211ai_4 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VPB |VPB +VNB |VNB +C1 |C1 +A1 |A1 +B1 |B1 +A2 |A2 +X |X +VGND |VGND +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o211a_1 and sky130_fd_sc_hd__o211a_1 are equivalent. + +Class sky130_fd_sc_hd__or3b_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5) +sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +VNB |VNB +VPB |VPB +VPWR |VPWR +B |B +X |X +C_N |C_N +A |A +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__or3b_2 and sky130_fd_sc_hd__or3b_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5) +sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5) +Number of devices: 10 |Number of devices: 10 +Number of nets: 13 |Number of nets: 13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPWR |VPWR +VGND |VGND +A2 |A2 +A1 |A1 +X |X +B1 |B1 +A3 |A3 +VNB |VNB +VPB |VPB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__o31a_1 and sky130_fd_sc_hd__o31a_1 are equivalent. + +Class sky130_fd_sc_hd__nor2_4 (1): Merged 12 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2) +sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2) +Number of devices: 4 |Number of devices: 4 +Number of nets: 8 |Number of nets: 8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +Y |Y +B |B +VPB |VPB +A |A +VGND |VGND +VNB |VNB +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__nor2_4 and sky130_fd_sc_hd__nor2_4 are equivalent. + +Class sky130_fd_sc_hd__and2b_2 (1): Merged 2 parallel devices. +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4) +sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 10 |Number of nets: 10 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VGND |VGND +X |X +B |B +A_N |A_N +VPWR |VPWR +VPB |VPB +VNB |VNB +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__and2b_2 and sky130_fd_sc_hd__and2b_2 are equivalent. + +Subcircuit summary: +Circuit 1: EZ_sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4) +sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4) +Number of devices: 8 |Number of devices: 8 +Number of nets: 12 |Number of nets: 12 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: EZ_sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1 +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +VPB |VPB +VNB |VNB +B1 |B1 +A1 |A1 +VGND |VGND +A3 |A3 +A2 |A2 +Y |Y +VPWR |VPWR +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes EZ_sky130_fd_sc_hd__a31oi_1 and sky130_fd_sc_hd__a31oi_1 are equivalent. + +Cell user_proj_example (0) disconnected node: io_in[0] +Cell user_proj_example (0) disconnected node: io_in[10] +Cell user_proj_example (0) disconnected node: io_in[11] +Cell user_proj_example (0) disconnected node: io_in[12] +Cell user_proj_example (0) disconnected node: io_in[13] +Cell user_proj_example (0) disconnected node: io_in[14] +Cell user_proj_example (0) disconnected node: io_in[15] +Cell user_proj_example (0) disconnected node: io_in[1] +Cell user_proj_example (0) disconnected node: io_in[2] +Cell user_proj_example (0) disconnected node: io_in[3] +Cell user_proj_example (0) disconnected node: io_in[4] +Cell user_proj_example (0) disconnected node: io_in[5] +Cell user_proj_example (0) disconnected node: io_in[6] +Cell user_proj_example (0) disconnected node: io_in[7] +Cell user_proj_example (0) disconnected node: io_in[8] +Cell user_proj_example (0) disconnected node: io_in[9] +Cell user_proj_example (0) disconnected node: la_data_in[0] +Cell user_proj_example (0) disconnected node: la_data_in[100] +Cell user_proj_example (0) disconnected node: la_data_in[101] +Cell user_proj_example (0) disconnected node: la_data_in[102] +Cell user_proj_example (0) disconnected node: la_data_in[103] +Cell user_proj_example (0) disconnected node: la_data_in[104] +Cell user_proj_example (0) disconnected node: la_data_in[105] +Cell user_proj_example (0) disconnected node: la_data_in[106] +Cell user_proj_example (0) disconnected node: la_data_in[107] +Cell user_proj_example (0) disconnected node: la_data_in[108] +Cell user_proj_example (0) disconnected node: la_data_in[109] +Cell user_proj_example (0) disconnected node: la_data_in[10] +Cell user_proj_example (0) disconnected node: la_data_in[110] +Cell user_proj_example (0) disconnected node: la_data_in[111] +Cell user_proj_example (0) disconnected node: la_data_in[112] +Cell user_proj_example (0) disconnected node: la_data_in[113] +Cell user_proj_example (0) disconnected node: la_data_in[114] +Cell user_proj_example (0) disconnected node: la_data_in[115] +Cell user_proj_example (0) disconnected node: la_data_in[116] +Cell user_proj_example (0) disconnected node: la_data_in[117] +Cell user_proj_example (0) disconnected node: la_data_in[118] +Cell user_proj_example (0) disconnected node: la_data_in[119] +Cell user_proj_example (0) disconnected node: la_data_in[11] +Cell user_proj_example (0) disconnected node: la_data_in[120] +Cell user_proj_example (0) disconnected node: la_data_in[121] +Cell user_proj_example (0) disconnected node: la_data_in[122] +Cell user_proj_example (0) disconnected node: la_data_in[123] +Cell user_proj_example (0) disconnected node: la_data_in[124] +Cell user_proj_example (0) disconnected node: la_data_in[125] +Cell user_proj_example (0) disconnected node: la_data_in[126] +Cell user_proj_example (0) disconnected node: la_data_in[127] +Cell user_proj_example (0) disconnected node: la_data_in[12] +Cell user_proj_example (0) disconnected node: la_data_in[13] +Cell user_proj_example (0) disconnected node: la_data_in[14] +Cell user_proj_example (0) disconnected node: la_data_in[15] +Cell user_proj_example (0) disconnected node: la_data_in[16] +Cell user_proj_example (0) disconnected node: la_data_in[17] +Cell user_proj_example (0) disconnected node: la_data_in[18] +Cell user_proj_example (0) disconnected node: la_data_in[19] +Cell user_proj_example (0) disconnected node: la_data_in[1] +Cell user_proj_example (0) disconnected node: la_data_in[20] +Cell user_proj_example (0) disconnected node: la_data_in[21] +Cell user_proj_example (0) disconnected node: la_data_in[22] +Cell user_proj_example (0) disconnected node: la_data_in[23] +Cell user_proj_example (0) disconnected node: la_data_in[24] +Cell user_proj_example (0) disconnected node: la_data_in[25] +Cell user_proj_example (0) disconnected node: la_data_in[26] +Cell user_proj_example (0) disconnected node: la_data_in[27] +Cell user_proj_example (0) disconnected node: la_data_in[28] +Cell user_proj_example (0) disconnected node: la_data_in[29] +Cell user_proj_example (0) disconnected node: la_data_in[2] +Cell user_proj_example (0) disconnected node: la_data_in[30] +Cell user_proj_example (0) disconnected node: la_data_in[31] +Cell user_proj_example (0) disconnected node: la_data_in[32] +Cell user_proj_example (0) disconnected node: la_data_in[33] +Cell user_proj_example (0) disconnected node: la_data_in[34] +Cell user_proj_example (0) disconnected node: la_data_in[35] +Cell user_proj_example (0) disconnected node: la_data_in[36] +Cell user_proj_example (0) disconnected node: la_data_in[37] +Cell user_proj_example (0) disconnected node: la_data_in[38] +Cell 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user_proj_example (1) disconnected node: la_oenb[14] +Cell user_proj_example (1) disconnected node: la_oenb[13] +Cell user_proj_example (1) disconnected node: la_oenb[12] +Cell user_proj_example (1) disconnected node: la_oenb[11] +Cell user_proj_example (1) disconnected node: la_oenb[10] +Cell user_proj_example (1) disconnected node: la_oenb[9] +Cell user_proj_example (1) disconnected node: la_oenb[8] +Cell user_proj_example (1) disconnected node: la_oenb[7] +Cell user_proj_example (1) disconnected node: la_oenb[6] +Cell user_proj_example (1) disconnected node: la_oenb[5] +Cell user_proj_example (1) disconnected node: la_oenb[4] +Cell user_proj_example (1) disconnected node: la_oenb[3] +Cell user_proj_example (1) disconnected node: la_oenb[2] +Cell user_proj_example (1) disconnected node: la_oenb[1] +Cell user_proj_example (1) disconnected node: la_oenb[0] +Cell user_proj_example (1) disconnected node: wbs_adr_i[31] +Cell user_proj_example (1) disconnected node: wbs_adr_i[30] +Cell user_proj_example (1) disconnected node: wbs_adr_i[29] +Cell user_proj_example (1) disconnected node: wbs_adr_i[28] +Cell user_proj_example (1) disconnected node: wbs_adr_i[27] +Cell user_proj_example (1) disconnected node: wbs_adr_i[26] +Cell user_proj_example (1) disconnected node: wbs_adr_i[25] +Cell user_proj_example (1) disconnected node: wbs_adr_i[24] +Cell user_proj_example (1) disconnected node: wbs_adr_i[23] +Cell user_proj_example (1) disconnected node: wbs_adr_i[22] +Cell user_proj_example (1) disconnected node: wbs_adr_i[21] +Cell user_proj_example (1) disconnected node: wbs_adr_i[20] +Cell user_proj_example (1) disconnected node: wbs_adr_i[19] +Cell user_proj_example (1) disconnected node: wbs_adr_i[18] +Cell user_proj_example (1) disconnected node: wbs_adr_i[17] +Cell user_proj_example (1) disconnected node: wbs_adr_i[16] +Cell user_proj_example (1) disconnected node: wbs_adr_i[15] +Cell user_proj_example (1) disconnected node: wbs_adr_i[14] +Cell user_proj_example (1) disconnected node: wbs_adr_i[13] +Cell user_proj_example (1) disconnected node: wbs_adr_i[12] +Cell user_proj_example (1) disconnected node: wbs_adr_i[11] +Cell user_proj_example (1) disconnected node: wbs_adr_i[10] +Cell user_proj_example (1) disconnected node: wbs_adr_i[9] +Cell user_proj_example (1) disconnected node: wbs_adr_i[8] +Cell user_proj_example (1) disconnected node: wbs_adr_i[7] +Cell user_proj_example (1) disconnected node: wbs_adr_i[6] +Cell user_proj_example (1) disconnected node: wbs_adr_i[5] +Cell user_proj_example (1) disconnected node: wbs_adr_i[4] +Cell user_proj_example (1) disconnected node: wbs_adr_i[3] +Cell user_proj_example (1) disconnected node: wbs_adr_i[2] +Cell user_proj_example (1) disconnected node: wbs_adr_i[1] +Cell user_proj_example (1) disconnected node: wbs_adr_i[0] +Cell user_proj_example (1) disconnected node: wbs_dat_i[31] +Cell user_proj_example (1) disconnected node: wbs_dat_i[30] +Cell user_proj_example (1) disconnected node: wbs_dat_i[29] +Cell user_proj_example (1) disconnected node: wbs_dat_i[28] +Cell user_proj_example (1) disconnected node: wbs_dat_i[27] +Cell user_proj_example (1) disconnected node: wbs_dat_i[26] +Cell user_proj_example (1) disconnected node: wbs_dat_i[25] +Cell user_proj_example (1) disconnected node: wbs_dat_i[24] +Cell user_proj_example (1) disconnected node: wbs_dat_i[23] +Cell user_proj_example (1) disconnected node: wbs_dat_i[22] +Cell user_proj_example (1) disconnected node: wbs_dat_i[21] +Cell user_proj_example (1) disconnected node: wbs_dat_i[20] +Cell user_proj_example (1) disconnected node: wbs_dat_i[19] +Cell user_proj_example (1) disconnected node: wbs_dat_i[18] +Cell user_proj_example (1) disconnected node: wbs_dat_i[17] +Cell user_proj_example (1) disconnected node: wbs_dat_i[16] +Cell user_proj_example (1) disconnected node: wbs_sel_i[3] +Cell user_proj_example (1) disconnected node: wbs_sel_i[2] +Subcircuit summary: +Circuit 1: user_proj_example |Circuit 2: user_proj_example +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +EZ_sky130_fd_sc_hd__fill_4 (68575->1) |sky130_fd_sc_hd__fill_4 (68575->1) +EZ_sky130_ef_sc_hd__decap_40_12 (275484->1) |sky130_ef_sc_hd__decap_40_12 (275484->1) +EZ_sky130_fd_sc_hd__fill_1 (69626->1) |sky130_fd_sc_hd__fill_1 (69626->1) +EZ_sky130_fd_sc_hd__fill_2 (69894->1) |sky130_fd_sc_hd__fill_2 (69894->1) +EZ_sky130_fd_sc_hd__decap_3 (1278->1) |sky130_fd_sc_hd__decap_3 (1278->1) +EZ_sky130_fd_sc_hd__tapvpwrvgnd_1 (69228->1) |sky130_fd_sc_hd__tapvpwrvgnd_1 (69228->1) +EZ_sky130_fd_sc_hd__diode_2 (644->219) |sky130_fd_sc_hd__diode_2 (644->219) +EZ_sky130_fd_sc_hd__mux2_1 (17) |sky130_fd_sc_hd__mux2_1 (17) +EZ_sky130_fd_sc_hd__fill_8 (505->1) |sky130_fd_sc_hd__fill_8 (505->1) +EZ_sky130_fd_sc_hd__dlygate4sd3_1 (218) |sky130_fd_sc_hd__dlygate4sd3_1 (218) +EZ_sky130_fd_sc_hd__o21ai_1 (1) |sky130_fd_sc_hd__o21ai_1 (1) +EZ_sky130_fd_sc_hd__nor2_1 (5) |sky130_fd_sc_hd__nor2_1 (5) +EZ_sky130_fd_sc_hd__conb_1 (131) |sky130_fd_sc_hd__conb_1 (131) +EZ_sky130_fd_sc_hd__buf_12 (81) |sky130_fd_sc_hd__buf_12 (81) +EZ_sky130_fd_sc_hd__o31ai_1 (1) |sky130_fd_sc_hd__o31ai_1 (1) +EZ_sky130_fd_sc_hd__dfxtp_1 (13) |sky130_fd_sc_hd__dfxtp_1 (13) +EZ_sky130_fd_sc_hd__and2_1 (3) |sky130_fd_sc_hd__and2_1 (3) +EZ_sky130_fd_sc_hd__buf_4 (18) |sky130_fd_sc_hd__buf_4 (18) +EZ_sky130_fd_sc_hd__a32o_1 (3) |sky130_fd_sc_hd__a32o_1 (3) +EZ_sky130_fd_sc_hd__a221o_1 (1) |sky130_fd_sc_hd__a221o_1 (1) +EZ_sky130_fd_sc_hd__xor2_1 (3) |sky130_fd_sc_hd__xor2_1 (3) +EZ_sky130_fd_sc_hd__buf_1 (35) |sky130_fd_sc_hd__buf_1 (35) +EZ_sky130_fd_sc_hd__and3b_1 (1) |sky130_fd_sc_hd__and3b_1 (1) +EZ_sky130_fd_sc_hd__and3b_4 (2) |sky130_fd_sc_hd__and3b_4 (2) +EZ_sky130_fd_sc_hd__and3_1 (6) |sky130_fd_sc_hd__and3_1 (6) +EZ_sky130_fd_sc_hd__dfxtp_4 (15) |sky130_fd_sc_hd__dfxtp_4 (15) +EZ_sky130_fd_sc_hd__a21boi_1 (1) |sky130_fd_sc_hd__a21boi_1 (1) +EZ_sky130_fd_sc_hd__a31o_1 (5) |sky130_fd_sc_hd__a31o_1 (5) +EZ_sky130_fd_sc_hd__clkbuf_8 (9) |sky130_fd_sc_hd__clkbuf_8 (9) +EZ_sky130_fd_sc_hd__a21oi_1 (11) |sky130_fd_sc_hd__a21oi_1 (11) +EZ_sky130_fd_sc_hd__a31o_4 (1) |sky130_fd_sc_hd__a31o_4 (1) +EZ_sky130_fd_sc_hd__clkbuf_4 (17) |sky130_fd_sc_hd__clkbuf_4 (17) +EZ_sky130_fd_sc_hd__dfxtp_2 (5) |sky130_fd_sc_hd__dfxtp_2 (5) +EZ_sky130_fd_sc_hd__a21bo_1 (1) |sky130_fd_sc_hd__a21bo_1 (1) +EZ_sky130_fd_sc_hd__a41o_4 (1) |sky130_fd_sc_hd__a41o_4 (1) +EZ_sky130_fd_sc_hd__o2bb2a_1 (3) |sky130_fd_sc_hd__o2bb2a_1 (3) +EZ_sky130_fd_sc_hd__a211o_1 (8) |sky130_fd_sc_hd__a211o_1 (8) +EZ_sky130_fd_sc_hd__or3b_4 (7) |sky130_fd_sc_hd__or3b_4 (7) +EZ_sky130_fd_sc_hd__a41oi_4 (1) |sky130_fd_sc_hd__a41oi_4 (1) +EZ_sky130_fd_sc_hd__a22o_1 (7) |sky130_fd_sc_hd__a22o_1 (7) +EZ_sky130_fd_sc_hd__and2_2 (2) |sky130_fd_sc_hd__and2_2 (2) +EZ_sky130_fd_sc_hd__clkbuf_16 (5) |sky130_fd_sc_hd__clkbuf_16 (5) +EZ_sky130_fd_sc_hd__clkbuf_2 (1) |sky130_fd_sc_hd__clkbuf_2 (1) +EZ_sky130_fd_sc_hd__or2_2 (1) |sky130_fd_sc_hd__or2_2 (1) +EZ_sky130_fd_sc_hd__nand4_2 (1) |sky130_fd_sc_hd__nand4_2 (1) +EZ_sky130_fd_sc_hd__and4_1 (3) |sky130_fd_sc_hd__and4_1 (3) +EZ_sky130_fd_sc_hd__inv_2 (7) |sky130_fd_sc_hd__inv_2 (7) +EZ_sky130_fd_sc_hd__nand2b_1 (3) |sky130_fd_sc_hd__nand2b_1 (3) +EZ_sky130_fd_sc_hd__or3_4 (1) |sky130_fd_sc_hd__or3_4 (1) +EZ_sky130_fd_sc_hd__or2_1 (2) |sky130_fd_sc_hd__or2_1 (2) +EZ_sky130_fd_sc_hd__a21oi_4 (2) |sky130_fd_sc_hd__a21oi_4 (2) +EZ_sky130_fd_sc_hd__nand2_1 (5) |sky130_fd_sc_hd__nand2_1 (5) +EZ_sky130_fd_sc_hd__a32o_4 (1) |sky130_fd_sc_hd__a32o_4 (1) +EZ_sky130_fd_sc_hd__a21o_1 (2) |sky130_fd_sc_hd__a21o_1 (2) +EZ_sky130_fd_sc_hd__a31o_2 (1) |sky130_fd_sc_hd__a31o_2 (1) +EZ_sky130_fd_sc_hd__and4_2 (3) |sky130_fd_sc_hd__and4_2 (3) +EZ_sky130_fd_sc_hd__xnor2_1 (3) |sky130_fd_sc_hd__xnor2_1 (3) +EZ_sky130_fd_sc_hd__nand2_2 (1) |sky130_fd_sc_hd__nand2_2 (1) +EZ_sky130_fd_sc_hd__clkbuf_1 (14) |sky130_fd_sc_hd__clkbuf_1 (14) +EZ_sky130_fd_sc_hd__o32a_1 (1) |sky130_fd_sc_hd__o32a_1 (1) +EZ_sky130_fd_sc_hd__buf_2 (2) |sky130_fd_sc_hd__buf_2 (2) +EZ_sky130_fd_sc_hd__and4_4 (1) |sky130_fd_sc_hd__and4_4 (1) +EZ_sky130_fd_sc_hd__o21a_1 (2) |sky130_fd_sc_hd__o21a_1 (2) +EZ_sky130_fd_sc_hd__buf_8 (2) |sky130_fd_sc_hd__buf_8 (2) +EZ_sky130_fd_sc_hd__buf_6 (3) |sky130_fd_sc_hd__buf_6 (3) +EZ_sky130_fd_sc_hd__a41o_1 (1) |sky130_fd_sc_hd__a41o_1 (1) +EZ_sky130_fd_sc_hd__nand2_8 (2) |sky130_fd_sc_hd__nand2_8 (2) +EZ_sky130_fd_sc_hd__and2_4 (2) |sky130_fd_sc_hd__and2_4 (2) +EZ_sky130_fd_sc_hd__nand3b_4 (1) |sky130_fd_sc_hd__nand3b_4 (1) +EZ_sky130_fd_sc_hd__nor2_2 (1) |sky130_fd_sc_hd__nor2_2 (1) +EZ_sky130_fd_sc_hd__and2b_1 (2) |sky130_fd_sc_hd__and2b_1 (2) +EZ_sky130_fd_sc_hd__xnor2_2 (1) |sky130_fd_sc_hd__xnor2_2 (1) +EZ_sky130_fd_sc_hd__nor2_8 (1) |sky130_fd_sc_hd__nor2_8 (1) +EZ_sky130_fd_sc_hd__o211ai_4 (1) |sky130_fd_sc_hd__o211ai_4 (1) +EZ_sky130_fd_sc_hd__o211a_1 (1) |sky130_fd_sc_hd__o211a_1 (1) +EZ_sky130_fd_sc_hd__or3b_2 (1) |sky130_fd_sc_hd__or3b_2 (1) +EZ_sky130_fd_sc_hd__o31a_1 (1) |sky130_fd_sc_hd__o31a_1 (1) +EZ_sky130_fd_sc_hd__nor2_4 (1) |sky130_fd_sc_hd__nor2_4 (1) +EZ_sky130_fd_sc_hd__and2b_2 (1) |sky130_fd_sc_hd__and2b_2 (1) +EZ_sky130_fd_sc_hd__a31oi_1 (1) |sky130_fd_sc_hd__a31oi_1 (1) +Number of devices: 944 |Number of devices: 944 +Number of nets: 910 |Number of nets: 910 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Resolving symmetries by property value. +Resolving symmetries by pin name. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: user_proj_example |Circuit 2: user_proj_example +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +io_out[14] |io_out[14] +io_out[12] |io_out[12] +io_out[15] |io_out[15] +io_out[13] |io_out[13] +io_out[11] |io_out[11] +io_oeb[8] |io_oeb[8] +la_data_out[7] |la_data_out[7] +io_oeb[0] |io_oeb[0] +io_oeb[1] |io_oeb[1] +io_oeb[2] |io_oeb[2] +io_oeb[3] |io_oeb[3] +io_oeb[4] |io_oeb[4] +io_oeb[5] |io_oeb[5] +io_oeb[6] |io_oeb[6] +la_data_out[0] |la_data_out[0] +la_data_out[10] |la_data_out[10] +la_data_out[14] |la_data_out[14] +la_data_out[12] |la_data_out[12] +la_data_out[6] |la_data_out[6] +la_data_out[5] |la_data_out[5] +la_data_out[2] |la_data_out[2] +la_data_out[8] |la_data_out[8] +la_data_out[4] |la_data_out[4] +la_data_out[1] |la_data_out[1] +la_data_out[13] |la_data_out[13] +la_data_out[11] |la_data_out[11] +la_data_out[9] |la_data_out[9] +la_data_out[3] |la_data_out[3] +la_data_out[15] |la_data_out[15] +io_oeb[10] |io_oeb[10] +io_oeb[11] |io_oeb[11] +io_oeb[12] |io_oeb[12] +io_oeb[13] |io_oeb[13] +io_oeb[14] |io_oeb[14] +io_oeb[15] |io_oeb[15] +io_oeb[9] |io_oeb[9] +wbs_ack_o |wbs_ack_o +io_out[9] |io_out[9] +wbs_dat_o[0] |wbs_dat_o[0] +wbs_dat_o[1] |wbs_dat_o[1] +wbs_dat_o[2] |wbs_dat_o[2] +io_out[8] |io_out[8] +io_out[10] |io_out[10] +io_out[3] |io_out[3] +io_oeb[7] |io_oeb[7] +io_out[1] |io_out[1] +io_out[4] |io_out[4] +wbs_dat_o[15] |wbs_dat_o[15] +wbs_dat_o[4] |wbs_dat_o[4] +wbs_dat_o[5] |wbs_dat_o[5] +wbs_dat_o[14] |wbs_dat_o[14] +wbs_dat_o[9] |wbs_dat_o[9] +wbs_dat_o[8] |wbs_dat_o[8] +wbs_dat_o[7] |wbs_dat_o[7] +wbs_dat_o[10] |wbs_dat_o[10] +wbs_dat_o[3] |wbs_dat_o[3] +wbs_dat_o[13] |wbs_dat_o[13] +wbs_dat_o[11] |wbs_dat_o[11] +wbs_dat_o[12] |wbs_dat_o[12] +wbs_dat_o[6] |wbs_dat_o[6] +io_out[7] |io_out[7] +io_out[6] |io_out[6] +io_out[2] |io_out[2] +io_out[5] |io_out[5] +io_out[0] |io_out[0] +la_data_out[48] |la_data_out[48] +la_data_out[49] |la_data_out[49] +la_data_out[50] |la_data_out[50] +la_data_out[51] |la_data_out[51] +la_data_out[52] |la_data_out[52] +la_data_out[53] |la_data_out[53] +la_data_out[54] |la_data_out[54] +la_data_out[55] |la_data_out[55] +la_data_out[56] |la_data_out[56] +la_data_out[57] |la_data_out[57] +la_data_out[58] |la_data_out[58] +la_data_out[59] |la_data_out[59] +la_data_out[60] |la_data_out[60] +la_data_out[61] |la_data_out[61] +la_data_out[62] |la_data_out[62] +la_data_out[63] |la_data_out[63] +la_data_out[64] |la_data_out[64] +la_data_out[65] |la_data_out[65] +la_data_out[66] |la_data_out[66] +la_data_out[67] |la_data_out[67] +la_data_out[68] |la_data_out[68] +la_data_out[69] |la_data_out[69] +la_data_out[70] |la_data_out[70] +la_data_out[71] |la_data_out[71] +la_data_out[72] |la_data_out[72] +la_data_out[73] |la_data_out[73] +la_data_out[74] |la_data_out[74] +la_data_out[75] |la_data_out[75] +la_data_out[76] |la_data_out[76] +la_data_out[77] |la_data_out[77] +la_data_out[78] |la_data_out[78] +la_data_out[79] |la_data_out[79] +la_data_out[80] |la_data_out[80] +la_data_out[81] |la_data_out[81] +la_data_out[82] |la_data_out[82] +la_data_out[83] |la_data_out[83] +la_data_out[84] |la_data_out[84] +la_data_out[85] |la_data_out[85] +la_data_out[86] |la_data_out[86] +la_data_out[87] |la_data_out[87] +la_data_out[88] |la_data_out[88] +la_data_out[89] |la_data_out[89] +la_data_out[90] |la_data_out[90] +la_data_out[91] |la_data_out[91] +la_data_out[92] |la_data_out[92] +la_data_out[93] |la_data_out[93] +la_data_out[94] |la_data_out[94] +la_data_out[95] |la_data_out[95] +la_data_out[96] |la_data_out[96] +la_data_out[97] |la_data_out[97] +la_data_out[98] |la_data_out[98] +la_data_out[99] |la_data_out[99] +la_data_out[100] |la_data_out[100] +la_data_out[101] |la_data_out[101] +la_data_out[102] |la_data_out[102] +la_data_out[103] |la_data_out[103] +la_data_out[104] |la_data_out[104] +la_data_out[105] |la_data_out[105] +la_data_out[106] |la_data_out[106] +la_data_out[107] |la_data_out[107] +la_data_out[108] |la_data_out[108] +la_data_out[109] |la_data_out[109] +la_data_out[110] |la_data_out[110] +la_data_out[111] |la_data_out[111] +la_data_out[112] |la_data_out[112] +la_data_out[113] |la_data_out[113] +la_data_out[114] |la_data_out[114] +la_data_out[115] |la_data_out[115] +la_data_out[116] |la_data_out[116] +la_data_out[117] |la_data_out[117] +la_data_out[118] |la_data_out[118] +la_data_out[119] |la_data_out[119] +la_data_out[120] |la_data_out[120] +la_data_out[121] |la_data_out[121] +la_data_out[122] |la_data_out[122] +la_data_out[123] |la_data_out[123] +la_data_out[124] |la_data_out[124] +la_data_out[125] |la_data_out[125] +la_data_out[126] |la_data_out[126] +la_data_out[127] |la_data_out[127] +wbs_dat_o[16] |wbs_dat_o[16] +wbs_dat_o[17] |wbs_dat_o[17] +wbs_dat_o[18] |wbs_dat_o[18] +wbs_dat_o[19] |wbs_dat_o[19] +wbs_dat_o[20] |wbs_dat_o[20] +wbs_dat_o[21] |wbs_dat_o[21] +wbs_dat_o[22] |wbs_dat_o[22] +wbs_dat_o[23] |wbs_dat_o[23] +wbs_dat_o[24] |wbs_dat_o[24] +wbs_dat_o[25] |wbs_dat_o[25] +wbs_dat_o[26] |wbs_dat_o[26] +wbs_dat_o[27] |wbs_dat_o[27] +wbs_dat_o[28] |wbs_dat_o[28] +wbs_dat_o[29] |wbs_dat_o[29] +wbs_dat_o[30] |wbs_dat_o[30] +wbs_dat_o[31] |wbs_dat_o[31] +irq[0] |irq[0] +irq[1] |irq[1] +irq[2] |irq[2] +la_data_out[16] |la_data_out[16] +la_data_out[17] |la_data_out[17] +la_data_out[18] |la_data_out[18] +la_data_out[19] |la_data_out[19] +la_data_out[20] |la_data_out[20] +la_data_out[21] |la_data_out[21] +la_data_out[22] |la_data_out[22] +la_data_out[23] |la_data_out[23] +la_data_out[24] |la_data_out[24] +la_data_out[25] |la_data_out[25] +la_data_out[26] |la_data_out[26] +la_data_out[27] |la_data_out[27] +la_data_out[28] |la_data_out[28] +la_data_out[29] |la_data_out[29] +la_data_out[30] |la_data_out[30] +la_data_out[31] |la_data_out[31] +la_data_out[32] |la_data_out[32] +la_data_out[33] |la_data_out[33] +la_data_out[34] |la_data_out[34] +la_data_out[35] |la_data_out[35] +la_data_out[36] |la_data_out[36] +la_data_out[37] |la_data_out[37] +la_data_out[38] |la_data_out[38] +la_data_out[39] |la_data_out[39] +la_data_out[40] |la_data_out[40] +la_data_out[41] |la_data_out[41] +la_data_out[42] |la_data_out[42] +la_data_out[43] |la_data_out[43] +la_data_out[44] |la_data_out[44] +la_data_out[45] |la_data_out[45] +la_data_out[46] |la_data_out[46] +la_data_out[47] |la_data_out[47] +la_data_in[50] |la_data_in[50] +la_data_in[51] |la_data_in[51] +la_data_in[61] |la_data_in[61] +la_data_in[62] |la_data_in[62] +la_oenb[49] |la_oenb[49] +la_oenb[57] |la_oenb[57] +la_oenb[54] |la_oenb[54] +la_oenb[59] |la_oenb[59] +la_oenb[63] |la_oenb[63] +wbs_dat_i[4] |wbs_dat_i[4] +wbs_dat_i[7] |wbs_dat_i[7] +wbs_dat_i[10] |wbs_dat_i[10] +la_data_in[48] |la_data_in[48] +wbs_dat_i[12] |wbs_dat_i[12] +wbs_sel_i[0] |wbs_sel_i[0] +wbs_sel_i[1] |wbs_sel_i[1] +wbs_cyc_i |wbs_cyc_i +wbs_stb_i |wbs_stb_i +wbs_we_i |wbs_we_i +wb_clk_i |wb_clk_i +la_data_in[64] |la_data_in[64] +wbs_dat_i[5] |wbs_dat_i[5] +la_oenb[64] |la_oenb[64] +wb_rst_i |wb_rst_i +la_oenb[56] |la_oenb[56] +wbs_dat_i[8] |wbs_dat_i[8] +la_oenb[62] |la_oenb[62] +la_oenb[65] |la_oenb[65] +la_data_in[65] |la_data_in[65] +la_oenb[58] |la_oenb[58] +la_oenb[52] |la_oenb[52] +la_oenb[60] |la_oenb[60] +la_data_in[63] |la_data_in[63] +la_data_in[58] |la_data_in[58] +la_oenb[55] |la_oenb[55] +la_oenb[48] |la_oenb[48] +la_oenb[53] |la_oenb[53] +la_data_in[56] |la_data_in[56] +la_data_in[55] |la_data_in[55] +la_data_in[53] |la_data_in[53] +wbs_dat_i[6] |wbs_dat_i[6] +wbs_dat_i[3] |wbs_dat_i[3] +la_oenb[50] |la_oenb[50] +la_oenb[61] |la_oenb[61] +la_oenb[51] |la_oenb[51] +la_data_in[54] |la_data_in[54] +la_data_in[59] |la_data_in[59] +la_data_in[60] |la_data_in[60] +la_data_in[52] |la_data_in[52] +la_data_in[57] |la_data_in[57] +la_data_in[49] |la_data_in[49] +wbs_dat_i[9] |wbs_dat_i[9] +wbs_dat_i[15] |wbs_dat_i[15] +wbs_dat_i[2] |wbs_dat_i[2] +wbs_dat_i[1] |wbs_dat_i[1] +wbs_dat_i[0] |wbs_dat_i[0] +wbs_dat_i[14] |wbs_dat_i[14] +wbs_dat_i[11] |wbs_dat_i[11] +wbs_dat_i[13] |wbs_dat_i[13] +vssd1 |vssd1 +vccd1 |vccd1 +io_in[0] |io_in[0] +io_in[10] |io_in[10] +io_in[11] |io_in[11] +io_in[12] |io_in[12] +io_in[13] |io_in[13] +io_in[14] |io_in[14] +io_in[15] |io_in[15] +io_in[1] |io_in[1] +io_in[2] |io_in[2] +io_in[3] |io_in[3] +io_in[4] |io_in[4] +io_in[5] |io_in[5] +io_in[6] |io_in[6] +io_in[7] |io_in[7] +io_in[8] |io_in[8] +io_in[9] |io_in[9] +la_data_in[0] |la_data_in[0] +la_data_in[100] |la_data_in[100] +la_data_in[101] |la_data_in[101] +la_data_in[102] |la_data_in[102] +la_data_in[103] |la_data_in[103] +la_data_in[104] |la_data_in[104] +la_data_in[105] |la_data_in[105] +la_data_in[106] |la_data_in[106] +la_data_in[107] |la_data_in[107] +la_data_in[108] |la_data_in[108] +la_data_in[109] |la_data_in[109] +la_data_in[10] |la_data_in[10] +la_data_in[110] |la_data_in[110] +la_data_in[111] |la_data_in[111] +la_data_in[112] |la_data_in[112] +la_data_in[113] |la_data_in[113] +la_data_in[114] |la_data_in[114] +la_data_in[115] |la_data_in[115] +la_data_in[116] |la_data_in[116] +la_data_in[117] |la_data_in[117] +la_data_in[118] |la_data_in[118] +la_data_in[119] |la_data_in[119] +la_data_in[11] |la_data_in[11] +la_data_in[120] |la_data_in[120] +la_data_in[121] |la_data_in[121] +la_data_in[122] |la_data_in[122] +la_data_in[123] |la_data_in[123] +la_data_in[124] |la_data_in[124] +la_data_in[125] |la_data_in[125] +la_data_in[126] |la_data_in[126] +la_data_in[127] |la_data_in[127] +la_data_in[12] |la_data_in[12] +la_data_in[13] |la_data_in[13] +la_data_in[14] |la_data_in[14] +la_data_in[15] |la_data_in[15] +la_data_in[16] |la_data_in[16] +la_data_in[17] |la_data_in[17] +la_data_in[18] |la_data_in[18] +la_data_in[19] |la_data_in[19] +la_data_in[1] |la_data_in[1] +la_data_in[20] |la_data_in[20] +la_data_in[21] |la_data_in[21] +la_data_in[22] |la_data_in[22] +la_data_in[23] |la_data_in[23] +la_data_in[24] |la_data_in[24] +la_data_in[25] |la_data_in[25] +la_data_in[26] |la_data_in[26] +la_data_in[27] |la_data_in[27] +la_data_in[28] |la_data_in[28] +la_data_in[29] |la_data_in[29] +la_data_in[2] |la_data_in[2] +la_data_in[30] |la_data_in[30] +la_data_in[31] |la_data_in[31] +la_data_in[32] |la_data_in[32] +la_data_in[33] |la_data_in[33] +la_data_in[34] |la_data_in[34] +la_data_in[35] |la_data_in[35] +la_data_in[36] |la_data_in[36] +la_data_in[37] |la_data_in[37] +la_data_in[38] |la_data_in[38] +la_data_in[39] |la_data_in[39] +la_data_in[3] |la_data_in[3] +la_data_in[40] |la_data_in[40] +la_data_in[41] |la_data_in[41] +la_data_in[42] |la_data_in[42] +la_data_in[43] |la_data_in[43] +la_data_in[44] |la_data_in[44] +la_data_in[45] |la_data_in[45] +la_data_in[46] |la_data_in[46] +la_data_in[47] |la_data_in[47] +la_data_in[4] |la_data_in[4] +la_data_in[5] |la_data_in[5] +la_data_in[66] |la_data_in[66] +la_data_in[67] |la_data_in[67] +la_data_in[68] |la_data_in[68] +la_data_in[69] |la_data_in[69] +la_data_in[6] |la_data_in[6] +la_data_in[70] |la_data_in[70] +la_data_in[71] |la_data_in[71] +la_data_in[72] |la_data_in[72] +la_data_in[73] |la_data_in[73] +la_data_in[74] |la_data_in[74] +la_data_in[75] |la_data_in[75] +la_data_in[76] |la_data_in[76] +la_data_in[77] |la_data_in[77] +la_data_in[78] |la_data_in[78] +la_data_in[79] |la_data_in[79] +la_data_in[7] |la_data_in[7] +la_data_in[80] |la_data_in[80] +la_data_in[81] |la_data_in[81] +la_data_in[82] |la_data_in[82] +la_data_in[83] |la_data_in[83] +la_data_in[84] |la_data_in[84] +la_data_in[85] |la_data_in[85] +la_data_in[86] |la_data_in[86] +la_data_in[87] |la_data_in[87] +la_data_in[88] |la_data_in[88] +la_data_in[89] |la_data_in[89] +la_data_in[8] |la_data_in[8] +la_data_in[90] |la_data_in[90] +la_data_in[91] |la_data_in[91] +la_data_in[92] |la_data_in[92] +la_data_in[93] |la_data_in[93] +la_data_in[94] |la_data_in[94] +la_data_in[95] |la_data_in[95] +la_data_in[96] |la_data_in[96] +la_data_in[97] |la_data_in[97] +la_data_in[98] |la_data_in[98] +la_data_in[99] |la_data_in[99] +la_data_in[9] |la_data_in[9] +la_oenb[0] |la_oenb[0] +la_oenb[100] |la_oenb[100] +la_oenb[101] |la_oenb[101] +la_oenb[102] |la_oenb[102] +la_oenb[103] |la_oenb[103] +la_oenb[104] |la_oenb[104] +la_oenb[105] |la_oenb[105] +la_oenb[106] |la_oenb[106] +la_oenb[107] |la_oenb[107] +la_oenb[108] |la_oenb[108] +la_oenb[109] |la_oenb[109] +la_oenb[10] |la_oenb[10] +la_oenb[110] |la_oenb[110] +la_oenb[111] |la_oenb[111] +la_oenb[112] |la_oenb[112] +la_oenb[113] |la_oenb[113] +la_oenb[114] |la_oenb[114] +la_oenb[115] |la_oenb[115] +la_oenb[116] |la_oenb[116] +la_oenb[117] |la_oenb[117] +la_oenb[118] |la_oenb[118] +la_oenb[119] |la_oenb[119] +la_oenb[11] |la_oenb[11] +la_oenb[120] |la_oenb[120] +la_oenb[121] |la_oenb[121] +la_oenb[122] |la_oenb[122] +la_oenb[123] |la_oenb[123] +la_oenb[124] |la_oenb[124] +la_oenb[125] |la_oenb[125] +la_oenb[126] |la_oenb[126] +la_oenb[127] |la_oenb[127] +la_oenb[12] |la_oenb[12] +la_oenb[13] |la_oenb[13] +la_oenb[14] |la_oenb[14] +la_oenb[15] |la_oenb[15] +la_oenb[16] |la_oenb[16] +la_oenb[17] |la_oenb[17] +la_oenb[18] |la_oenb[18] +la_oenb[19] |la_oenb[19] +la_oenb[1] |la_oenb[1] +la_oenb[20] |la_oenb[20] +la_oenb[21] |la_oenb[21] +la_oenb[22] |la_oenb[22] +la_oenb[23] |la_oenb[23] +la_oenb[24] |la_oenb[24] +la_oenb[25] |la_oenb[25] +la_oenb[26] |la_oenb[26] +la_oenb[27] |la_oenb[27] +la_oenb[28] |la_oenb[28] +la_oenb[29] |la_oenb[29] +la_oenb[2] |la_oenb[2] +la_oenb[30] |la_oenb[30] +la_oenb[31] |la_oenb[31] +la_oenb[32] |la_oenb[32] +la_oenb[33] |la_oenb[33] +la_oenb[34] |la_oenb[34] +la_oenb[35] |la_oenb[35] +la_oenb[36] |la_oenb[36] +la_oenb[37] |la_oenb[37] +la_oenb[38] |la_oenb[38] +la_oenb[39] |la_oenb[39] +la_oenb[3] |la_oenb[3] +la_oenb[40] |la_oenb[40] +la_oenb[41] |la_oenb[41] +la_oenb[42] |la_oenb[42] +la_oenb[43] |la_oenb[43] +la_oenb[44] |la_oenb[44] +la_oenb[45] |la_oenb[45] +la_oenb[46] |la_oenb[46] +la_oenb[47] |la_oenb[47] +la_oenb[4] |la_oenb[4] +la_oenb[5] |la_oenb[5] +la_oenb[66] |la_oenb[66] +la_oenb[67] |la_oenb[67] +la_oenb[68] |la_oenb[68] +la_oenb[69] |la_oenb[69] +la_oenb[6] |la_oenb[6] +la_oenb[70] |la_oenb[70] +la_oenb[71] |la_oenb[71] +la_oenb[72] |la_oenb[72] +la_oenb[73] |la_oenb[73] +la_oenb[74] |la_oenb[74] +la_oenb[75] |la_oenb[75] +la_oenb[76] |la_oenb[76] +la_oenb[77] |la_oenb[77] +la_oenb[78] |la_oenb[78] +la_oenb[79] |la_oenb[79] +la_oenb[7] |la_oenb[7] +la_oenb[80] |la_oenb[80] +la_oenb[81] |la_oenb[81] +la_oenb[82] |la_oenb[82] +la_oenb[83] |la_oenb[83] +la_oenb[84] |la_oenb[84] +la_oenb[85] |la_oenb[85] +la_oenb[86] |la_oenb[86] +la_oenb[87] |la_oenb[87] +la_oenb[88] |la_oenb[88] +la_oenb[89] |la_oenb[89] +la_oenb[8] |la_oenb[8] +la_oenb[90] |la_oenb[90] +la_oenb[91] |la_oenb[91] +la_oenb[92] |la_oenb[92] +la_oenb[93] |la_oenb[93] +la_oenb[94] |la_oenb[94] +la_oenb[95] |la_oenb[95] +la_oenb[96] |la_oenb[96] +la_oenb[97] |la_oenb[97] +la_oenb[98] |la_oenb[98] +la_oenb[99] |la_oenb[99] +la_oenb[9] |la_oenb[9] +wbs_adr_i[0] |wbs_adr_i[0] +wbs_adr_i[10] |wbs_adr_i[10] +wbs_adr_i[11] |wbs_adr_i[11] +wbs_adr_i[12] |wbs_adr_i[12] +wbs_adr_i[13] |wbs_adr_i[13] +wbs_adr_i[14] |wbs_adr_i[14] +wbs_adr_i[15] |wbs_adr_i[15] +wbs_adr_i[16] |wbs_adr_i[16] +wbs_adr_i[17] |wbs_adr_i[17] +wbs_adr_i[18] |wbs_adr_i[18] +wbs_adr_i[19] |wbs_adr_i[19] +wbs_adr_i[1] |wbs_adr_i[1] +wbs_adr_i[20] |wbs_adr_i[20] +wbs_adr_i[21] |wbs_adr_i[21] +wbs_adr_i[22] |wbs_adr_i[22] +wbs_adr_i[23] |wbs_adr_i[23] +wbs_adr_i[24] |wbs_adr_i[24] +wbs_adr_i[25] |wbs_adr_i[25] +wbs_adr_i[26] |wbs_adr_i[26] +wbs_adr_i[27] |wbs_adr_i[27] +wbs_adr_i[28] |wbs_adr_i[28] +wbs_adr_i[29] |wbs_adr_i[29] +wbs_adr_i[2] |wbs_adr_i[2] +wbs_adr_i[30] |wbs_adr_i[30] +wbs_adr_i[31] |wbs_adr_i[31] +wbs_adr_i[3] |wbs_adr_i[3] +wbs_adr_i[4] |wbs_adr_i[4] +wbs_adr_i[5] |wbs_adr_i[5] +wbs_adr_i[6] |wbs_adr_i[6] +wbs_adr_i[7] |wbs_adr_i[7] +wbs_adr_i[8] |wbs_adr_i[8] +wbs_adr_i[9] |wbs_adr_i[9] +wbs_dat_i[16] |wbs_dat_i[16] +wbs_dat_i[17] |wbs_dat_i[17] +wbs_dat_i[18] |wbs_dat_i[18] +wbs_dat_i[19] |wbs_dat_i[19] +wbs_dat_i[20] |wbs_dat_i[20] +wbs_dat_i[21] |wbs_dat_i[21] +wbs_dat_i[22] |wbs_dat_i[22] +wbs_dat_i[23] |wbs_dat_i[23] +wbs_dat_i[24] |wbs_dat_i[24] +wbs_dat_i[25] |wbs_dat_i[25] +wbs_dat_i[26] |wbs_dat_i[26] +wbs_dat_i[27] |wbs_dat_i[27] +wbs_dat_i[28] |wbs_dat_i[28] +wbs_dat_i[29] |wbs_dat_i[29] +wbs_dat_i[30] |wbs_dat_i[30] +wbs_dat_i[31] |wbs_dat_i[31] +wbs_sel_i[2] |wbs_sel_i[2] +wbs_sel_i[3] |wbs_sel_i[3] +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes user_proj_example and user_proj_example are equivalent. + +Cell user_project_wrapper (0) disconnected node: analog_io[0] +Cell user_project_wrapper (0) disconnected node: analog_io[10] +Cell user_project_wrapper (0) disconnected node: analog_io[11] +Cell user_project_wrapper (0) disconnected node: analog_io[12] +Cell user_project_wrapper (0) disconnected node: analog_io[13] +Cell user_project_wrapper (0) disconnected node: analog_io[14] +Cell user_project_wrapper (0) disconnected node: analog_io[15] +Cell user_project_wrapper (0) disconnected node: analog_io[16] +Cell user_project_wrapper (0) disconnected node: analog_io[17] +Cell user_project_wrapper (0) disconnected node: analog_io[18] +Cell user_project_wrapper (0) disconnected node: analog_io[19] +Cell user_project_wrapper (0) disconnected node: analog_io[1] +Cell user_project_wrapper (0) disconnected node: analog_io[20] +Cell user_project_wrapper (0) disconnected node: analog_io[21] +Cell user_project_wrapper (0) disconnected node: analog_io[22] +Cell user_project_wrapper (0) disconnected node: analog_io[23] +Cell user_project_wrapper (0) disconnected node: analog_io[24] +Cell user_project_wrapper (0) disconnected node: analog_io[25] +Cell user_project_wrapper (0) disconnected node: analog_io[26] +Cell user_project_wrapper (0) disconnected node: analog_io[27] +Cell user_project_wrapper (0) disconnected node: analog_io[28] +Cell user_project_wrapper (0) disconnected node: analog_io[2] +Cell user_project_wrapper (0) disconnected node: analog_io[3] +Cell user_project_wrapper (0) disconnected node: analog_io[4] +Cell user_project_wrapper (0) disconnected node: analog_io[5] +Cell user_project_wrapper (0) disconnected node: analog_io[6] +Cell user_project_wrapper (0) disconnected node: analog_io[7] +Cell user_project_wrapper (0) disconnected node: analog_io[8] +Cell user_project_wrapper (0) disconnected node: analog_io[9] +Cell user_project_wrapper (0) disconnected node: io_in[10] +Cell user_project_wrapper (0) disconnected node: io_in[11] +Cell user_project_wrapper (0) disconnected node: io_in[12] +Cell user_project_wrapper (0) disconnected node: io_in[13] +Cell user_project_wrapper (0) disconnected node: io_in[14] +Cell user_project_wrapper (0) disconnected node: io_in[15] +Cell user_project_wrapper (0) disconnected node: io_in[16] +Cell user_project_wrapper (0) disconnected node: io_in[17] +Cell user_project_wrapper (0) disconnected node: io_in[18] +Cell user_project_wrapper (0) disconnected node: io_in[19] +Cell user_project_wrapper (0) disconnected node: io_in[20] +Cell user_project_wrapper (0) disconnected node: io_in[21] +Cell user_project_wrapper (0) disconnected node: io_in[22] +Cell user_project_wrapper (0) disconnected node: io_in[23] +Cell user_project_wrapper (0) disconnected node: io_in[24] +Cell user_project_wrapper (0) disconnected node: io_in[25] +Cell user_project_wrapper (0) disconnected node: io_in[26] +Cell user_project_wrapper (0) disconnected node: io_in[27] +Cell user_project_wrapper (0) disconnected node: io_in[28] +Cell user_project_wrapper (0) disconnected node: io_in[29] +Cell user_project_wrapper (0) disconnected node: io_in[8] +Cell user_project_wrapper (0) disconnected node: io_in[9] +Cell user_project_wrapper (0) disconnected node: io_oeb[10] +Cell user_project_wrapper (0) disconnected node: io_oeb[11] +Cell user_project_wrapper (0) disconnected node: io_oeb[12] +Cell user_project_wrapper (0) disconnected node: io_oeb[13] +Cell user_project_wrapper (0) disconnected node: io_oeb[14] +Cell user_project_wrapper (0) disconnected node: io_oeb[15] +Cell user_project_wrapper (0) disconnected node: io_oeb[16] +Cell user_project_wrapper (0) disconnected node: io_oeb[17] +Cell user_project_wrapper (0) disconnected node: io_oeb[18] +Cell user_project_wrapper (0) disconnected node: io_oeb[19] +Cell user_project_wrapper (0) disconnected node: io_oeb[20] +Cell user_project_wrapper (0) disconnected node: io_oeb[21] +Cell user_project_wrapper (0) disconnected node: io_oeb[22] +Cell user_project_wrapper (0) disconnected node: io_oeb[23] +Cell user_project_wrapper (0) disconnected node: io_oeb[24] +Cell user_project_wrapper (0) disconnected node: io_oeb[25] +Cell user_project_wrapper (0) disconnected node: io_oeb[26] +Cell user_project_wrapper (0) disconnected node: io_oeb[27] +Cell user_project_wrapper (0) disconnected node: io_oeb[28] +Cell user_project_wrapper (0) disconnected node: io_oeb[29] +Cell user_project_wrapper (0) disconnected node: io_oeb[8] +Cell user_project_wrapper (0) disconnected node: io_oeb[9] +Cell user_project_wrapper (0) disconnected node: io_out[10] +Cell user_project_wrapper (0) disconnected node: io_out[11] +Cell user_project_wrapper (0) disconnected node: io_out[12] +Cell user_project_wrapper (0) disconnected node: io_out[13] +Cell user_project_wrapper (0) disconnected node: io_out[14] +Cell user_project_wrapper (0) disconnected node: io_out[15] +Cell user_project_wrapper (0) disconnected node: io_out[16] +Cell user_project_wrapper (0) disconnected node: io_out[17] +Cell user_project_wrapper (0) disconnected node: io_out[18] +Cell user_project_wrapper (0) disconnected node: io_out[19] +Cell user_project_wrapper (0) disconnected node: io_out[20] +Cell user_project_wrapper (0) disconnected node: io_out[21] +Cell user_project_wrapper (0) disconnected node: io_out[22] +Cell user_project_wrapper (0) disconnected node: io_out[23] +Cell user_project_wrapper (0) disconnected node: io_out[24] +Cell user_project_wrapper (0) disconnected node: io_out[25] +Cell user_project_wrapper (0) disconnected node: io_out[26] +Cell user_project_wrapper (0) disconnected node: io_out[27] +Cell user_project_wrapper (0) disconnected node: io_out[28] +Cell user_project_wrapper (0) disconnected node: io_out[29] +Cell user_project_wrapper (0) disconnected node: io_out[8] +Cell user_project_wrapper (0) disconnected node: io_out[9] +Cell user_project_wrapper (0) disconnected node: user_clock2 +Cell user_project_wrapper (0) disconnected node: vccd1 +Cell user_project_wrapper (0) disconnected node: vdda1 +Cell user_project_wrapper (0) disconnected node: vdda2 +Cell user_project_wrapper (0) disconnected node: vssa1 +Cell user_project_wrapper (0) disconnected node: vssa2 +Cell user_project_wrapper (0) disconnected node: vssd1 +Cell user_project_wrapper (1) disconnected node: user_clock2 +Cell user_project_wrapper (1) disconnected node: vssa2 +Cell user_project_wrapper (1) disconnected node: vdda2 +Cell user_project_wrapper (1) disconnected node: vssa1 +Cell user_project_wrapper (1) disconnected node: vdda1 +Cell user_project_wrapper (1) disconnected node: vssd1 +Cell user_project_wrapper (1) disconnected node: vccd1 +Cell user_project_wrapper (1) disconnected node: analog_io[28] +Cell user_project_wrapper (1) disconnected node: analog_io[27] +Cell user_project_wrapper (1) disconnected node: analog_io[26] +Cell user_project_wrapper (1) disconnected node: analog_io[25] +Cell user_project_wrapper (1) disconnected node: analog_io[24] +Cell user_project_wrapper (1) disconnected node: analog_io[23] +Cell user_project_wrapper (1) disconnected node: analog_io[22] +Cell user_project_wrapper (1) disconnected node: analog_io[21] +Cell user_project_wrapper (1) disconnected node: analog_io[20] +Cell user_project_wrapper (1) disconnected node: analog_io[19] +Cell user_project_wrapper (1) disconnected node: analog_io[18] +Cell user_project_wrapper (1) disconnected node: analog_io[17] +Cell user_project_wrapper (1) disconnected node: analog_io[16] +Cell user_project_wrapper (1) disconnected node: analog_io[15] +Cell user_project_wrapper (1) disconnected node: analog_io[14] +Cell user_project_wrapper (1) disconnected node: analog_io[13] +Cell user_project_wrapper (1) disconnected node: analog_io[12] +Cell user_project_wrapper (1) disconnected node: analog_io[11] +Cell user_project_wrapper (1) disconnected node: analog_io[10] +Cell user_project_wrapper (1) disconnected node: analog_io[9] +Cell user_project_wrapper (1) disconnected node: analog_io[8] +Cell user_project_wrapper (1) disconnected node: analog_io[7] +Cell user_project_wrapper (1) disconnected node: analog_io[6] +Cell user_project_wrapper (1) disconnected node: analog_io[5] +Cell user_project_wrapper (1) disconnected node: analog_io[4] +Cell user_project_wrapper (1) disconnected node: analog_io[3] +Cell user_project_wrapper (1) disconnected node: analog_io[2] +Cell user_project_wrapper (1) disconnected node: analog_io[1] +Cell user_project_wrapper (1) disconnected node: analog_io[0] +Cell user_project_wrapper (1) disconnected node: io_in[29] +Cell user_project_wrapper (1) disconnected node: io_in[28] +Cell user_project_wrapper (1) disconnected node: io_in[27] +Cell user_project_wrapper (1) disconnected node: io_in[26] +Cell user_project_wrapper (1) disconnected node: io_in[25] +Cell user_project_wrapper (1) disconnected node: io_in[24] +Cell user_project_wrapper (1) disconnected node: io_in[23] +Cell user_project_wrapper (1) disconnected node: io_in[22] +Cell user_project_wrapper (1) disconnected node: io_in[21] +Cell user_project_wrapper (1) disconnected node: io_in[20] +Cell user_project_wrapper (1) disconnected node: io_in[19] +Cell user_project_wrapper (1) disconnected node: io_in[18] +Cell user_project_wrapper (1) disconnected node: io_in[17] +Cell user_project_wrapper (1) disconnected node: io_in[16] +Cell user_project_wrapper (1) disconnected node: io_in[15] +Cell user_project_wrapper (1) disconnected node: io_in[14] +Cell user_project_wrapper (1) disconnected node: io_in[13] +Cell user_project_wrapper (1) disconnected node: io_in[12] +Cell user_project_wrapper (1) disconnected node: io_in[11] +Cell user_project_wrapper (1) disconnected node: io_in[10] +Cell user_project_wrapper (1) disconnected node: io_in[9] +Cell user_project_wrapper (1) disconnected node: io_in[8] +Cell user_project_wrapper (1) disconnected node: io_oeb[29] +Cell user_project_wrapper (1) disconnected node: io_oeb[28] +Cell user_project_wrapper (1) disconnected node: io_oeb[27] +Cell user_project_wrapper (1) disconnected node: io_oeb[26] +Cell user_project_wrapper (1) disconnected node: io_oeb[25] +Cell user_project_wrapper (1) disconnected node: io_oeb[24] +Cell user_project_wrapper (1) disconnected node: io_oeb[23] +Cell user_project_wrapper (1) disconnected node: io_oeb[22] +Cell user_project_wrapper (1) disconnected node: io_oeb[21] +Cell user_project_wrapper (1) disconnected node: io_oeb[20] +Cell user_project_wrapper (1) disconnected node: io_oeb[19] +Cell user_project_wrapper (1) disconnected node: io_oeb[18] +Cell user_project_wrapper (1) disconnected node: io_oeb[17] +Cell user_project_wrapper (1) disconnected node: io_oeb[16] +Cell user_project_wrapper (1) disconnected node: io_oeb[15] +Cell user_project_wrapper (1) disconnected node: io_oeb[14] +Cell user_project_wrapper (1) disconnected node: io_oeb[13] +Cell user_project_wrapper (1) disconnected node: io_oeb[12] +Cell user_project_wrapper (1) disconnected node: io_oeb[11] +Cell user_project_wrapper (1) disconnected node: io_oeb[10] +Cell user_project_wrapper (1) disconnected node: io_oeb[9] +Cell user_project_wrapper (1) disconnected node: io_oeb[8] +Cell user_project_wrapper (1) disconnected node: io_out[29] +Cell user_project_wrapper (1) disconnected node: io_out[28] +Cell user_project_wrapper (1) disconnected node: io_out[27] +Cell user_project_wrapper (1) disconnected node: io_out[26] +Cell user_project_wrapper (1) disconnected node: io_out[25] +Cell user_project_wrapper (1) disconnected node: io_out[24] +Cell user_project_wrapper (1) disconnected node: io_out[23] +Cell user_project_wrapper (1) disconnected node: io_out[22] +Cell user_project_wrapper (1) disconnected node: io_out[21] +Cell user_project_wrapper (1) disconnected node: io_out[20] +Cell user_project_wrapper (1) disconnected node: io_out[19] +Cell user_project_wrapper (1) disconnected node: io_out[18] +Cell user_project_wrapper (1) disconnected node: io_out[17] +Cell user_project_wrapper (1) disconnected node: io_out[16] +Cell user_project_wrapper (1) disconnected node: io_out[15] +Cell user_project_wrapper (1) disconnected node: io_out[14] +Cell user_project_wrapper (1) disconnected node: io_out[13] +Cell user_project_wrapper (1) disconnected node: io_out[12] +Cell user_project_wrapper (1) disconnected node: io_out[11] +Cell user_project_wrapper (1) disconnected node: io_out[10] +Cell user_project_wrapper (1) disconnected node: io_out[9] +Cell user_project_wrapper (1) disconnected node: io_out[8] +Subcircuit summary: +Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +user_proj_example (1) |user_proj_example (1) +Number of devices: 1 |Number of devices: 1 +Number of nets: 543 |Number of nets: 543 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper +----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- +wb_clk_i |wb_clk_i +wb_rst_i |wb_rst_i +wbs_ack_o |wbs_ack_o +wbs_cyc_i |wbs_cyc_i +wbs_stb_i |wbs_stb_i +wbs_we_i |wbs_we_i +vccd2 |vccd2 +vssd2 |vssd2 +io_in[37] |io_in[37] +io_in[36] |io_in[36] +io_in[35] |io_in[35] +io_in[34] |io_in[34] +io_in[33] |io_in[33] +io_in[32] |io_in[32] +io_in[31] |io_in[31] +io_in[30] |io_in[30] +io_in[7] |io_in[7] +io_in[6] |io_in[6] +io_in[5] |io_in[5] +io_in[4] |io_in[4] +io_in[3] |io_in[3] +io_in[2] |io_in[2] +io_in[1] |io_in[1] +io_in[0] |io_in[0] +io_oeb[37] |io_oeb[37] +io_oeb[36] |io_oeb[36] +io_oeb[35] |io_oeb[35] +io_oeb[34] |io_oeb[34] +io_oeb[33] |io_oeb[33] +io_oeb[32] |io_oeb[32] +io_oeb[31] |io_oeb[31] +io_oeb[30] |io_oeb[30] +io_oeb[7] |io_oeb[7] +io_oeb[6] |io_oeb[6] +io_oeb[5] |io_oeb[5] +io_oeb[4] |io_oeb[4] +io_oeb[3] |io_oeb[3] +io_oeb[2] |io_oeb[2] +io_oeb[1] |io_oeb[1] +io_oeb[0] |io_oeb[0] +io_out[37] |io_out[37] +io_out[36] |io_out[36] +io_out[35] |io_out[35] +io_out[34] |io_out[34] +io_out[33] |io_out[33] +io_out[32] |io_out[32] +io_out[31] |io_out[31] +io_out[30] |io_out[30] +io_out[7] |io_out[7] +io_out[6] |io_out[6] +io_out[5] |io_out[5] +io_out[4] |io_out[4] +io_out[3] |io_out[3] +io_out[2] |io_out[2] +io_out[1] |io_out[1] +io_out[0] |io_out[0] +user_irq[2] |user_irq[2] +user_irq[1] |user_irq[1] +user_irq[0] |user_irq[0] +la_data_in[127] |la_data_in[127] +la_data_in[126] |la_data_in[126] +la_data_in[125] |la_data_in[125] +la_data_in[124] |la_data_in[124] +la_data_in[123] |la_data_in[123] +la_data_in[122] |la_data_in[122] +la_data_in[121] |la_data_in[121] +la_data_in[120] |la_data_in[120] +la_data_in[119] |la_data_in[119] +la_data_in[118] |la_data_in[118] +la_data_in[117] |la_data_in[117] +la_data_in[116] |la_data_in[116] +la_data_in[115] |la_data_in[115] +la_data_in[114] |la_data_in[114] +la_data_in[113] |la_data_in[113] +la_data_in[112] |la_data_in[112] +la_data_in[111] |la_data_in[111] +la_data_in[110] |la_data_in[110] +la_data_in[109] |la_data_in[109] +la_data_in[108] |la_data_in[108] +la_data_in[107] |la_data_in[107] +la_data_in[106] |la_data_in[106] +la_data_in[105] |la_data_in[105] +la_data_in[104] |la_data_in[104] +la_data_in[103] |la_data_in[103] +la_data_in[102] |la_data_in[102] +la_data_in[101] |la_data_in[101] +la_data_in[100] |la_data_in[100] +la_data_in[99] |la_data_in[99] +la_data_in[98] |la_data_in[98] +la_data_in[97] |la_data_in[97] +la_data_in[96] |la_data_in[96] +la_data_in[95] |la_data_in[95] +la_data_in[94] |la_data_in[94] +la_data_in[93] |la_data_in[93] +la_data_in[92] |la_data_in[92] +la_data_in[91] |la_data_in[91] +la_data_in[90] |la_data_in[90] +la_data_in[89] |la_data_in[89] +la_data_in[88] |la_data_in[88] +la_data_in[87] |la_data_in[87] +la_data_in[86] |la_data_in[86] +la_data_in[85] |la_data_in[85] +la_data_in[84] |la_data_in[84] +la_data_in[83] |la_data_in[83] +la_data_in[82] |la_data_in[82] +la_data_in[81] |la_data_in[81] +la_data_in[80] |la_data_in[80] +la_data_in[79] |la_data_in[79] +la_data_in[78] |la_data_in[78] +la_data_in[77] |la_data_in[77] +la_data_in[76] |la_data_in[76] +la_data_in[75] |la_data_in[75] +la_data_in[74] |la_data_in[74] +la_data_in[73] |la_data_in[73] +la_data_in[72] |la_data_in[72] +la_data_in[71] |la_data_in[71] +la_data_in[70] |la_data_in[70] +la_data_in[69] |la_data_in[69] +la_data_in[68] |la_data_in[68] +la_data_in[67] |la_data_in[67] +la_data_in[66] |la_data_in[66] +la_data_in[65] |la_data_in[65] +la_data_in[64] |la_data_in[64] +la_data_in[63] |la_data_in[63] +la_data_in[62] |la_data_in[62] +la_data_in[61] |la_data_in[61] +la_data_in[60] |la_data_in[60] +la_data_in[59] |la_data_in[59] +la_data_in[58] |la_data_in[58] +la_data_in[57] |la_data_in[57] +la_data_in[56] |la_data_in[56] +la_data_in[55] |la_data_in[55] +la_data_in[54] |la_data_in[54] +la_data_in[53] |la_data_in[53] +la_data_in[52] |la_data_in[52] +la_data_in[51] |la_data_in[51] +la_data_in[50] |la_data_in[50] +la_data_in[49] |la_data_in[49] +la_data_in[48] |la_data_in[48] +la_data_in[47] |la_data_in[47] +la_data_in[46] |la_data_in[46] +la_data_in[45] |la_data_in[45] +la_data_in[44] |la_data_in[44] +la_data_in[43] |la_data_in[43] +la_data_in[42] |la_data_in[42] +la_data_in[41] |la_data_in[41] +la_data_in[40] |la_data_in[40] +la_data_in[39] |la_data_in[39] +la_data_in[38] |la_data_in[38] +la_data_in[37] |la_data_in[37] +la_data_in[36] |la_data_in[36] +la_data_in[35] |la_data_in[35] +la_data_in[34] |la_data_in[34] +la_data_in[33] |la_data_in[33] +la_data_in[32] |la_data_in[32] +la_data_in[31] |la_data_in[31] +la_data_in[30] |la_data_in[30] +la_data_in[29] |la_data_in[29] +la_data_in[28] |la_data_in[28] +la_data_in[27] |la_data_in[27] +la_data_in[26] |la_data_in[26] +la_data_in[25] |la_data_in[25] +la_data_in[24] |la_data_in[24] +la_data_in[23] |la_data_in[23] +la_data_in[22] |la_data_in[22] +la_data_in[21] |la_data_in[21] +la_data_in[20] |la_data_in[20] +la_data_in[19] |la_data_in[19] +la_data_in[18] |la_data_in[18] +la_data_in[17] |la_data_in[17] +la_data_in[16] |la_data_in[16] +la_data_in[15] |la_data_in[15] +la_data_in[14] |la_data_in[14] +la_data_in[13] |la_data_in[13] +la_data_in[12] |la_data_in[12] +la_data_in[11] |la_data_in[11] +la_data_in[10] |la_data_in[10] +la_data_in[9] |la_data_in[9] +la_data_in[8] |la_data_in[8] +la_data_in[7] |la_data_in[7] +la_data_in[6] |la_data_in[6] +la_data_in[5] |la_data_in[5] +la_data_in[4] |la_data_in[4] +la_data_in[3] |la_data_in[3] +la_data_in[2] |la_data_in[2] +la_data_in[1] |la_data_in[1] +la_data_in[0] |la_data_in[0] +la_data_out[127] |la_data_out[127] +la_data_out[126] |la_data_out[126] +la_data_out[125] |la_data_out[125] +la_data_out[124] |la_data_out[124] +la_data_out[123] |la_data_out[123] +la_data_out[122] |la_data_out[122] +la_data_out[121] |la_data_out[121] +la_data_out[120] |la_data_out[120] +la_data_out[119] |la_data_out[119] +la_data_out[118] |la_data_out[118] +la_data_out[117] |la_data_out[117] +la_data_out[116] |la_data_out[116] +la_data_out[115] |la_data_out[115] +la_data_out[114] |la_data_out[114] +la_data_out[113] |la_data_out[113] +la_data_out[112] |la_data_out[112] +la_data_out[111] |la_data_out[111] +la_data_out[110] |la_data_out[110] +la_data_out[109] |la_data_out[109] +la_data_out[108] |la_data_out[108] +la_data_out[107] |la_data_out[107] +la_data_out[106] |la_data_out[106] +la_data_out[105] |la_data_out[105] +la_data_out[104] |la_data_out[104] +la_data_out[103] |la_data_out[103] +la_data_out[102] |la_data_out[102] +la_data_out[101] |la_data_out[101] +la_data_out[100] |la_data_out[100] +la_data_out[99] |la_data_out[99] +la_data_out[98] |la_data_out[98] +la_data_out[97] |la_data_out[97] +la_data_out[96] |la_data_out[96] +la_data_out[95] |la_data_out[95] +la_data_out[94] |la_data_out[94] +la_data_out[93] |la_data_out[93] +la_data_out[92] |la_data_out[92] +la_data_out[91] |la_data_out[91] +la_data_out[90] |la_data_out[90] +la_data_out[89] |la_data_out[89] +la_data_out[88] |la_data_out[88] +la_data_out[87] |la_data_out[87] +la_data_out[86] |la_data_out[86] +la_data_out[85] |la_data_out[85] +la_data_out[84] |la_data_out[84] +la_data_out[83] |la_data_out[83] +la_data_out[82] |la_data_out[82] +la_data_out[81] |la_data_out[81] +la_data_out[80] |la_data_out[80] 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|io_out[13] +io_out[14] |io_out[14] +io_out[15] |io_out[15] +io_out[16] |io_out[16] +io_out[17] |io_out[17] +io_out[18] |io_out[18] +io_out[19] |io_out[19] +io_out[20] |io_out[20] +io_out[21] |io_out[21] +io_out[22] |io_out[22] +io_out[23] |io_out[23] +io_out[24] |io_out[24] +io_out[25] |io_out[25] +io_out[26] |io_out[26] +io_out[27] |io_out[27] +io_out[28] |io_out[28] +io_out[29] |io_out[29] +io_out[8] |io_out[8] +io_out[9] |io_out[9] +user_clock2 |user_clock2 +vccd1 |vccd1 +vdda1 |vdda1 +vdda2 |vdda2 +vssa1 |vssa1 +vssa2 |vssa2 +vssd1 |vssd1 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes user_project_wrapper and user_project_wrapper are equivalent. + +Final result: Circuits match uniquely. +. diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.unflattened b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/lvs.unflattened new file mode 100644 index 00000000..e69de29b diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml new file mode 100644 index 00000000..2db2ff83 --- /dev/null +++ b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/spike_check.xml @@ -0,0 +1,15 @@ + + + gdsArea0 null-shapes & bad paths + /tmp/tmp5bbb3lz4/repo/gds/user_project_wrapper.gds + + + + + + + + + + + diff --git a/precheck_results/12_MAY_2026___07_45_39/outputs/reports/user_project_wrapper.gds.spice.gz b/precheck_results/12_MAY_2026___07_45_39/outputs/reports/user_project_wrapper.gds.spice.gz new file mode 100644 index 0000000000000000000000000000000000000000..1a84cbf17f9c6d3e27718aa6cafa4a611e0693d7 GIT binary patch literal 3145996 zcmZ5{bySp5_bvz$qO^e0($XN^B_JT6NW*}1Bi)0vbPpXO4xx0Xbc1vZHFP)3FvHAT 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