Chisel 7.0.0 error from testbench in Verilator

[oharboe]

Any tips?

Chisel 7.0.0 error from testbench:

primary-sources/ram_4x64.sv:83:24: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.
                                                                                                                                                                                                                                                                                             : ... In instance svsimTestbench.dut.....queue.ram_ext
   83 |             _RANDOM_MEM[j +: 32] = $urandom;  
      |                        ^
                ... For warning description see https://verilator.org/warn/WIDTH?v=5.006
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)

[oharboe]

Workaround:

    val backendSpecificCompilationSettings = svsim.verilator.Backend.CompilationSettings(
      traceStyle = Some(
        svsim.verilator.Backend.CompilationSettings
          .TraceStyle(svsim.verilator.Backend.CompilationSettings.TraceKind.Vcd, traceUnderscore = true)
      ),
      // FIXME should we care about this?
      disabledWarnings = Seq("WIDTH")
    )

[seldridge]

This should have been fixed as of CIRCT 1.111.0 via: llvm/circt#8351

Can you share what CIRCT version that Verilog is being generated from? Also, is this 7.0.0-RC1, 7.0.0-RC2, or 7.0.0-RC3?

[oharboe]

Upgrading from 1.109.0 til 1.126.0 fixed that problem, but introduced new ones...

%Error: bazel-out/k8-opt/bin/.../Simulation/layers-Foo-Simulation.sv:4:12: Cannot find include file: 'layers-Foo-Simulation.sv'
    4 |   `include "layers-Foo-Simulation.sv"
      |            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        ... Looked in:
             bazel-out/k8-opt/bin/.../layers-Foo-Simulation.sv
             bazel-out/k8-opt/bin/.../layers-Foo-Simulation.sv.v

Will need to dig in.

[oharboe]

1.111.0 worked and fixes the problem 😌

I suspect the incompatibilty with our build scripts is that firtool used to generate one .sv file and now is producing multiple and we're assuming it was only one in our bazel scripts.

If this is the case, then the solution for us is to use a folder of files as input for the next stage in bazel. We actually want to use bazel instead of make to build the .cpp files from Verilator, because then we get caching so that when we modify one module in Chisel, we don't have to rerun verilator.