Add netv2 board and default hardware design

Signed-off-by: Tomasz Michalak <[email protected]>

Author: tmichalak

other/boards.json

@@ -29,6 +29,11 @@
         "device": "a200t",
         "package": "sbg484-1"
     },
+    "netv2": {
+        "family": "xc7",
+        "device": "a100t",
+        "package": "fgg484-2"
+    },
     "icebreaker": {
         "family": "ice40",
         "device": "up5k",

other/vendors.json

@@ -1,6 +1,6 @@
 {
     "xilinx": {
-        "boards": ["arty-a35t", "arty-a100t", "basys3", "zybo", "nexys-video"],
+        "boards": ["arty-a35t", "arty-a100t", "basys3", "zybo", "nexys-video", "netv2"],
         "toolchains": ["vivado", "yosys-vivado", "yosys-vivado-uhdm", "vpr", "vpr-fasm2bels", "nextpnr-xilinx", "nextpnr-fpga-interchange", "nextpnr-xilinx-fasm2bels"]
     },
     "lattice-ice40": {

project/netv2-fpga.json

@@ -0,0 +1,28 @@
+{
+    "srcs": [
+	"src/netv2-fpga/i2c_snoop.v",
+	"src/netv2-fpga/hdcp_block.v",
+	"src/netv2-fpga/diff_network.v",
+	"src/netv2-fpga/shuffle_network.v",
+	"src/netv2-fpga/hdcp_cipher.v",
+	"src/netv2-fpga/hdcp_lfsr.v",
+	"src/netv2-fpga/hdcp_mod.v",
+	"third_party/vexriscv-verilog/VexRiscv_Debug.v",
+	"src/netv2-fpga/top.v"
+        ],
+    "top": "top",
+    "name": "netv2-fpga",
+    "data": [
+        "src/netv2-fpga/mem.init",
+        "src/netv2-fpga/edid_mem_1.init",
+        "src/netv2-fpga/mem_2.init",
+        "src/netv2-fpga/edid_mem.init"
+    ],
+    "clocks": {
+        "IO_CLK": 10.0
+    },
+    "vendors": {
+        "xilinx": ["netv2"]
+    },
+    "required_toolchains": ["vivado", "yosys-vivado"]
+}