Add tests for Crosslink NX with FPGA Interchange

Signed-off-by: Robert Szczepanski <[email protected]>

Author: robertszczepanski

assets/boards.yaml

@@ -46,6 +46,10 @@ lifcl-17:
   family: nexus
   device: LIFCL-17
   package: 8UWG72C
+lifcl-17-WLCSP72:
+  family: nexus
+  device: LIFCL-17
+  package: WLCSP72
 xczu7ev:
   family: xcup
   device: xczu7ev

assets/project/hps-accel-gen1-nexus.yaml

@@ -15,5 +15,6 @@ clock_aliases:
 vendors:
   lattice-nexus:
     - lifcl-17
+    - lifcl-17-WLCSP72
 required_toolchains:
   - nextpnr-nexus

assets/project/hps-accel-gen2-nexus.yaml

@@ -15,6 +15,7 @@ clock_aliases:
 vendors:
   lattice-nexus:
     - lifcl-17
+    - lifcl-17-WLCSP72
 required_toolchains:
   - nextpnr-nexus
 skip_toolchains:

assets/project/oneblink.yaml

@@ -17,6 +17,7 @@ vendors:
   lattice-nexus:
     - lifcl-40
     - lifcl-17
+    - lifcl-17-WLCSP72
   quicklogic:
     - quickfeather
 required_toolchains:

assets/vendors.yaml

@@ -28,10 +28,12 @@ lattice-nexus:
   boards:
     - lifcl-40
     - lifcl-17
+    - lifcl-17-WLCSP72
   toolchains:
     - nextpnr-nexus
     - synpro-radiant
     - lse-radiant
+    - nextpnr-fpga-interchange
 quicklogic:
   boards:
     - quickfeather

src/hps-accel-gen1-nexus/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,14 @@
+set_property PACKAGE_PIN A3 [get_ports spiflash4x_cs_n]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_cs_n]
+set_property PACKAGE_PIN B4 [get_ports spiflash4x_clk]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_clk]
+set_property PACKAGE_PIN B5 [get_ports spiflash4x_dq[0]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[0]]
+set_property PACKAGE_PIN C4 [get_ports spiflash4x_dq[1]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[1]]
+set_property PACKAGE_PIN B3 [get_ports spiflash4x_dq[2]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[2]]
+set_property PACKAGE_PIN B2 [get_ports spiflash4x_dq[3]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[3]]
+set_property PACKAGE_PIN G3 [get_ports user_led0]
+set_property IOSTANDARD LVCMOS18H [get_ports user_led0]

src/hps-accel-gen2-nexus/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,22 @@
+set_property PACKAGE_PIN A3 [get_ports spiflash4x_cs_n]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_cs_n]
+set_property SLEW FAST [get_ports spiflash4x_cs_n]
+set_property PACKAGE_PIN B4 [get_ports spiflash4x_clk]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_clk]
+set_property SLEW FAST [get_ports spiflash4x_clk]
+set_property PACKAGE_PIN B5 [get_ports spiflash4x_dq[0]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[0]]
+set_property SLEW FAST [get_ports spiflash4x_dq[0]]
+set_property PACKAGE_PIN C4 [get_ports spiflash4x_dq[1]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[1]]
+set_property SLEW FAST [get_ports spiflash4x_dq[1]]
+set_property PACKAGE_PIN B3 [get_ports spiflash4x_dq[2]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[2]]
+set_property SLEW FAST [get_ports spiflash4x_dq[2]]
+set_property PACKAGE_PIN B2 [get_ports spiflash4x_dq[3]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[3]]
+set_property SLEW FAST [get_ports spiflash4x_dq[3]]
+set_property PACKAGE_PIN E2 [get_ports serial_rx]
+set_property IOSTANDARD LVCMOS18 [get_ports serial_rx]
+set_property PACKAGE_PIN G1 [get_ports serial_tx]
+set_property IOSTANDARD LVCMOS18H [get_ports serial_tx]

src/oneblink/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,7 @@
+set_property LOC B4 [get_ports clk]
+set_property LOC A3 [get_ports out]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports out]
+
+create_clock -name clk -period 13.333 [get_ports clk]