From 06c9571eab87cda00d5aa8d50b9c7d543d7b86c2 Mon Sep 17 00:00:00 2001
From: Matthew Lister <chocolatepatty@hotmail.co.uk>
Date: Wed, 17 Jun 2020 10:06:56 +0100
Subject: [PATCH 1/2] added verilog exporter to current version

re-implemented a slightly improved version of the verilog exporter for the current version of the master

export code still a little messy and testing has been limited but operational
---
 src/logicsim/App.java            |  17 +
 src/logicsim/CircuitPart.java    |   6 +-
 src/logicsim/Gate.java           |   4 -
 src/logicsim/HTMLHelp.java       |   3 +-
 src/logicsim/LSFrame.java        | 102 ++++-
 src/logicsim/LSPanel.java        |  14 +-
 src/logicsim/LSToggleButton.java |   3 +-
 src/logicsim/Lang.java           |   2 +-
 src/logicsim/Pin.java            |   6 +-
 src/logicsim/VerilogCreator.java | 681 +++++++++++++++++++++++++++++++
 src/logicsim/VerilogFile.java    |  74 ++++
 src/logicsim/Wire.java           |  18 +-
 src/logicsim/XMLCreator.java     |   4 +-
 13 files changed, 888 insertions(+), 46 deletions(-)
 create mode 100644 src/logicsim/VerilogCreator.java
 create mode 100644 src/logicsim/VerilogFile.java

diff --git a/src/logicsim/App.java b/src/logicsim/App.java
index 6483e42..de4f50d 100755
--- a/src/logicsim/App.java
+++ b/src/logicsim/App.java
@@ -12,10 +12,13 @@
 import java.util.Map;
 import java.util.Objects;
 
+import javax.swing.JOptionPane;
+
 public class App {
 
 	public static final String APP_TITLE = "LogicSim";
 	public static final String CIRCUIT_FILE_SUFFIX = "lsc";
+	public static final String VERILOG_FILE_SUFFIX = "v";
 	public static final String MODULE_FILE_SUFFIX = "lsm";
 	public static final String GRAPHICS_FORMAT = "png";
 	public static boolean Running_From_Jar = false;
@@ -191,6 +194,20 @@ public static String getCircuitPath() {
 		}
 		return "";
 	}
+	
+	public static String getVerilogPath() {
+		File f = new File("");
+		String fname = f.getAbsolutePath() + "/verilog/";
+		f = new File(fname);
+		if (f != null && f.exists() && f.isDirectory()) {
+			return new String(f.getAbsolutePath() + "/");
+		} else {
+			JOptionPane.showMessageDialog(null,
+					"Directory verilog not found.\nPlease run the program from its directory");
+			System.exit(0);
+		}
+		return "";
+	}
 
 	public static Gate getGate(String type) {
 		for (Category cat : cats) {
diff --git a/src/logicsim/CircuitPart.java b/src/logicsim/CircuitPart.java
index 3461063..97b03d2 100755
--- a/src/logicsim/CircuitPart.java
+++ b/src/logicsim/CircuitPart.java
@@ -60,10 +60,14 @@ public static int round(int num) {
 
 	public static final String TEXT = "text";
 
-	public String TEXT_DEFAULT = "";
+	public String TEXT_DEFAULT = "<Label>";
 
 	public String text;
 
+	public String type;
+	
+	protected String label;
+
 	public CircuitPart(int x, int y) {
 		this.x = x;
 		this.y = y;
diff --git a/src/logicsim/Gate.java b/src/logicsim/Gate.java
index 2a3df2a..a2beace 100755
--- a/src/logicsim/Gate.java
+++ b/src/logicsim/Gate.java
@@ -41,8 +41,6 @@ public class Gate extends CircuitPart {
 
 	protected int height = 60;
 
-	protected String label;
-
 	protected int labelOffsetX;
 
 	protected int labelOffsetY;
@@ -67,8 +65,6 @@ public class Gate extends CircuitPart {
 	 */
 	public int rotate90 = 0;
 
-	protected String type;
-
 	protected boolean variableInputCountSupported = false;
 
 	protected int width = 60;
diff --git a/src/logicsim/HTMLHelp.java b/src/logicsim/HTMLHelp.java
index d0f9d79..92edff9 100755
--- a/src/logicsim/HTMLHelp.java
+++ b/src/logicsim/HTMLHelp.java
@@ -96,8 +96,7 @@ private void initComponents() {
 		jButton_ok = new javax.swing.JButton();
 		jScrollPane1 = new javax.swing.JScrollPane();
 		jTextPane1 = new javax.swing.JTextPane();
-		jTextPane1.setContentType("text/html;charset=UTF-8");
-		
+
 		jButton_ok.setText("OK");
 		jButton_ok.addActionListener(new java.awt.event.ActionListener() {
 			public void actionPerformed(java.awt.event.ActionEvent evt) {
diff --git a/src/logicsim/LSFrame.java b/src/logicsim/LSFrame.java
index c7744ca..61931e8 100755
--- a/src/logicsim/LSFrame.java
+++ b/src/logicsim/LSFrame.java
@@ -53,6 +53,7 @@ public class LSFrame extends JFrame implements ActionListener, CircuitChangedLis
 	private static final long serialVersionUID = -5281157929385660575L;
 
 	LogicSimFile lsFile;
+	VerilogFile vFile;
 
 	JMenuBar mnuBar;
 	JToolBar btnBar;
@@ -75,6 +76,7 @@ public LSFrame(String title) {
 
 		lsFile = new LogicSimFile(defaultCircuitFileName());
 		lsFile.circuit.setRepaintListener(lspanel);
+		vFile = new VerilogFile(defaultVerilogFileName());
 		lspanel.setChangeListener(this);
 
 		try {
@@ -109,6 +111,13 @@ private String defaultCircuitFileName() {
 		fn += "." + App.CIRCUIT_FILE_SUFFIX;
 		return fn;
 	}
+	
+	private String defaultVerilogFileName() {
+		String fn = App.getVerilogPath();
+		fn += I18N.tr(Lang.UNNAMED);
+		fn += "." + App.VERILOG_FILE_SUFFIX;
+		return fn;
+	}
 
 	/** Component initialization */
 	private void createUI() {
@@ -183,6 +192,14 @@ public void actionPerformed(ActionEvent e) {
 			}
 		});
 		mnu.add(m);
+		
+		m = createMenuItem(Lang.VEXPORT, 0, true);
+		m.addActionListener(new ActionListener() {
+			public void actionPerformed(ActionEvent e) {
+				actionVExport(e);
+			}
+		});
+		mnu.add(m);
 
 		m = createMenuItem(Lang.PRINT, 0, true);
 		m.addActionListener(new ActionListener() {
@@ -593,14 +610,14 @@ public void actionPerformed(ActionEvent e) {
 		});
 		btnBar.add(btnToggle, null);
 
-		// btnLS = new LSButton("select", Lang.SELECT);
-		// btnLS.addActionListener(new ActionListener() {
-		// public void actionPerformed(ActionEvent e) {
-		// lspanel.setAction(LSPanel.ACTION_SELECT);
-		// lspanel.requestFocusInWindow();
-		// }
-		// });
-		// btnBar.add(btnLS, null);
+		//btnLS = new LSButton("select", Lang.SELECT);
+		//btnLS.addActionListener(new ActionListener() {
+		//	public void actionPerformed(ActionEvent e) {
+		//		lspanel.setAction(LSPanel.ACTION_SELECT);
+		//		lspanel.requestFocusInWindow();
+		//	}
+		//});
+		//btnBar.add(btnLS, null);
 
 		btnBar.add(getMenuGap());
 
@@ -787,13 +804,10 @@ void actionSimulate(ActionEvent e) {
 				lspanel.circuit.deselectAll();
 				repaint();
 				Simulation.getInstance().start();
-				changedStatusText(I18N.tr(Lang.SIMULATION_STARTED));
 			}
 		} else {
-			if (Simulation.getInstance().isRunning()) {
+			if (Simulation.getInstance().isRunning())
 				Simulation.getInstance().stop();
-				changedStatusText(I18N.tr(Lang.SIMULATION_STOPPED));
-			}
 		}
 	}
 
@@ -913,6 +927,21 @@ void actionSave(ActionEvent e, boolean saveAs) {
 		lsFile.changed = false;
 		fillGateList();
 	}
+	
+	void actionVExport(ActionEvent e) {
+		if (showVExportDialog() == false)
+			return;
+		vFile.circuit = lspanel.circuit;
+		try {
+			VerilogCreator.createVerilog(vFile);
+		} catch (RuntimeException err) {
+			System.err.println(err);
+			err.printStackTrace(System.err);
+			JOptionPane.showMessageDialog(this, I18N.tr(Lang.SAVEERROR) + " " + err.getMessage());
+		}
+		setStatusText(String.format(I18N.tr(Lang.SAVED), vFile.fileName));
+		fillGateList();
+	}
 
 	/**
 	 * helper method to show the save dialog
@@ -947,6 +976,48 @@ public boolean showSaveDialog() {
 		} else
 			return false;
 	}
+	
+	/**
+	 * helper method to show the verilog-export dialog
+	 * 
+	 * @return
+	 */
+	public boolean showVExportDialog() {
+		File file = new File(vFile.fileName);
+		String parentDirName = file.getParent();
+
+		JFileChooser chooser = new JFileChooser(parentDirName);
+		chooser.setDialogTitle(I18N.tr(Lang.SAVECIRCUIT));
+
+		String s = "Verilog Files (" + "." + App.VERILOG_FILE_SUFFIX + ")";
+		FileNameExtensionFilter filter = new FileNameExtensionFilter(s, App.VERILOG_FILE_SUFFIX);
+		chooser.setFileFilter(filter);
+
+		if (chooser.showSaveDialog(this) == JFileChooser.APPROVE_OPTION) {
+			vFile.fileName = chooser.getSelectedFile().getAbsolutePath();
+			// check fileName
+			int lastSeparator = vFile.fileName.lastIndexOf(File.separatorChar);
+			int lastDot = vFile.fileName.lastIndexOf(".");
+			if (lastDot < lastSeparator) {
+				// ending is missing
+				vFile.fileNameNE = vFile.fileName;
+				vFile.fileName += "." + App.VERILOG_FILE_SUFFIX;
+			}
+			else {
+				int iend = vFile.fileName.indexOf(".");
+				if (iend != -1) {
+				    vFile.fileNameNE = vFile.fileName.substring(0 , iend);
+				}
+			}
+			int lastSlash = vFile.fileNameNE.lastIndexOf("/");
+			if (lastSlash == 0) {
+				lastSlash = vFile.fileNameNE.lastIndexOf("\\");
+			}
+			vFile.fileNameNE = vFile.fileNameNE.substring(lastSlash+1,vFile.fileNameNE.length());
+			return true;
+		} else
+			return false;
+	}
 
 	/**
 	 * handles initial steps to create a new module
@@ -1044,9 +1115,6 @@ void fillGateList() {
 	 * @param e
 	 */
 	void actionLstGatesSelected(ListSelectionEvent e) {
-		if (Simulation.getInstance().isRunning())
-			return;
-		
 		int sel = lstParts.getSelectedIndex();
 		if (sel < 0)
 			return;
@@ -1241,11 +1309,9 @@ public void changedStatusText(String text) {
 			for (Component c : btnBar.getComponents()) {
 				if (c instanceof LSToggleButton) {
 					LSToggleButton b = (LSToggleButton) c;
-					if (!b.id.equals(I18N.langToStr(Lang.SIMULATE)))
-						b.setSelected(false);
+					b.setSelected(false);
 				}
 			}
-			return;
 		}
 		if (LSPanel.MSG_ABORTED.equals(text)) {
 			for (Component c : btnBar.getComponents()) {
diff --git a/src/logicsim/LSPanel.java b/src/logicsim/LSPanel.java
index ac185d6..d3808bb 100755
--- a/src/logicsim/LSPanel.java
+++ b/src/logicsim/LSPanel.java
@@ -187,13 +187,13 @@ public void mousePressed(MouseEvent e) {
 			int rx = CircuitPart.round(e.getX());
 			int ry = CircuitPart.round(e.getY());
 
-			boolean simRunning = Simulation.getInstance().isRunning();
+			boolean sim = Simulation.getInstance().isRunning();
 			boolean expertMode = LSProperties.MODE_EXPERT
 					.equals(LSProperties.getInstance().getProperty(LSProperties.MODE, LSProperties.MODE_NORMAL));
 
-			if (simRunning) {
+			if (sim) {
 				currentAction = ACTION_NONE;
-				//fireStatusText(NOTHING);
+				fireStatusText(NOTHING);
 			}
 
 			if (currentAction == ACTION_SELECT) {
@@ -208,7 +208,7 @@ public void mousePressed(MouseEvent e) {
 			}
 			// if (cp != null)
 			// System.out.println(cp.toStringAll());
-			if (!simRunning && cp instanceof Pin && !e.isAltDown() && currentAction == ACTION_NONE) {
+			if (!sim && cp instanceof Pin && !e.isAltDown() && currentAction == ACTION_NONE) {
 				// we start a new wire if the pin we clicked is an output OR
 				// if we are in expert mode
 				if (((Pin) cp).isOutput() || expertMode)
@@ -325,7 +325,7 @@ public void mousePressed(MouseEvent e) {
 				return;
 			}
 			// check if the part is a connector
-			if (cp instanceof Pin && !e.isAltDown() && !simRunning) {
+			if (cp instanceof Pin && !e.isAltDown() && !sim) {
 				Pin pin = ((Pin) cp);
 				fireStatusText(I18N.tr(Lang.PIN) + " (" + cp.getId() + ")");
 				// modify input (inverted or high or low or revert to normal type)
@@ -349,7 +349,7 @@ public void mousePressed(MouseEvent e) {
 				else
 					fireStatusText(I18N.getString(type, I18N.DESCRIPTION) + " (" + cp.getId() + ")");
 
-				if (parts.length > 0 && !simRunning) {
+				if (parts.length > 0 && !sim) {
 					// check if we clicked a new gate
 					if (!cp.isSelected()) {
 						cp.select();
@@ -359,7 +359,7 @@ public void mousePressed(MouseEvent e) {
 						parts = circuit.getSelected();
 					}
 				}
-			} else if (cp instanceof Wire && !simRunning) {
+			} else if (cp instanceof Wire && !sim) {
 				String s = cp.getProperty(CircuitPart.TEXT);
 				String desc = I18N.tr(Lang.WIRE);
 				if (s != null)
diff --git a/src/logicsim/LSToggleButton.java b/src/logicsim/LSToggleButton.java
index a759ca0..8cc8c30 100644
--- a/src/logicsim/LSToggleButton.java
+++ b/src/logicsim/LSToggleButton.java
@@ -8,12 +8,11 @@
 public class LSToggleButton extends JToggleButton {
 
 	private static final long serialVersionUID = 4992541122998327288L;
-	public final String id;
+
 	public LSToggleButton(String iconName, Lang toolTip) {
 		this.setDoubleBuffered(true);
 		this.setIcon(getIcon(iconName));
 		this.setToolTipText(I18N.tr(toolTip));
-		this.id = I18N.langToStr(toolTip);
 		// this.setBorderPainted(true);
 		// this.setBorder(BorderFactory.createLineBorder(Color.black));
 		// this.addMouseListener(this);
diff --git a/src/logicsim/Lang.java b/src/logicsim/Lang.java
index 86d644f..8cd17da 100755
--- a/src/logicsim/Lang.java
+++ b/src/logicsim/Lang.java
@@ -9,5 +9,5 @@ public enum Lang {
 	PRINT, PROPERTIES, QUESTION_CONFIRMDISCARD, QUESTION_CONFIRMSAVE, QUESTION_DELETE, READERROR, REMOVEGATE,
 	REMOVEPOINT, REMOVEPOINT_HELP, RESET, ROTATE, SAVE, SAVEAS, SAVECIRCUIT, SAVED, SAVEERROR, SELECT, SELECTALL,
 	SELECTNONE, SETTINGS, SIMULATE, TEXT, UNNAMED, WIRE, WIREEDIT, WIRENEW, WIRENEW_HELP, WIREPOINT, YES, ZOOMALL,
-	ZOOMIN, ZOOMOUT, SIMULATION_STARTED, SIMULATION_STOPPED
+	ZOOMIN, ZOOMOUT, VEXPORT
 }
diff --git a/src/logicsim/Pin.java b/src/logicsim/Pin.java
index 8b38b09..66119b3 100755
--- a/src/logicsim/Pin.java
+++ b/src/logicsim/Pin.java
@@ -30,6 +30,8 @@ public class Pin extends CircuitPart {
 
 	public int number;
 
+
+	
 	protected boolean level = false;
 	public int paintDirection = RIGHT;
 
@@ -55,8 +57,10 @@ public void setIoType(int ioType) {
 
 	public Pin(int x, int y, Gate gate, int number) {
 		super(x, y);
+		this.type = "pin";
 		this.parent = gate;
 		this.number = number;
+		loadProperties();
 	}
 
 	/**
@@ -79,7 +83,7 @@ private void drawLabel(Graphics2D g2) {
 		int y = getY();
 
 		g2.setFont(smallFont);
-		if (text != null && text.length() > 0) {
+		if (text != null && text.length() > 0 && text != "<Label>") {
 			if (paintDirection == RIGHT) {
 				if (POS_EDGE_TRIG.equals(text)) {
 					Polygon tr = new Polygon();
diff --git a/src/logicsim/VerilogCreator.java b/src/logicsim/VerilogCreator.java
new file mode 100644
index 0000000..185c079
--- /dev/null
+++ b/src/logicsim/VerilogCreator.java
@@ -0,0 +1,681 @@
+package logicsim;
+
+import java.io.File;
+import java.io.IOException;
+import java.io.FileOutputStream;
+import java.io.FileWriter;
+import java.io.StringWriter;
+import java.util.HashMap;
+import java.util.Iterator;
+import java.util.Properties;
+
+import javax.xml.parsers.DocumentBuilder;
+import javax.xml.parsers.DocumentBuilderFactory;
+import javax.xml.transform.OutputKeys;
+import javax.xml.transform.Transformer;
+import javax.xml.transform.TransformerFactory;
+import javax.xml.transform.dom.DOMSource;
+import javax.xml.transform.stream.StreamResult;
+
+import org.w3c.dom.Document;
+import org.w3c.dom.Element;
+import org.w3c.dom.Node;
+
+/**
+ * Generates a verilog file corresponding to the circuit
+ * Individual components, other than simple logic gates, are expressed as modules,
+ * thus corresponding modules with the correct I/O labels need to be present in the file system already
+ * to give a full verilog implementation
+ * 
+ * For proper output, all pins on gates used should have their label characteristic set as the title of that pin in the appropriate module.
+ * Other labels (i.e. the "text" attribute annotations added via properties) are not strictly necessary but will produce a much more comprehensible output.
+ * 
+ * @author Matthew Lister
+ * @version 1.0
+ */
+public class VerilogCreator {
+
+	public static void createVerilog(VerilogFile f) throws RuntimeException {
+		
+		HashMap<String, Integer> nameCounter = new HashMap<String, Integer>();
+		HashMap<CircuitPart, String> nameLookup = new HashMap<CircuitPart, String>();
+		
+		    try {
+		      File vOutput = new File(f.fileName);
+		      if (vOutput.createNewFile()) {
+				    
+				    try {
+				    	FileWriter vWriter = new FileWriter(f.fileName);
+				        vWriter.write("module " + f.fileNameNE + "(");
+				        vWriter.write(System.lineSeparator());
+				        
+				        buildLookupTables(f, nameCounter, nameLookup);
+
+				        writeInputs(vOutput, vWriter, f, nameCounter, nameLookup);
+				        writeOutputs(vOutput, vWriter, f, nameCounter, nameLookup);
+				        vWriter.write(");" + System.lineSeparator());
+				        vWriter.write(System.lineSeparator());
+				        vWriter.write(System.lineSeparator());
+				        vWriter.write(System.lineSeparator());
+				        
+				        writeWires(vOutput, vWriter, f, nameCounter, nameLookup);
+				        vWriter.write(System.lineSeparator());
+				        vWriter.write(System.lineSeparator());
+				        
+				        writeGates(vOutput, vWriter, f, nameCounter, nameLookup);
+				        vWriter.write(System.lineSeparator());
+				        vWriter.write(System.lineSeparator());
+
+				        vWriter.write("endmodule");
+				        
+				        
+				        vWriter.close();
+				    } catch (IOException e) {
+				        System.out.println("An error occurred.");
+				        e.printStackTrace();
+				    }
+				    
+		        System.out.println("File created: " + vOutput.getName());
+		      } else {
+		        System.out.println("File already exists.");
+		      }
+		    } catch (IOException e) {
+		      System.out.println("An error occurred.");
+		      e.printStackTrace();
+		    }
+	}
+	
+	public static void buildLookupTables(VerilogFile f, HashMap<String, Integer> nameCounter, HashMap<CircuitPart, String> nameLookup) {
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				
+				String vName = getVName(g);
+				Integer vNameCount;
+				if (nameCounter.containsKey(vName)) {
+					vNameCount = nameCounter.get(vName) + 1;
+				}
+				else {
+					vNameCount = 1;
+				}
+				String vNameNum = vName;
+				if (vNameCount > 1) {
+					vNameNum = vName + Integer.toString(vNameCount);
+				}
+				nameCounter.put(vName, vNameCount);
+				nameLookup.put(g, vNameNum);
+				
+				if (g.getInputs() != null) {
+					for (Pin i : g.getInputs()) {
+						
+						boolean isFree = true;
+						if (f.getWires() != null) {
+							for (Wire w : f.getWires()) {
+								
+								Pin toPin;
+								
+								if (w.getTo() instanceof Pin) {
+									toPin = (Pin) w.getTo();
+									isFree = (isFree && toPin != i);
+								};
+							}
+						}
+						if (isFree) {
+							String pinVName = getVName(i);
+							Integer pinVNameCount;
+							if (nameCounter.containsKey(pinVName)) {
+								pinVNameCount = nameCounter.get(pinVName) + 1;
+							}
+							else {
+								pinVNameCount = 1;
+							}
+							nameCounter.put(pinVName, pinVNameCount);
+							if (pinVNameCount > 1) {
+								nameLookup.put(i, pinVName + Integer.toString(pinVNameCount));
+							}
+							else {
+								nameLookup.put(i, pinVName);
+							}
+						}
+					}
+				}
+				if (g.getOutputs() != null) {
+					for (Pin i : g.getOutputs()) {
+						
+
+						String pinVName = getVName(i);
+						Integer pinVNameCount;
+						if (nameCounter.containsKey(pinVName)) {
+							pinVNameCount = nameCounter.get(pinVName) + 1;
+						}
+						else {
+							pinVNameCount = 1;
+						}
+						nameCounter.put(pinVName, pinVNameCount);
+						
+						if (pinVNameCount > 1) {
+							nameLookup.put(i, pinVName + Integer.toString(pinVNameCount));
+						}
+						else {
+							nameLookup.put(i, pinVName);
+						}
+						
+						if (f.getWires() != null) {
+							for (Wire w : f.getWires()) {
+								
+								Pin fromPin;
+								
+								if (w.getFrom() instanceof Pin) {
+									fromPin = (Pin) w.getFrom();
+
+									if (fromPin == i) {
+										nameLookup.put(w, nameLookup.get(i));
+									}
+								};
+							}
+						}
+						
+					}
+				}
+				
+			}
+		}
+	}
+	
+	public static String getVName(CircuitPart p) {
+
+			if (p.text == "<Label>") {
+				return p.type;
+			}
+			else {
+				return p.text;
+			}
+	}
+
+	
+	public static String getPinLabel(Pin p, Wire w) {
+		if (p.label != null && p.label != "<Label>") {
+			return p.label;
+		}
+		else if (p.text != "<Label>") {
+			return p.text;
+		}
+		else if (w != null) {
+			if (w.text != "<Label>") {
+				return w.text;
+			}
+			else {
+				return p.type;
+			}
+		}
+		else {
+			return p.type;
+		}
+	}
+
+	public static void writeInputs(File voutput, FileWriter vWriter, VerilogFile f, HashMap<String, Integer> nameCounter, HashMap<CircuitPart, String> nameLookup) {
+		boolean isFirst = true;
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				
+				if (g.getInputs() != null) {
+					for (Pin i : g.getInputs()) {
+						
+						boolean isFree = true;
+						if (f.getWires() != null) {
+							for (Wire w : f.getWires()) {
+								
+								Pin toPin;
+								
+								if (w.getTo() instanceof Pin) {
+									toPin = (Pin) w.getTo();
+									isFree = (isFree && toPin != i);
+								};
+								
+							}
+						}
+						if (isFree) {
+							String vName = nameLookup.get(i);
+							Integer vNameCount;
+							if (nameCounter.containsKey(vName)) {
+								vNameCount = nameCounter.get(vName) + 1;
+							}
+							else {
+								vNameCount = 1;
+							}
+							nameCounter.put(vName, vNameCount);
+							String pinLabel = getPinLabel(i, null);
+							
+							try {
+								if (pinLabel.charAt(0) != '_') {
+									if (!isFirst) {
+										vWriter.write("," + System.lineSeparator());
+									}
+									else {
+										isFirst = false;
+									}
+									
+									vWriter.write("			input wire " + vName);
+									
+								}
+							} 
+							catch (IOException e) {
+								    System.out.println("Input printing error");
+							}
+						}
+						
+					}
+				}
+				
+			}
+		}
+	}
+	
+	public static void writeOutputs(File voutput, FileWriter vWriter, VerilogFile f, HashMap<String, Integer> nameCounter, HashMap<CircuitPart, String> nameLookup) {
+		boolean isFirst = true;
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				
+				if (g.getInputs() != null) {
+					isFirst = false;
+				}
+			}
+		}
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				
+				if (g.getOutputs() != null) {
+					for (Pin i : g.getOutputs()) {
+						
+						boolean isFree = true;
+						if (f.getWires() != null) {
+							for (Wire w : f.getWires()) {
+								
+								Pin fromPin;
+								
+								if (w.getFrom() instanceof Pin) {
+									fromPin = (Pin) w.getFrom();
+									isFree = (isFree && fromPin != i);
+								};
+							}
+						}
+						if (isFree || nameLookup.get(i).charAt(0) == 'M') {
+							String vName = nameLookup.get(i);
+							
+							String pinLabel = getPinLabel(i, null);
+							
+							try {
+								if (pinLabel.charAt(0) != '_') {
+									if (!isFirst) {
+										vWriter.write("," + System.lineSeparator());
+									}
+									else {
+										isFirst = false;
+									}
+									
+									vWriter.write("			output wire " + vName);
+								}
+							} 
+							catch (IOException e) {
+								    System.out.println("Input printing error");
+							}
+						}
+						
+					}
+				}
+				
+			}
+		}
+	}
+	
+	public static void writeWires(File voutput, FileWriter vWriter, VerilogFile f, HashMap<String, Integer> nameCounter, HashMap<CircuitPart, String> nameLookup) {
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				
+				if (g.getOutputs() != null) {
+					for (Pin i : g.getOutputs()) {
+						
+						boolean isFree = true;
+						
+						Pin fromPin;
+						
+						if (f.getWires() != null) {
+							for (Wire w : f.getWires()) {
+								
+								
+								if (w.getFrom() instanceof Pin) {
+									fromPin = (Pin) w.getFrom();
+									isFree = (isFree && (fromPin != i));
+								};
+							}
+						}
+						if (!isFree && nameLookup.get(i).charAt(0) != 'M') {
+							try {
+								vWriter.write("	wire " + nameLookup.get(i) + ";");
+								vWriter.write(System.lineSeparator());
+							} catch (IOException e) {
+							    System.out.println("Wire printing error");
+							}
+						}
+						
+					}
+				}
+				
+			}
+		}
+		
+	}
+	
+	public static void writeGates(File voutput, FileWriter vWriter, VerilogFile f, HashMap<String, Integer> nameCounter, HashMap<CircuitPart, String> nameLookup) {
+		if (f.getGates() != null) {
+			for (Gate g : f.getGates()) {
+				//separate case for writing elementary logic gates
+				if (g.type == "and" || g.type == "or" || g.type == "xor" || g.type == "nand" || g.type == "nor" || g.type == "xnor" || g.type == "not") {
+					
+					try {
+						vWriter.write("	" + g.type + " (");
+					}
+					catch (IOException e) {
+					    System.out.println("Logic gate printing error");
+					} 
+					
+					boolean isFirst = true;
+					if (g.getOutputs() != null) {
+						for (Pin i : g.getOutputs()) {
+							
+							String wireName = "error";
+							boolean isFree = true;
+							Pin fromPin;
+							
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									if (w.getFrom() instanceof Pin) {
+										fromPin = (Pin) w.getFrom();
+										if (fromPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+										}
+									};
+									
+
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+							}
+							try {
+								if (isFirst) {
+									isFirst = false;
+									vWriter.write(wireName);
+								}
+								else {
+									vWriter.write(", " + wireName);
+								}	
+							} 
+							catch (IOException e) {
+							    System.out.println("Logic gate input printing error");
+							} 
+						}
+					}
+					if (g.getInputs() != null) {
+						for (Pin i : g.getInputs()) {
+							
+							String wireName = "error";
+							boolean isFree = true;
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									Pin toPin;
+									
+									if (w.getTo() instanceof Pin) {
+										toPin = (Pin) w.getTo();
+
+										if (toPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+										}
+									};
+									
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+							}
+							try {
+								if (isFirst) {
+									isFirst = false;
+									vWriter.write(wireName);
+								}
+								else {
+									vWriter.write(", " + wireName);
+								}	
+							} 
+							catch (IOException e) {
+							    System.out.println("logic gate output printing error");
+							} 
+						}
+					}
+					
+					try {
+						vWriter.write(");");
+						vWriter.write(System.lineSeparator());
+					}
+					catch (IOException e) {
+					    System.out.println("Logic gate printing error");
+					} 
+				}
+				
+				// treats buffer components as assign statements
+				else if (g.type == "buffer") {
+					
+					try {
+						vWriter.write("	assign ");
+					}
+					catch (IOException e) {
+					    System.out.println("Logic gate printing error");
+					} 
+					
+					boolean isFirst = true;
+					if (g.getOutputs() != null) {
+						for (Pin i : g.getOutputs()) {
+							
+							String wireName = "error";
+							boolean isFree = true;
+							Pin fromPin;
+							
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									if (w.getFrom() instanceof Pin) {
+										fromPin = (Pin) w.getFrom();
+										if (fromPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+										}
+									};
+									
+
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+							}
+							try {
+									vWriter.write(wireName + " = ");
+							} 
+							catch (IOException e) {
+							    System.out.println("Buffer output printing error");
+							} 
+						}
+					}
+					if (g.getInputs() != null) {
+						for (Pin i : g.getInputs()) {
+							
+							String wireName = "error";
+							boolean isFree = true;
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									Pin toPin;
+									
+									if (w.getTo() instanceof Pin) {
+										toPin = (Pin) w.getTo();
+
+										if (toPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+										}
+									};
+									
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+							}
+							try {
+								if (isFirst) {
+									isFirst = false;
+									vWriter.write(wireName);
+								}
+								else {
+									vWriter.write(wireName);
+								}	
+							} 
+							catch (IOException e) {
+							    System.out.println("buffer input printing error");
+							} 
+						}
+					}
+					
+					try {
+						vWriter.write(";");
+						vWriter.write(System.lineSeparator());
+					}
+					catch (IOException e) {
+					    System.out.println("buffer printing error");
+					} 
+				}
+
+				//case for all non-trivial gates
+				else {
+					String vName = nameLookup.get(g);
+					String vModule = g.type;
+					
+					try {
+						vWriter.write("	" + vModule);
+						vWriter.write(System.lineSeparator());
+						vWriter.write("	  " + vName + " (");
+						vWriter.write(System.lineSeparator());
+					} 
+					catch (IOException e) {
+					    System.out.println("Input printing error");
+					} 
+					boolean isFirst = false;
+					if (g.getPins() != null) {
+						isFirst = true;
+					}
+					if (g.getInputs() != null) {
+						for (Pin i : g.getInputs()) {
+							
+							String wireName = "error";
+							String pinLabel = "error";
+							boolean isFree = true;
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									Pin toPin;
+									
+									if (w.getTo() instanceof Pin) {
+										toPin = (Pin) w.getTo();
+
+										if (toPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+											pinLabel = getPinLabel(i, w);
+										}
+									};
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+								pinLabel = getPinLabel(i, null);
+							}
+							try {
+								if (pinLabel.charAt(0) != '_') {
+									if (isFirst) {
+										isFirst = false;
+										vWriter.write("	  ." + pinLabel + "(" + wireName + ")");
+									}
+									else {
+										vWriter.write("," + System.lineSeparator());
+										vWriter.write("	  ." + pinLabel + "(" + wireName + ")");
+									}
+								}
+							} 
+							catch (IOException e) {
+							    System.out.println("Input printing error");
+							} 
+						}
+					}
+					if (g.getOutputs() != null) {
+						for (Pin i : g.getOutputs()) {
+							
+							String wireName = "error";
+							String pinLabel = "error";
+							boolean isFree = true;
+							Pin fromPin;
+							
+							
+							if (f.getWires() != null) {
+								for (Wire w : f.getWires()) {
+									
+									if (w.getFrom() instanceof Pin) {
+										fromPin = (Pin) w.getFrom();
+										
+										if (fromPin == i) {
+											isFree = false;
+											wireName = nameLookup.get(w);
+											pinLabel = getPinLabel(i, w);
+										}
+									};
+								}
+							}
+							if (isFree) {
+								wireName = nameLookup.get(i);
+								pinLabel = getPinLabel(i, null);
+							}
+							try {
+								if (pinLabel.charAt(0) != '_') {
+									if (isFirst) {
+										isFirst = false;
+										vWriter.write("	  ." + pinLabel + "(" + wireName + ")");
+									}
+									else {
+										vWriter.write("," + System.lineSeparator());
+										vWriter.write("	  ." + pinLabel + "(" + wireName + ")");
+									}
+								}
+							} 
+							catch (IOException e) {
+							    System.out.println("Output printing error");
+							} 
+						}
+					}
+					
+					try {
+						vWriter.write(System.lineSeparator());
+						vWriter.write("	" + ");");
+						vWriter.write(System.lineSeparator());
+					} 
+					catch (IOException e) {
+					    System.out.println("Input printing error");
+					    System.out.println("Input printing error");
+					} 
+					
+					
+				}
+			}
+		}
+	}
+
+}
diff --git a/src/logicsim/VerilogFile.java b/src/logicsim/VerilogFile.java
new file mode 100644
index 0000000..7f09fc0
--- /dev/null
+++ b/src/logicsim/VerilogFile.java
@@ -0,0 +1,74 @@
+package logicsim;
+
+import java.io.File;
+import java.util.HashMap;
+import java.util.Map;
+import java.util.Vector;
+
+public class VerilogFile {
+	Circuit circuit = new Circuit();
+	Map<String, String> info = new HashMap<String, String>();
+	String fileName;
+	//file name without extension
+	String fileNameNE;
+
+	public VerilogFile(String fileName) {
+		this.fileName = fileName;
+	}
+
+	public VerilogFile(String fileName, Map<String, String> info, Vector<Gate> gates, Vector<Wire> wires) {
+		this(fileName);
+		this.info = info;
+		this.circuit.setGates(gates);
+	}
+
+	/**
+	 * extract the pure file name from an absolute path
+	 * 
+	 * @param fileName
+	 * @return
+	 */
+	public String extractFileName() {
+		File f = new File(fileName);
+		String name = f.getName();
+		// strip extension
+		name = name.substring(0, name.lastIndexOf('.'));
+		return name;
+	}
+
+	public Vector<Gate> getGates() {
+		return circuit.getGates();
+	}
+
+	public void setGates(Vector<Gate> gates) {
+		circuit.setGates(gates);
+	}
+
+	public void setWires(Vector<Wire> wires) {
+		circuit.setWires(wires);
+	}
+
+	public Vector<Wire> getWires() {
+		return circuit.getWires();
+	}
+
+	private String getKey(String key) {
+		return info.containsKey(key) ? info.get(key) : null;
+	}
+
+	public void setLabel(String value) {
+		info.put("label", value);
+	}
+
+	public void setDescription(String value) {
+		info.put("description", value);
+	}
+
+	public String getLabel() {
+		return getKey("label");
+	}
+
+	public String getDescription() {
+		return getKey("description");
+	}
+}
diff --git a/src/logicsim/Wire.java b/src/logicsim/Wire.java
index 93fbb53..458b867 100755
--- a/src/logicsim/Wire.java
+++ b/src/logicsim/Wire.java
@@ -170,14 +170,16 @@ public void draw(Graphics2D g2) {
 
 		g2.setColor(Color.black);
 
-		if (points.size() > 0) {
-			g2.drawString(text, (getFrom().getX() + points.get(0).getX()) / 2,
-					(getFrom().getY() + points.get(0).getY()) / 2);
-		} else {
-			if (getFrom() != null && getTo() == null && tempPoint != null) {
-				g2.drawString(text, (getFrom().getX() + tempPoint.x) / 2, (getFrom().getY() + tempPoint.y) / 2);
-			} else if (getFrom() != null && getTo() != null) {
-				g2.drawString(text, (getFrom().getX() + getTo().getX()) / 2, (getFrom().getY() + getTo().getY()) / 2);
+		if (text != null && text.length() > 0 && text != "<Label>") {
+			if (points.size() > 0) {
+				g2.drawString(text, (getFrom().getX() + points.get(0).getX()) / 2,
+						(getFrom().getY() + points.get(0).getY()) / 2);
+			} else {
+				if (getFrom() != null && getTo() == null && tempPoint != null) {
+					g2.drawString(text, (getFrom().getX() + tempPoint.x) / 2, (getFrom().getY() + tempPoint.y) / 2);
+				} else if (getFrom() != null && getTo() != null) {
+					g2.drawString(text, (getFrom().getX() + getTo().getX()) / 2, (getFrom().getY() + getTo().getY()) / 2);
+				}
 			}
 		}
 	}
diff --git a/src/logicsim/XMLCreator.java b/src/logicsim/XMLCreator.java
index ca6f05a..8e2303c 100755
--- a/src/logicsim/XMLCreator.java
+++ b/src/logicsim/XMLCreator.java
@@ -138,13 +138,13 @@ else if (g.mirror == Gate.BOTH_AXES)
 
 		for (Pin c : g.getInputs()) {
 			if ((g instanceof MODIN && c.getProperty(CircuitPart.TEXT) != null)
-					|| (c.getIoType() == Pin.INPUT && c.levelType != Pin.NORMAL)) {
+					|| (c.getIoType() == Pin.INPUT && c.levelType != Pin.NORMAL) || (c.text != "<Label>")) {
 				node.appendChild(createPinNode(doc, c));
 			}
 		}
 		for (Pin c : g.getOutputs()) {
 			if ((g instanceof MODOUT && c.getProperty(CircuitPart.TEXT) != null)
-					|| (c.getIoType() == Pin.INPUT && c.levelType != Pin.NORMAL)) {
+					|| (c.getIoType() == Pin.INPUT && c.levelType != Pin.NORMAL) || (c.text != "<Label>")) {
 				node.appendChild(createPinNode(doc, c));
 			}
 		}

From 9a7ef378c8fe2e2fe98f2496d14cd59eaedd867a Mon Sep 17 00:00:00 2001
From: Matthew Lister <chocolatepatty@hotmail.co.uk>
Date: Thu, 18 Jun 2020 23:29:09 +0100
Subject: [PATCH 2/2] Add files via upload

---
 verilog/z1.v | 15 +++++++++++++++
 verilog/z2.v | 15 +++++++++++++++
 verilog/z3.v | 15 +++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 verilog/z1.v
 create mode 100644 verilog/z2.v
 create mode 100644 verilog/z3.v

diff --git a/verilog/z1.v b/verilog/z1.v
new file mode 100644
index 0000000..05317a5
--- /dev/null
+++ b/verilog/z1.v
@@ -0,0 +1,15 @@
+module z1(
+			input wire awef,
+			input wire gea,
+			output wire eag);
+
+
+
+	wire pin;
+
+
+	nor (pin, awef, gea);
+	and (eag, pin, null);
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/z2.v b/verilog/z2.v
new file mode 100644
index 0000000..121402b
--- /dev/null
+++ b/verilog/z2.v
@@ -0,0 +1,15 @@
+module z2(
+			input wire awef,
+			input wire gea,
+			output wire eag);
+
+
+
+	wire pin;
+
+
+	nor (pin, awef, gea);
+	and (eag, pin, null);
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/z3.v b/verilog/z3.v
new file mode 100644
index 0000000..18e6406
--- /dev/null
+++ b/verilog/z3.v
@@ -0,0 +1,15 @@
+module z3(
+			input wire awef,
+			input wire gea,
+			output wire eag);
+
+
+
+	wire pin;
+
+
+	nor (pin, awef, gea);
+	and (eag, pin, null);
+
+
+endmodule
\ No newline at end of file