sw_pe_array_sw_extend.v

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module sw_pe_array_sw_extend (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        qs_baddr_V,
        qs_V_address0,
        qs_V_ce0,
        qs_V_q0,
        ts_baddr_V,
        qlen,
        tlen_V,
        o_ins,
        e_ins,
        o_del,
        e_del,
        w_in,
        h0,
        regScore_read,
        max_ins,
        max_del,
        qle_ret_read,
        tle_ret_read,
        gtle_ret_read,
        gscore_ret_read,
        maxoff_ret_read,
        ap_return_0,
        ap_return_1,
        ap_return_2,
        ap_return_3,
        ap_return_4,
        ap_return_5,
        ap_return_6
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 9'b1;
parameter    ap_ST_st2_fsm_1 = 9'b10;
parameter    ap_ST_st3_fsm_2 = 9'b100;
parameter    ap_ST_st4_fsm_3 = 9'b1000;
parameter    ap_ST_st5_fsm_4 = 9'b10000;
parameter    ap_ST_pp0_stg0_fsm_5 = 9'b100000;
parameter    ap_ST_st11_fsm_6 = 9'b1000000;
parameter    ap_ST_st12_fsm_7 = 9'b10000000;
parameter    ap_ST_st13_fsm_8 = 9'b100000000;
parameter    ap_true = 1'b1;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv1_0 = 1'b0;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv32_8 = 32'b1000;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv12_FFF = 12'b111111111111;
parameter    ap_const_lv11_0 = 11'b00000000000;
parameter    ap_const_lv8_0 = 8'b00000000;
parameter    ap_const_lv8_1 = 8'b1;
parameter    ap_const_lv8_FF = 8'b11111111;
parameter    ap_const_lv12_0 = 12'b000000000000;
parameter    ap_const_lv7_0 = 7'b0000000;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv9_1 = 9'b1;
parameter    ap_const_lv11_1 = 11'b1;
parameter    ap_const_lv32_F = 32'b1111;
parameter    ap_const_lv8_FC = 8'b11111100;
parameter    ap_const_lv9_2 = 9'b10;
parameter    ap_const_lv10_0 = 10'b0000000000;
parameter    ap_const_lv13_0 = 13'b0000000000000;
parameter    ap_const_lv8_2 = 8'b10;
parameter    ap_const_lv13_1 = 13'b1;
parameter    ap_const_lv16_0 = 16'b0000000000000000;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [8:0] qs_baddr_V;
output  [10:0] qs_V_address0;
output   qs_V_ce0;
input  [3:0] qs_V_q0;
input  [10:0] ts_baddr_V;
input  [7:0] qlen;
input  [10:0] tlen_V;
input  [7:0] o_ins;
input  [7:0] e_ins;
input  [7:0] o_del;
input  [7:0] e_del;
input  [7:0] w_in;
input  [7:0] h0;
input  [15:0] regScore_read;
input  [15:0] max_ins;
input  [15:0] max_del;
input  [15:0] qle_ret_read;
input  [15:0] tle_ret_read;
input  [15:0] gtle_ret_read;
input  [15:0] gscore_ret_read;
input  [15:0] maxoff_ret_read;
output  [15:0] ap_return_0;
output  [15:0] ap_return_1;
output  [15:0] ap_return_2;
output  [15:0] ap_return_3;
output  [15:0] ap_return_4;
output  [15:0] ap_return_5;
output  [15:0] ap_return_6;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg[10:0] qs_V_address0;
reg qs_V_ce0;
reg[15:0] ap_return_0;
reg[15:0] ap_return_1;
reg[15:0] ap_return_2;
reg[15:0] ap_return_3;
reg[15:0] ap_return_4;
reg[15:0] ap_return_5;
reg[15:0] ap_return_6;
(* fsm_encoding = "none" *) reg   [8:0] ap_CS_fsm = 9'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_27;
reg   [7:0] mj_reg_499;
reg   [7:0] ap_reg_ppstg_mj_reg_499_pp0_it1;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_5;
reg    ap_sig_bdd_71;
reg    ap_reg_ppiten_pp0_it0 = 1'b0;
reg    ap_reg_ppiten_pp0_it1 = 1'b0;
reg    ap_reg_ppiten_pp0_it2 = 1'b0;
reg    ap_reg_ppiten_pp0_it3 = 1'b0;
reg    ap_reg_ppiten_pp0_it4 = 1'b0;
reg   [7:0] ap_reg_ppstg_mj_reg_499_pp0_it2;
reg   [7:0] ap_reg_ppstg_mj_reg_499_pp0_it3;
reg   [7:0] backw_tmp_reg_509;
reg   [7:0] backw_reg_reg_521;
reg   [7:0] forw_update_reg_533;
reg   [7:0] forw_tmp_reg_545;
reg   [7:0] h_reg_557;
reg   [7:0] f_reg_569;
reg   [7:0] h1_reg_reg_581;
reg   [7:0] max_1_reg_591;
reg   [7:0] max_j_1_reg_603;
wire   [7:0] oe_ins_fu_658_p2;
reg   [7:0] oe_ins_reg_2001;
wire   [7:0] tmp_123_fu_664_p1;
reg   [7:0] tmp_123_reg_2006;
wire   [7:0] tmp_124_fu_668_p1;
reg   [7:0] tmp_124_reg_2011;
wire   [7:0] tmp_eme_1_cast_fu_696_p1;
reg   [7:0] tmp_eme_1_cast_reg_2016;
wire   [7:0] h1_init_val_fu_700_p2;
reg   [7:0] h1_init_val_reg_2021;
wire   [9:0] lhs_V_2_cast_fu_706_p1;
reg   [9:0] lhs_V_2_cast_reg_2026;
wire   [7:0] sum_fu_710_p2;
reg   [7:0] sum_reg_2031;
wire   [1:0] k_V_fu_756_p2;
reg   [1:0] k_V_reg_2039;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_157;
wire   [9:0] prev_V_fu_762_p1;
reg   [9:0] prev_V_reg_2044;
wire   [0:0] tmp_7_fu_750_p2;
wire   [7:0] aw_tmp_fu_770_p2;
reg   [7:0] aw_tmp_reg_2049;
wire   [7:0] aw_tmp_2_fu_784_p3;
reg   [7:0] aw_tmp_2_reg_2056;
wire   [0:0] tmp_14_fu_795_p2;
reg   [0:0] tmp_14_reg_2061;
wire   [7:0] aw1_fu_846_p3;
reg   [7:0] aw1_reg_2066;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_bdd_179;
wire  signed [12:0] rhs_V_fu_851_p1;
reg  signed [12:0] rhs_V_reg_2072;
wire  signed [12:0] tmp_cast_fu_865_p1;
reg  signed [12:0] tmp_cast_reg_2077;
wire   [0:0] tmp_16_fu_869_p2;
reg   [0:0] tmp_16_reg_2082;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_bdd_192;
wire   [10:0] i_V_fu_874_p2;
reg   [10:0] i_V_reg_2086;
wire   [7:0] h1_init_val_2_fu_890_p2;
reg   [7:0] h1_init_val_2_reg_2096;
wire   [6:0] p_s_fu_907_p3;
reg   [6:0] p_s_reg_2101;
wire   [12:0] lhs_V_fu_919_p1;
reg   [12:0] lhs_V_reg_2106;
wire   [7:0] j_fu_943_p3;
reg   [7:0] j_reg_2111;
wire   [7:0] end_1_fu_977_p3;
reg   [7:0] end_1_reg_2118;
wire   [11:0] max_ie_V_cast_fu_985_p1;
reg   [11:0] max_ie_V_cast_reg_2124;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_bdd_218;
wire   [7:0] p_cast_fu_989_p1;
wire   [7:0] qlen_end_1_fu_996_p3;
reg   [7:0] qlen_end_1_reg_2135;
wire   [7:0] beg_1_fu_1007_p3;
reg   [7:0] beg_1_reg_2141;
wire   [0:0] tmp_31_fu_1014_p2;
reg   [0:0] tmp_31_reg_2147;
wire   [3:0] tmp_65_cast_fu_1024_p1;
reg   [3:0] tmp_65_cast_reg_2156;
wire   [4:0] p_shl_fu_1028_p3;
reg   [4:0] p_shl_reg_2161;
wire   [0:0] tmp_32_fu_1036_p2;
reg   [0:0] tmp_32_reg_2166;
reg   [0:0] ap_reg_ppstg_tmp_32_reg_2166_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_32_reg_2166_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_32_reg_2166_pp0_it3;
reg   [7:0] eh_arr_addr_reg_2175;
reg   [7:0] ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it1;
reg   [7:0] ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it2;
reg   [7:0] ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it3;
wire   [6:0] tmp_eme_5_fu_1087_p3;
reg   [6:0] tmp_eme_5_reg_2181;
wire   [0:0] or_cond_fu_1117_p2;
reg   [0:0] or_cond_reg_2186;
wire   [7:0] tmp_eme_4_fu_1130_p3;
reg   [7:0] tmp_eme_4_reg_2191;
wire   [7:0] newSel2_fu_1138_p3;
reg   [7:0] newSel2_reg_2196;
wire   [7:0] j_1_fu_1145_p2;
reg   [7:0] j_1_reg_2201;
wire   [7:0] newSel4_fu_1175_p3;
reg   [7:0] newSel4_reg_2206;
wire   [7:0] e_fu_1181_p3;
reg   [7:0] e_reg_2211;
wire   [4:0] tmp_69_fu_1205_p2;
reg   [4:0] tmp_69_reg_2218;
wire   [7:0] h_4_fu_1275_p3;
reg   [7:0] h_4_reg_2223;
wire   [7:0] e_1_fu_1282_p2;
reg   [7:0] e_1_reg_2229;
reg   [7:0] ap_reg_ppstg_e_1_reg_2229_pp0_it3;
wire   [7:0] m_fu_1291_p3;
reg   [7:0] m_reg_2235;
wire   [0:0] grp_fu_640_p2;
reg   [0:0] tmp_55_reg_2240;
wire   [7:0] backw_reg_0_backw_tmp_1_fu_1312_p3;
reg   [7:0] backw_reg_0_backw_tmp_1_reg_2246;
wire   [7:0] m_0_s_fu_1320_p3;
reg   [7:0] m_0_s_reg_2251;
wire   [7:0] mj_0_s_fu_1328_p3;
reg   [7:0] mj_0_s_reg_2256;
wire  signed [8:0] tmp_59_fu_1340_p2;
reg  signed [8:0] tmp_59_reg_2261;
wire   [6:0] t_1_fu_1361_p3;
reg   [6:0] t_1_reg_2266;
wire   [6:0] t_3_fu_1384_p3;
reg   [6:0] t_3_reg_2271;
wire   [7:0] phitmp_fu_1392_p2;
reg   [7:0] phitmp_reg_2276;
wire   [7:0] forw_update_3_fu_1449_p3;
wire   [7:0] forw_tmp_3_fu_1465_p3;
wire   [7:0] f_2_fu_1502_p3;
wire   [7:0] forw_tmp_5_fu_1589_p3;
reg   [7:0] forw_tmp_5_reg_2296;
reg    ap_sig_cseq_ST_st11_fsm_6;
reg    ap_sig_bdd_319;
wire   [11:0] p_0414_3_fu_1626_p3;
reg   [11:0] p_0414_3_reg_2301;
wire   [11:0] p_0408_3_fu_1634_p3;
reg   [11:0] p_0408_3_reg_2307;
wire   [0:0] tmp_73_fu_1648_p2;
reg   [0:0] tmp_73_reg_2316;
wire   [0:0] tmp_51_fu_1642_p2;
wire   [9:0] abs_mj_m_i_V_fu_1679_p3;
reg   [9:0] abs_mj_m_i_V_reg_2322;
wire  signed [15:0] maxoff_ret_fu_1712_p1;
reg  signed [15:0] maxoff_ret_reg_2327;
wire  signed [15:0] tmp_66_fu_1716_p1;
reg  signed [15:0] tmp_66_reg_2332;
wire   [0:0] phitmp1_fu_1777_p2;
reg   [0:0] phitmp1_reg_2337;
wire   [7:0] beg_2_fu_1820_p2;
reg    ap_sig_cseq_ST_st12_fsm_7;
reg    ap_sig_bdd_352;
wire   [7:0] end_3_fu_1831_p2;
wire  signed [15:0] qle_ret_cast_fu_1857_p1;
reg    ap_sig_cseq_ST_st13_fsm_8;
reg    ap_sig_bdd_363;
wire  signed [15:0] tle_ret_cast_fu_1871_p1;
wire  signed [15:0] gtle_ret_cast_fu_1885_p1;
wire  signed [15:0] gscore_ret_fu_1889_p1;
wire   [7:0] eh_arr_address0;
reg    eh_arr_ce0;
wire   [15:0] eh_arr_q0;
reg   [7:0] eh_arr_address1;
reg    eh_arr_ce1;
reg    eh_arr_we1;
reg   [15:0] eh_arr_d1;
wire   [15:0] eh_arr_q1;
reg   [15:0] tle_ret_write_assign_reg_315;
reg   [15:0] gtle_ret_write_assign_reg_324;
reg   [15:0] qle_ret_write_assign_reg_333;
reg   [15:0] gscore_ret_write_assign_reg_342;
reg   [15:0] maxoff_ret_write_assign_reg_351;
reg   [15:0] val_assign_reg_360;
reg   [1:0] p_1_reg_369;
reg   [11:0] p_3_reg_380;
reg   [11:0] p_5_reg_392;
reg   [0:0] isBreak_reg_404;
reg   [7:0] aw_tmp_s_reg_415;
reg   [10:0] max_ie_V_reg_426;
reg   [11:0] p_0414_1_reg_438;
reg   [11:0] p_0408_1_reg_449;
reg   [7:0] beg_reg_460;
reg   [7:0] end_reg_471;
reg   [7:0] tmp_eme3_reg_480;
reg   [7:0] h1_init_val1_reg_490;
reg   [7:0] mj_phi_fu_502_p4;
reg   [7:0] backw_tmp_phi_fu_513_p4;
reg   [7:0] backw_reg_phi_fu_525_p4;
reg   [7:0] h_phi_fu_561_p4;
reg   [7:0] f_phi_fu_573_p4;
reg   [7:0] h1_reg_phi_fu_584_p4;
reg   [7:0] max_1_phi_fu_595_p4;
reg   [7:0] max_j_1_phi_fu_607_p4;
reg   [11:0] p_0414_4_reg_615;
reg   [11:0] p_0408_4_reg_627;
wire   [63:0] tmp_18_fu_885_p1;
wire   [63:0] tmp_34_fu_1050_p1;
wire   [63:0] tmp_35_fu_1055_p1;
wire   [63:0] tmp_36_fu_1519_p1;
reg   [7:0] max_fu_146;
wire   [7:0] max_2_fu_1694_p3;
reg   [7:0] max_j_fu_150;
wire   [7:0] i_op_assign_3_fu_1807_p3;
reg   [11:0] max_off_V_3_fu_154;
wire   [11:0] max_off_V_2_fu_1800_p3;
reg   [11:0] p_2_fu_158;
wire   [11:0] p_0420_2_fu_1687_p3;
wire   [15:0] eh_h_addr68_part_set_fu_1510_p3;
wire   [15:0] eh_e_addr_11516_part_set_fu_1523_p3;
reg   [7:0] grp_fu_640_p0;
wire   [7:0] tmp_eme_fu_672_p2;
wire   [0:0] tmp_6_fu_682_p2;
wire   [6:0] tmp_125_fu_678_p1;
wire   [6:0] tmp_eme_1_fu_688_p3;
wire   [0:0] tmp_126_fu_736_p3;
wire   [0:0] rev_fu_744_p2;
wire   [7:0] tmp_8_cast_fu_766_p1;
wire  signed [15:0] tmp_11_cast_fu_775_p1;
wire   [0:0] tmp_12_fu_779_p2;
wire  signed [15:0] tmp_13_cast_fu_791_p1;
wire  signed [15:0] w_ret_write_assign_fu_800_p1;
wire  signed [8:0] rhs_V_cast_fu_855_p1;
wire  signed [8:0] tmp_fu_859_p2;
wire   [10:0] ts_baddr_t_V_fu_880_p2;
wire   [0:0] tmp_129_fu_899_p3;
wire   [6:0] tmp_128_fu_895_p1;
wire   [12:0] tmp_20_cast_fu_915_p1;
wire  signed [12:0] r_V_fu_923_p2;
wire   [7:0] tmp_130_fu_934_p1;
wire   [0:0] tmp_22_fu_928_p2;
wire   [7:0] tmp_24_fu_938_p2;
wire   [12:0] tmp_25_cast_fu_951_p1;
wire  signed [12:0] r_V_2_fu_955_p2;
wire   [7:0] tmp33_fu_966_p2;
wire   [0:0] tmp_27_fu_960_p2;
wire   [7:0] end_2_fu_972_p2;
wire   [0:0] tmp_29_fu_992_p2;
wire   [0:0] tmp_30_fu_1002_p2;
wire   [2:0] tmp_131_fu_1020_p1;
wire   [9:0] rhs_V_1_cast_fu_1041_p1;
wire   [9:0] r_V_3_fu_1045_p2;
wire   [7:0] tmp_eme_2_fu_1072_p2;
wire   [0:0] tmp_47_fu_1081_p2;
wire   [6:0] tmp_133_fu_1077_p1;
wire   [0:0] tmp_39_fu_1060_p2;
wire   [0:0] tmp_45_fu_1066_p2;
wire   [0:0] sel_tmp4_fu_1100_p2;
wire   [0:0] tmp34_fu_1106_p2;
wire   [0:0] sel_tmp6_fu_1112_p2;
wire   [0:0] sel_tmp2_fu_1095_p2;
wire   [7:0] newSel_fu_1123_p3;
wire   [7:0] tmp_eme_5_cast_fu_1165_p1;
wire   [7:0] h_6_fu_1151_p1;
wire   [7:0] newSel3_fu_1168_p3;
wire   [7:0] e_4_fu_1155_p4;
wire   [2:0] tmp_134_fu_1188_p1;
wire   [3:0] tmp_68_cast_fu_1192_p1;
wire   [3:0] tmp41_fu_1196_p2;
wire   [4:0] tmp49_cast_fu_1201_p1;
wire   [7:0] tmp_48_fu_1210_p1;
wire  signed [7:0] tmp_48_fu_1210_p2;
wire  signed [7:0] tmp_48_fu_1210_p3;
wire  signed [7:0] tmp_48_fu_1210_p4;
wire  signed [7:0] tmp_48_fu_1210_p5;
wire  signed [7:0] tmp_48_fu_1210_p6;
wire   [7:0] tmp_48_fu_1210_p7;
wire  signed [7:0] tmp_48_fu_1210_p8;
wire  signed [7:0] tmp_48_fu_1210_p9;
wire  signed [7:0] tmp_48_fu_1210_p10;
wire  signed [7:0] tmp_48_fu_1210_p11;
wire  signed [7:0] tmp_48_fu_1210_p12;
wire   [7:0] tmp_48_fu_1210_p13;
wire  signed [7:0] tmp_48_fu_1210_p14;
wire  signed [7:0] tmp_48_fu_1210_p15;
wire  signed [7:0] tmp_48_fu_1210_p16;
wire  signed [7:0] tmp_48_fu_1210_p17;
wire  signed [7:0] tmp_48_fu_1210_p18;
wire   [7:0] tmp_48_fu_1210_p19;
wire  signed [7:0] tmp_48_fu_1210_p20;
wire  signed [7:0] tmp_48_fu_1210_p21;
wire  signed [7:0] tmp_48_fu_1210_p22;
wire  signed [7:0] tmp_48_fu_1210_p23;
wire  signed [7:0] tmp_48_fu_1210_p24;
wire  signed [7:0] tmp_48_fu_1210_p25;
wire   [4:0] tmp_48_fu_1210_p26;
wire   [7:0] tmp_48_fu_1210_p27;
wire   [7:0] h_3_fu_1265_p2;
wire   [0:0] tmp_52_fu_1270_p2;
wire   [0:0] tmp_54_fu_1286_p2;
wire   [0:0] tmp_56_fu_1306_p2;
wire   [7:0] backw_reg_2_fu_1298_p3;
wire  signed [8:0] tmp_58_cast_fu_1336_p1;
wire   [7:0] t_fu_1346_p2;
wire   [0:0] tmp_s_fu_1355_p2;
wire   [6:0] tmp_135_fu_1351_p1;
wire   [7:0] t_2_fu_1369_p2;
wire   [0:0] tmp_86_fu_1378_p2;
wire   [6:0] tmp_136_fu_1374_p1;
wire   [8:0] tmp_57_cast_fu_1398_p1;
wire   [7:0] forw_tmp_6_fu_1413_p2;
wire   [0:0] tmp_60_fu_1402_p2;
wire   [0:0] tmp_74_fu_1407_p2;
wire   [0:0] sel_tmp1_fu_1429_p2;
wire   [0:0] sel_tmp3_fu_1435_p2;
wire   [7:0] forw_update_1_fu_1419_p1;
wire   [7:0] sel_tmp5_fu_1441_p3;
wire   [7:0] forw_tmp_1_fu_1422_p3;
wire   [7:0] sel_tmp7_fu_1457_p3;
wire   [7:0] t_1_cast_fu_1473_p1;
wire   [0:0] tmp_85_fu_1476_p2;
wire   [7:0] f_1_fu_1491_p2;
wire   [7:0] t_3_cast_fu_1488_p1;
wire   [0:0] tmp_87_fu_1496_p2;
wire   [7:0] e_2_fu_1481_p3;
wire   [0:0] tmp_37_fu_1532_p2;
wire  signed [8:0] tmp_41_cast_fu_1547_p1;
wire   [8:0] tmp_40_cast_fu_1544_p1;
wire  signed [8:0] tmp_42_fu_1551_p2;
wire   [0:0] tmp_43_fu_1557_p2;
wire   [0:0] tmp_44_fu_1563_p2;
wire   [0:0] or_cond1_fu_1569_p2;
wire   [7:0] forw_tmp_2_fu_1575_p2;
wire   [0:0] or_cond_80_fu_1538_p2;
wire   [7:0] forw_tmp_4_fu_1581_p3;
wire  signed [11:0] gscore_V_fu_1601_p1;
wire   [0:0] tmp_50_fu_1605_p2;
wire   [0:0] tmp_46_fu_1597_p2;
wire   [11:0] p_0414_1_s_fu_1611_p3;
wire   [11:0] p_0408_1_s_fu_1618_p3;
wire  signed [12:0] lhs_V_1_fu_1654_p1;
wire  signed [12:0] r_V_4_fu_1658_p2;
wire   [9:0] tmp_137_fu_1663_p1;
wire   [0:0] abscond_fu_1673_p2;
wire   [9:0] neg_fu_1667_p2;
wire   [6:0] tmp_88_fu_1724_p4;
wire   [5:0] tmp_89_fu_1737_p4;
wire  signed [7:0] tmp_75_cast_fu_1733_p1;
wire  signed [7:0] tmp_76_cast_fu_1746_p1;
wire  signed [7:0] op2_assign_fu_1750_p2;
wire  signed [9:0] tmp_70_cast_fu_1720_p1;
wire  signed [11:0] op2_assign_cast_fu_1756_p1;
wire   [0:0] slt_fu_1765_p2;
wire   [0:0] rev1_fu_1771_p2;
wire   [0:0] notlhs_fu_1760_p2;
wire  signed [11:0] max_off_V_fu_1783_p1;
wire   [0:0] tmp_83_fu_1786_p2;
wire   [11:0] max_off_V_1_fu_1792_p3;
wire   [7:0] tmp_84_fu_1814_p2;
wire   [7:0] tmp42_fu_1826_p2;
wire  signed [8:0] tmp_61_cast_fu_1847_p1;
wire  signed [8:0] qle_ret_fu_1851_p2;
wire  signed [12:0] tmp_62_cast_fu_1861_p1;
wire  signed [12:0] tle_ret_fu_1865_p2;
wire  signed [12:0] tmp_64_cast_fu_1875_p1;
wire  signed [12:0] gtle_ret_fu_1879_p2;
reg   [15:0] ap_return_0_preg = 16'b0000000000000000;
reg   [15:0] ap_return_1_preg = 16'b0000000000000000;
reg   [15:0] ap_return_2_preg = 16'b0000000000000000;
reg   [15:0] ap_return_3_preg = 16'b0000000000000000;
reg   [15:0] ap_return_4_preg = 16'b0000000000000000;
reg   [15:0] ap_return_5_preg = 16'b0000000000000000;
reg   [15:0] ap_return_6_preg = 16'b0000000000000000;
reg   [8:0] ap_NS_fsm;


sw_pe_array_sw_extend_eh_arr #(
    .DataWidth( 16 ),
    .AddressRange( 256 ),
    .AddressWidth( 8 ))
eh_arr_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( eh_arr_address0 ),
    .ce0( eh_arr_ce0 ),
    .q0( eh_arr_q0 ),
    .address1( eh_arr_address1 ),
    .ce1( eh_arr_ce1 ),
    .we1( eh_arr_we1 ),
    .d1( eh_arr_d1 ),
    .q1( eh_arr_q1 )
);

sw_pe_array_mux_25to1_sel5_8_1 #(
    .ID( 1 ),
    .NUM_STAGE( 1 ),
    .din1_WIDTH( 8 ),
    .din2_WIDTH( 8 ),
    .din3_WIDTH( 8 ),
    .din4_WIDTH( 8 ),
    .din5_WIDTH( 8 ),
    .din6_WIDTH( 8 ),
    .din7_WIDTH( 8 ),
    .din8_WIDTH( 8 ),
    .din9_WIDTH( 8 ),
    .din10_WIDTH( 8 ),
    .din11_WIDTH( 8 ),
    .din12_WIDTH( 8 ),
    .din13_WIDTH( 8 ),
    .din14_WIDTH( 8 ),
    .din15_WIDTH( 8 ),
    .din16_WIDTH( 8 ),
    .din17_WIDTH( 8 ),
    .din18_WIDTH( 8 ),
    .din19_WIDTH( 8 ),
    .din20_WIDTH( 8 ),
    .din21_WIDTH( 8 ),
    .din22_WIDTH( 8 ),
    .din23_WIDTH( 8 ),
    .din24_WIDTH( 8 ),
    .din25_WIDTH( 8 ),
    .din26_WIDTH( 5 ),
    .dout_WIDTH( 8 ))
sw_pe_array_mux_25to1_sel5_8_1_U41(
    .din1( tmp_48_fu_1210_p1 ),
    .din2( tmp_48_fu_1210_p2 ),
    .din3( tmp_48_fu_1210_p3 ),
    .din4( tmp_48_fu_1210_p4 ),
    .din5( tmp_48_fu_1210_p5 ),
    .din6( tmp_48_fu_1210_p6 ),
    .din7( tmp_48_fu_1210_p7 ),
    .din8( tmp_48_fu_1210_p8 ),
    .din9( tmp_48_fu_1210_p9 ),
    .din10( tmp_48_fu_1210_p10 ),
    .din11( tmp_48_fu_1210_p11 ),
    .din12( tmp_48_fu_1210_p12 ),
    .din13( tmp_48_fu_1210_p13 ),
    .din14( tmp_48_fu_1210_p14 ),
    .din15( tmp_48_fu_1210_p15 ),
    .din16( tmp_48_fu_1210_p16 ),
    .din17( tmp_48_fu_1210_p17 ),
    .din18( tmp_48_fu_1210_p18 ),
    .din19( tmp_48_fu_1210_p19 ),
    .din20( tmp_48_fu_1210_p20 ),
    .din21( tmp_48_fu_1210_p21 ),
    .din22( tmp_48_fu_1210_p22 ),
    .din23( tmp_48_fu_1210_p23 ),
    .din24( tmp_48_fu_1210_p24 ),
    .din25( tmp_48_fu_1210_p25 ),
    .din26( tmp_48_fu_1210_p26 ),
    .dout( tmp_48_fu_1210_p27 )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_lv1_0 == tmp_32_fu_1036_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & ~(ap_const_lv1_0 == tmp_32_fu_1036_p2))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_lv1_0 == tmp_32_fu_1036_p2)))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
    end else begin
        ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
    end
end

/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
    end else begin
        ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
    end
end

/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
    end else begin
        ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
    end
end

/// ap_return_0_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_0_preg
    if (ap_rst == 1'b1) begin
        ap_return_0_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_0_preg <= val_assign_reg_360;
        end
    end
end

/// ap_return_1_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_1_preg
    if (ap_rst == 1'b1) begin
        ap_return_1_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_1_preg <= w_ret_write_assign_fu_800_p1;
        end
    end
end

/// ap_return_2_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_2_preg
    if (ap_rst == 1'b1) begin
        ap_return_2_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_2_preg <= qle_ret_write_assign_reg_333;
        end
    end
end

/// ap_return_3_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_3_preg
    if (ap_rst == 1'b1) begin
        ap_return_3_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_3_preg <= tle_ret_write_assign_reg_315;
        end
    end
end

/// ap_return_4_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_4_preg
    if (ap_rst == 1'b1) begin
        ap_return_4_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_4_preg <= gtle_ret_write_assign_reg_324;
        end
    end
end

/// ap_return_5_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_5_preg
    if (ap_rst == 1'b1) begin
        ap_return_5_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_5_preg <= gscore_ret_write_assign_reg_342;
        end
    end
end

/// ap_return_6_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_6_preg
    if (ap_rst == 1'b1) begin
        ap_return_6_preg <= ap_const_lv16_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
            ap_return_6_preg <= maxoff_ret_write_assign_reg_351;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        backw_reg_reg_521 <= backw_reg_0_backw_tmp_1_reg_2246;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        backw_reg_reg_521 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        backw_tmp_reg_509 <= phitmp_reg_2276;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        backw_tmp_reg_509 <= ap_const_lv8_1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        beg_reg_460 <= beg_2_fu_1820_p2;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        beg_reg_460 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        end_reg_471 <= end_3_fu_1831_p2;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        end_reg_471 <= qlen;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        f_reg_569 <= f_2_fu_1502_p3;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        f_reg_569 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        forw_tmp_reg_545 <= forw_tmp_3_fu_1465_p3;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        forw_tmp_reg_545 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        forw_update_reg_533 <= forw_update_3_fu_1449_p3;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        forw_update_reg_533 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        gscore_ret_write_assign_reg_342 <= gscore_ret_fu_1889_p1;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        gscore_ret_write_assign_reg_342 <= gscore_ret_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        gtle_ret_write_assign_reg_324 <= gtle_ret_cast_fu_1885_p1;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        gtle_ret_write_assign_reg_324 <= gtle_ret_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        h1_init_val1_reg_490 <= h1_init_val_2_reg_2096;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        h1_init_val1_reg_490 <= h1_init_val_reg_2021;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        h1_reg_reg_581 <= m_reg_2235;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        h1_reg_reg_581 <= p_cast_fu_989_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_const_lv1_0 == tmp_32_reg_2166))) begin
        h_reg_557 <= tmp_eme_4_reg_2191;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        h_reg_557 <= tmp_eme3_reg_480;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        isBreak_reg_404 <= phitmp1_reg_2337;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        isBreak_reg_404 <= ap_const_lv1_1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        max_1_reg_591 <= m_0_s_reg_2251;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        max_1_reg_591 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082) & (ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
        max_fu_146 <= max_2_fu_1694_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        max_fu_146 <= h0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        max_ie_V_reg_426 <= i_V_reg_2086;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        max_ie_V_reg_426 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        max_j_1_reg_603 <= mj_0_s_reg_2256;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        max_j_1_reg_603 <= ap_const_lv8_FF;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        max_j_fu_150 <= i_op_assign_3_fu_1807_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        max_j_fu_150 <= ap_const_lv8_FF;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        max_off_V_3_fu_154 <= max_off_V_2_fu_1800_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        max_off_V_3_fu_154 <= ap_const_lv12_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        maxoff_ret_write_assign_reg_351 <= maxoff_ret_reg_2327;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        maxoff_ret_write_assign_reg_351 <= maxoff_ret_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_const_lv1_0 == tmp_32_reg_2166))) begin
        mj_reg_499 <= j_1_reg_2201;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        mj_reg_499 <= j_reg_2111;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        p_0408_1_reg_449 <= p_0408_3_reg_2307;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        p_0408_1_reg_449 <= p_5_reg_392;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082) & ~(ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
        p_0408_4_reg_627 <= p_0408_3_fu_1634_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_16_fu_869_p2))) begin
        p_0408_4_reg_627 <= p_0408_1_reg_449;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        p_0414_1_reg_438 <= p_0414_3_reg_2301;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        p_0414_1_reg_438 <= p_3_reg_380;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082) & ~(ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
        p_0414_4_reg_615 <= p_0414_3_fu_1626_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_16_fu_869_p2))) begin
        p_0414_4_reg_615 <= p_0414_1_reg_438;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        p_1_reg_369 <= k_V_reg_2039;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        p_1_reg_369 <= ap_const_lv2_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082) & (ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
        p_2_fu_158 <= p_0420_2_fu_1687_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        p_2_fu_158 <= ap_const_lv12_FFF;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        p_3_reg_380 <= p_0414_4_reg_615;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        p_3_reg_380 <= ap_const_lv12_FFF;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        p_5_reg_392 <= p_0408_4_reg_627;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        p_5_reg_392 <= ap_const_lv12_FFF;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        qle_ret_write_assign_reg_333 <= qle_ret_cast_fu_1857_p1;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        qle_ret_write_assign_reg_333 <= qle_ret_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        tle_ret_write_assign_reg_315 <= tle_ret_cast_fu_1871_p1;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        tle_ret_write_assign_reg_315 <= tle_ret_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7)) begin
        tmp_eme3_reg_480 <= h_reg_557;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        tmp_eme3_reg_480 <= tmp_eme_1_cast_reg_2016;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        val_assign_reg_360 <= tmp_66_reg_2332;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        val_assign_reg_360 <= regScore_read;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082) & (ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
        abs_mj_m_i_V_reg_2322 <= abs_mj_m_i_V_fu_1679_p3;
        tmp_73_reg_2316 <= tmp_73_fu_1648_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_true == ap_true)) begin
        ap_reg_ppstg_e_1_reg_2229_pp0_it3 <= e_1_reg_2229;
        ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it2 <= ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it1;
        ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it3 <= ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it2;
        ap_reg_ppstg_mj_reg_499_pp0_it2 <= ap_reg_ppstg_mj_reg_499_pp0_it1;
        ap_reg_ppstg_mj_reg_499_pp0_it3 <= ap_reg_ppstg_mj_reg_499_pp0_it2;
        ap_reg_ppstg_tmp_32_reg_2166_pp0_it2 <= ap_reg_ppstg_tmp_32_reg_2166_pp0_it1;
        ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 <= ap_reg_ppstg_tmp_32_reg_2166_pp0_it2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5)) begin
        ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it1 <= eh_arr_addr_reg_2175;
        ap_reg_ppstg_mj_reg_499_pp0_it1 <= mj_reg_499;
        ap_reg_ppstg_tmp_32_reg_2166_pp0_it1 <= tmp_32_reg_2166;
        tmp_32_reg_2166 <= tmp_32_fu_1036_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        aw1_reg_2066 <= aw1_fu_846_p3;
        rhs_V_reg_2072 <= rhs_V_fu_851_p1;
        tmp_cast_reg_2077 <= tmp_cast_fu_865_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        aw_tmp_2_reg_2056 <= aw_tmp_2_fu_784_p3;
        aw_tmp_reg_2049 <= aw_tmp_fu_770_p2;
        prev_V_reg_2044 <= prev_V_fu_762_p1;
        tmp_14_reg_2061 <= tmp_14_fu_795_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_8)) begin
        aw_tmp_s_reg_415 <= aw_tmp_reg_2049;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it2))) begin
        backw_reg_0_backw_tmp_1_reg_2246 <= backw_reg_0_backw_tmp_1_fu_1312_p3;
        m_0_s_reg_2251 <= m_0_s_fu_1320_p3;
        m_reg_2235 <= m_fu_1291_p3;
        mj_0_s_reg_2256 <= mj_0_s_fu_1328_p3;
        phitmp_reg_2276 <= phitmp_fu_1392_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        beg_1_reg_2141 <= beg_1_fu_1007_p3;
        max_ie_V_cast_reg_2124[10 : 0] <= max_ie_V_cast_fu_985_p1[10 : 0];
        p_shl_reg_2161[4 : 2] <= p_shl_fu_1028_p3[4 : 2];
        qlen_end_1_reg_2135 <= qlen_end_1_fu_996_p3;
        tmp_31_reg_2147 <= tmp_31_fu_1014_p2;
        tmp_65_cast_reg_2156[2 : 0] <= tmp_65_cast_fu_1024_p1[2 : 0];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it1)) begin
        e_1_reg_2229 <= e_1_fu_1282_p2;
        h_4_reg_2223 <= h_4_fu_1275_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & ~(ap_const_lv1_0 == tmp_32_reg_2166))) begin
        e_reg_2211 <= e_fu_1181_p3;
        newSel4_reg_2206 <= newSel4_fu_1175_p3;
        tmp_69_reg_2218 <= tmp_69_fu_1205_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & ~(ap_const_lv1_0 == tmp_32_fu_1036_p2))) begin
        eh_arr_addr_reg_2175 <= tmp_35_fu_1055_p1;
        newSel2_reg_2196 <= newSel2_fu_1138_p3;
        or_cond_reg_2186 <= or_cond_fu_1117_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_16_fu_869_p2))) begin
        end_1_reg_2118 <= end_1_fu_977_p3;
        h1_init_val_2_reg_2096 <= h1_init_val_2_fu_890_p2;
        j_reg_2111 <= j_fu_943_p3;
        lhs_V_reg_2106[10 : 0] <= lhs_V_fu_919_p1[10 : 0];
        p_s_reg_2101 <= p_s_fu_907_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082))) begin
        forw_tmp_5_reg_2296 <= forw_tmp_5_fu_1589_p3;
        p_0408_3_reg_2307 <= p_0408_3_fu_1634_p3;
        p_0414_3_reg_2301 <= p_0414_3_fu_1626_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
        h1_init_val_reg_2021 <= h1_init_val_fu_700_p2;
        lhs_V_2_cast_reg_2026[8 : 0] <= lhs_V_2_cast_fu_706_p1[8 : 0];
        oe_ins_reg_2001 <= oe_ins_fu_658_p2;
        sum_reg_2031 <= sum_fu_710_p2;
        tmp_123_reg_2006 <= tmp_123_fu_664_p1;
        tmp_124_reg_2011 <= tmp_124_fu_668_p1;
        tmp_eme_1_cast_reg_2016[6 : 0] <= tmp_eme_1_cast_fu_696_p1[6 : 0];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        i_V_reg_2086 <= i_V_fu_874_p2;
        tmp_16_reg_2082 <= tmp_16_fu_869_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == tmp_32_fu_1036_p2))) begin
        j_1_reg_2201 <= j_1_fu_1145_p2;
        tmp_eme_4_reg_2191 <= tmp_eme_4_fu_1130_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        k_V_reg_2039 <= k_V_fu_756_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ((ap_const_lv1_0 == tmp_16_reg_2082) | ~(ap_const_lv1_0 == tmp_51_fu_1642_p2)))) begin
        maxoff_ret_reg_2327 <= maxoff_ret_fu_1712_p1;
        phitmp1_reg_2337 <= phitmp1_fu_1777_p2;
        tmp_66_reg_2332 <= tmp_66_fu_1716_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it2)) begin
        t_1_reg_2266 <= t_1_fu_1361_p3;
        t_3_reg_2271 <= t_3_fu_1384_p3;
        tmp_55_reg_2240 <= grp_fu_640_p2;
        tmp_59_reg_2261 <= tmp_59_fu_1340_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & ~(ap_const_lv1_0 == tmp_32_fu_1036_p2) & ~(ap_const_lv1_0 == tmp_31_reg_2147))) begin
        tmp_eme_5_reg_2181 <= tmp_eme_5_fu_1087_p3;
    end
end

/// ap_done assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2)
begin
    if (((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0)))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_return_0 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or val_assign_reg_360 or ap_return_0_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_0 = val_assign_reg_360;
    end else begin
        ap_return_0 = ap_return_0_preg;
    end
end

/// ap_return_1 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or w_ret_write_assign_fu_800_p1 or ap_return_1_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_1 = w_ret_write_assign_fu_800_p1;
    end else begin
        ap_return_1 = ap_return_1_preg;
    end
end

/// ap_return_2 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or qle_ret_write_assign_reg_333 or ap_return_2_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_2 = qle_ret_write_assign_reg_333;
    end else begin
        ap_return_2 = ap_return_2_preg;
    end
end

/// ap_return_3 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or tle_ret_write_assign_reg_315 or ap_return_3_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_3 = tle_ret_write_assign_reg_315;
    end else begin
        ap_return_3 = ap_return_3_preg;
    end
end

/// ap_return_4 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or gtle_ret_write_assign_reg_324 or ap_return_4_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_4 = gtle_ret_write_assign_reg_324;
    end else begin
        ap_return_4 = ap_return_4_preg;
    end
end

/// ap_return_5 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or gscore_ret_write_assign_reg_342 or ap_return_5_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_5 = gscore_ret_write_assign_reg_342;
    end else begin
        ap_return_5 = ap_return_5_preg;
    end
end

/// ap_return_6 assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_7_fu_750_p2 or maxoff_ret_write_assign_reg_351 or ap_return_6_preg)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_7_fu_750_p2 == ap_const_lv1_0))) begin
        ap_return_6 = maxoff_ret_write_assign_reg_351;
    end else begin
        ap_return_6 = ap_return_6_preg;
    end
end

/// ap_sig_cseq_ST_pp0_stg0_fsm_5 assign process. ///
always @ (ap_sig_bdd_71)
begin
    if (ap_sig_bdd_71) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_5 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_5 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st11_fsm_6 assign process. ///
always @ (ap_sig_bdd_319)
begin
    if (ap_sig_bdd_319) begin
        ap_sig_cseq_ST_st11_fsm_6 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st11_fsm_6 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st12_fsm_7 assign process. ///
always @ (ap_sig_bdd_352)
begin
    if (ap_sig_bdd_352) begin
        ap_sig_cseq_ST_st12_fsm_7 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st12_fsm_7 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st13_fsm_8 assign process. ///
always @ (ap_sig_bdd_363)
begin
    if (ap_sig_bdd_363) begin
        ap_sig_cseq_ST_st13_fsm_8 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st13_fsm_8 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_27)
begin
    if (ap_sig_bdd_27) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_157)
begin
    if (ap_sig_bdd_157) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_179)
begin
    if (ap_sig_bdd_179) begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_192)
begin
    if (ap_sig_bdd_192) begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_218)
begin
    if (ap_sig_bdd_218) begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
    end
end

/// backw_reg_phi_fu_525_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or backw_reg_reg_521 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or backw_reg_0_backw_tmp_1_reg_2246)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        backw_reg_phi_fu_525_p4 = backw_reg_0_backw_tmp_1_reg_2246;
    end else begin
        backw_reg_phi_fu_525_p4 = backw_reg_reg_521;
    end
end

/// backw_tmp_phi_fu_513_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or backw_tmp_reg_509 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or phitmp_reg_2276)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        backw_tmp_phi_fu_513_p4 = phitmp_reg_2276;
    end else begin
        backw_tmp_phi_fu_513_p4 = backw_tmp_reg_509;
    end
end

/// eh_arr_address1 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it3 or ap_sig_cseq_ST_st11_fsm_6 or tmp_36_fu_1519_p1)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6)) begin
        eh_arr_address1 = tmp_36_fu_1519_p1;
    end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it4)) begin
        eh_arr_address1 = ap_reg_ppstg_eh_arr_addr_reg_2175_pp0_it3;
    end else begin
        eh_arr_address1 = 'bx;
    end
end

/// eh_arr_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_5 or ap_reg_ppiten_pp0_it0)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
        eh_arr_ce0 = ap_const_logic_1;
    end else begin
        eh_arr_ce0 = ap_const_logic_0;
    end
end

/// eh_arr_ce1 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or ap_sig_cseq_ST_st11_fsm_6)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) | (ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6))) begin
        eh_arr_ce1 = ap_const_logic_1;
    end else begin
        eh_arr_ce1 = ap_const_logic_0;
    end
end

/// eh_arr_d1 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or ap_sig_cseq_ST_st11_fsm_6 or eh_h_addr68_part_set_fu_1510_p3 or eh_e_addr_11516_part_set_fu_1523_p3)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6)) begin
        eh_arr_d1 = eh_e_addr_11516_part_set_fu_1523_p3;
    end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it4)) begin
        eh_arr_d1 = eh_h_addr68_part_set_fu_1510_p3;
    end else begin
        eh_arr_d1 = 'bx;
    end
end

/// eh_arr_we1 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or tmp_16_reg_2082 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or ap_sig_cseq_ST_st11_fsm_6)
begin
    if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6) & ~(ap_const_lv1_0 == tmp_16_reg_2082)))) begin
        eh_arr_we1 = ap_const_logic_1;
    end else begin
        eh_arr_we1 = ap_const_logic_0;
    end
end

/// f_phi_fu_573_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or f_reg_569 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or f_2_fu_1502_p3)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        f_phi_fu_573_p4 = f_2_fu_1502_p3;
    end else begin
        f_phi_fu_573_p4 = f_reg_569;
    end
end

/// grp_fu_640_p0 assign process. ///
always @ (ap_reg_ppiten_pp0_it3 or h1_reg_reg_581 or ap_sig_cseq_ST_st11_fsm_6 or h1_reg_phi_fu_584_p4)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_6)) begin
        grp_fu_640_p0 = h1_reg_reg_581;
    end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) begin
        grp_fu_640_p0 = h1_reg_phi_fu_584_p4;
    end else begin
        grp_fu_640_p0 = 'bx;
    end
end

/// h1_reg_phi_fu_584_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or h1_reg_reg_581 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or m_reg_2235)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        h1_reg_phi_fu_584_p4 = m_reg_2235;
    end else begin
        h1_reg_phi_fu_584_p4 = h1_reg_reg_581;
    end
end

/// h_phi_fu_561_p4 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_5 or ap_reg_ppiten_pp0_it1 or h_reg_557 or tmp_32_reg_2166 or tmp_eme_4_reg_2191)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_const_lv1_0 == tmp_32_reg_2166))) begin
        h_phi_fu_561_p4 = tmp_eme_4_reg_2191;
    end else begin
        h_phi_fu_561_p4 = h_reg_557;
    end
end

/// max_1_phi_fu_595_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or max_1_reg_591 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or m_0_s_reg_2251)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        max_1_phi_fu_595_p4 = m_0_s_reg_2251;
    end else begin
        max_1_phi_fu_595_p4 = max_1_reg_591;
    end
end

/// max_j_1_phi_fu_607_p4 assign process. ///
always @ (ap_reg_ppiten_pp0_it4 or max_j_1_reg_603 or ap_reg_ppstg_tmp_32_reg_2166_pp0_it3 or mj_0_s_reg_2256)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_32_reg_2166_pp0_it3))) begin
        max_j_1_phi_fu_607_p4 = mj_0_s_reg_2256;
    end else begin
        max_j_1_phi_fu_607_p4 = max_j_1_reg_603;
    end
end

/// mj_phi_fu_502_p4 assign process. ///
always @ (mj_reg_499 or ap_sig_cseq_ST_pp0_stg0_fsm_5 or ap_reg_ppiten_pp0_it1 or tmp_32_reg_2166 or j_1_reg_2201)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_const_lv1_0 == tmp_32_reg_2166))) begin
        mj_phi_fu_502_p4 = j_1_reg_2201;
    end else begin
        mj_phi_fu_502_p4 = mj_reg_499;
    end
end

/// qs_V_address0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_5 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_st4_fsm_3 or tmp_18_fu_885_p1 or tmp_34_fu_1050_p1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
        qs_V_address0 = tmp_34_fu_1050_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        qs_V_address0 = tmp_18_fu_885_p1;
    end else begin
        qs_V_address0 = 'bx;
    end
end

/// qs_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_5 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_st4_fsm_3)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)))) begin
        qs_V_ce0 = ap_const_logic_1;
    end else begin
        qs_V_ce0 = ap_const_logic_0;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or tmp_7_fu_750_p2 or tmp_16_fu_869_p2 or tmp_16_reg_2082 or tmp_32_fu_1036_p2 or tmp_51_fu_1642_p2)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~(ap_start == ap_const_logic_0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            if ((tmp_7_fu_750_p2 == ap_const_lv1_0)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st3_fsm_2 : 
        begin
            ap_NS_fsm = ap_ST_st4_fsm_3;
        end
        ap_ST_st4_fsm_3 : 
        begin
            if ((ap_const_lv1_0 == tmp_16_fu_869_p2)) begin
                ap_NS_fsm = ap_ST_st11_fsm_6;
            end else begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end
        end
        ap_ST_st5_fsm_4 : 
        begin
            ap_NS_fsm = ap_ST_pp0_stg0_fsm_5;
        end
        ap_ST_pp0_stg0_fsm_5 : 
        begin
            if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == tmp_32_fu_1036_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_5;
            end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_lv1_0 == tmp_32_fu_1036_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
                ap_NS_fsm = ap_ST_st11_fsm_6;
            end else begin
                ap_NS_fsm = ap_ST_st11_fsm_6;
            end
        end
        ap_ST_st11_fsm_6 : 
        begin
            if (((ap_const_lv1_0 == tmp_16_reg_2082) | ~(ap_const_lv1_0 == tmp_51_fu_1642_p2))) begin
                ap_NS_fsm = ap_ST_st13_fsm_8;
            end else begin
                ap_NS_fsm = ap_ST_st12_fsm_7;
            end
        end
        ap_ST_st12_fsm_7 : 
        begin
            ap_NS_fsm = ap_ST_st4_fsm_3;
        end
        ap_ST_st13_fsm_8 : 
        begin
            ap_NS_fsm = ap_ST_st2_fsm_1;
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign abs_mj_m_i_V_fu_1679_p3 = ((abscond_fu_1673_p2[0:0]===1'b1)? tmp_137_fu_1663_p1: neg_fu_1667_p2);
assign abscond_fu_1673_p2 = ($signed(r_V_4_fu_1658_p2) > $signed(13'b0000000000000)? 1'b1: 1'b0);

/// ap_sig_bdd_157 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_157 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_179 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_179 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end

/// ap_sig_bdd_192 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_192 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_218 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_218 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end

/// ap_sig_bdd_27 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_27 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_319 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_319 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end

/// ap_sig_bdd_352 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_352 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end

/// ap_sig_bdd_363 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_363 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end

/// ap_sig_bdd_71 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_71 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
assign aw1_fu_846_p3 = ((tmp_14_reg_2061[0:0]===1'b1)? aw_tmp_2_reg_2056: tmp_124_reg_2011);
assign aw_tmp_2_fu_784_p3 = ((tmp_12_fu_779_p2[0:0]===1'b1)? aw_tmp_fu_770_p2: tmp_123_reg_2006);
assign aw_tmp_fu_770_p2 = w_in << tmp_8_cast_fu_766_p1;
assign backw_reg_0_backw_tmp_1_fu_1312_p3 = ((tmp_56_fu_1306_p2[0:0]===1'b1)? backw_reg_phi_fu_525_p4: backw_reg_2_fu_1298_p3);
assign backw_reg_2_fu_1298_p3 = ((grp_fu_640_p2[0:0]===1'b1)? ap_const_lv8_0: backw_tmp_phi_fu_513_p4);
assign beg_1_fu_1007_p3 = ((tmp_30_fu_1002_p2[0:0]===1'b1)? j_reg_2111: qlen_end_1_fu_996_p3);
assign beg_2_fu_1820_p2 = (tmp_84_fu_1814_p2 - backw_reg_reg_521);
assign e_1_fu_1282_p2 = (e_reg_2211 - e_del);
assign e_2_fu_1481_p3 = ((tmp_85_fu_1476_p2[0:0]===1'b1)? ap_reg_ppstg_e_1_reg_2229_pp0_it3: t_1_cast_fu_1473_p1);
assign e_4_fu_1155_p4 = {{eh_arr_q0[ap_const_lv32_F : ap_const_lv32_8]}};
assign e_fu_1181_p3 = ((tmp_31_reg_2147[0:0]===1'b1)? ap_const_lv8_0: e_4_fu_1155_p4);
assign eh_arr_address0 = tmp_35_fu_1055_p1;
assign eh_e_addr_11516_part_set_fu_1523_p3 = {{ap_const_lv8_0}, {h1_reg_reg_581}};
assign eh_h_addr68_part_set_fu_1510_p3 = {{e_2_fu_1481_p3}, {h1_reg_reg_581}};
assign end_1_fu_977_p3 = ((tmp_27_fu_960_p2[0:0]===1'b1)? end_2_fu_972_p2: end_reg_471);
assign end_2_fu_972_p2 = (tmp33_fu_966_p2 + aw1_reg_2066);
assign end_3_fu_1831_p2 = (tmp42_fu_1826_p2 + max_j_1_reg_603);
assign f_1_fu_1491_p2 = (f_reg_569 - e_ins);
assign f_2_fu_1502_p3 = ((tmp_87_fu_1496_p2[0:0]===1'b1)? f_1_fu_1491_p2: t_3_cast_fu_1488_p1);
assign forw_tmp_1_fu_1422_p3 = ((tmp_55_reg_2240[0:0]===1'b1)? forw_tmp_reg_545: forw_tmp_6_fu_1413_p2);
assign forw_tmp_2_fu_1575_p2 = (forw_tmp_reg_545 + ap_const_lv8_1);
assign forw_tmp_3_fu_1465_p3 = ((tmp_60_fu_1402_p2[0:0]===1'b1)? ap_const_lv8_0: sel_tmp7_fu_1457_p3);
assign forw_tmp_4_fu_1581_p3 = ((or_cond1_fu_1569_p2[0:0]===1'b1)? forw_tmp_reg_545: forw_tmp_2_fu_1575_p2);
assign forw_tmp_5_fu_1589_p3 = ((or_cond_80_fu_1538_p2[0:0]===1'b1)? forw_tmp_reg_545: forw_tmp_4_fu_1581_p3);
assign forw_tmp_6_fu_1413_p2 = (ap_const_lv8_1 + forw_tmp_reg_545);
assign forw_update_1_fu_1419_p1 = tmp_55_reg_2240;
assign forw_update_3_fu_1449_p3 = ((tmp_60_fu_1402_p2[0:0]===1'b1)? ap_const_lv8_0: sel_tmp5_fu_1441_p3);
assign grp_fu_640_p2 = (grp_fu_640_p0 == ap_const_lv8_0? 1'b1: 1'b0);
assign gscore_V_fu_1601_p1 = $signed(h1_reg_reg_581);
assign gscore_ret_fu_1889_p1 = $signed(p_0408_4_reg_627);
assign gtle_ret_cast_fu_1885_p1 = gtle_ret_fu_1879_p2;
assign gtle_ret_fu_1879_p2 = ($signed(tmp_64_cast_fu_1875_p1) + $signed(ap_const_lv13_1));
assign h1_init_val_2_fu_890_p2 = (h1_init_val1_reg_490 - e_del);
assign h1_init_val_fu_700_p2 = (h0 - o_del);
assign h_3_fu_1265_p2 = (tmp_48_fu_1210_p27 + newSel4_reg_2206);
assign h_4_fu_1275_p3 = ((tmp_52_fu_1270_p2[0:0]===1'b1)? h_3_fu_1265_p2: e_reg_2211);
assign h_6_fu_1151_p1 = eh_arr_q0[7:0];
assign i_V_fu_874_p2 = (max_ie_V_reg_426 + ap_const_lv11_1);
assign i_op_assign_3_fu_1807_p3 = ((tmp_73_reg_2316[0:0]===1'b1)? max_j_1_reg_603: max_j_fu_150);
assign j_1_fu_1145_p2 = (ap_const_lv8_1 + mj_phi_fu_502_p4);
assign j_fu_943_p3 = ((tmp_22_fu_928_p2[0:0]===1'b1)? tmp_24_fu_938_p2: beg_reg_460);
assign k_V_fu_756_p2 = (p_1_reg_369 + ap_const_lv2_1);
assign lhs_V_1_fu_1654_p1 = $signed(max_j_1_reg_603);
assign lhs_V_2_cast_fu_706_p1 = qs_baddr_V;
assign lhs_V_fu_919_p1 = max_ie_V_reg_426;
assign m_0_s_fu_1320_p3 = ((tmp_56_fu_1306_p2[0:0]===1'b1)? max_1_phi_fu_595_p4: m_fu_1291_p3);
assign m_fu_1291_p3 = ((tmp_54_fu_1286_p2[0:0]===1'b1)? h_4_reg_2223: f_phi_fu_573_p4);
assign max_2_fu_1694_p3 = ((tmp_73_fu_1648_p2[0:0]===1'b1)? max_1_reg_591: max_fu_146);
assign max_ie_V_cast_fu_985_p1 = max_ie_V_reg_426;
assign max_off_V_1_fu_1792_p3 = ((tmp_83_fu_1786_p2[0:0]===1'b1)? max_off_V_fu_1783_p1: max_off_V_3_fu_154);
assign max_off_V_2_fu_1800_p3 = ((tmp_73_reg_2316[0:0]===1'b1)? max_off_V_1_fu_1792_p3: max_off_V_3_fu_154);
assign max_off_V_fu_1783_p1 = $signed(abs_mj_m_i_V_reg_2322);
assign maxoff_ret_fu_1712_p1 = $signed(max_off_V_3_fu_154);
assign mj_0_s_fu_1328_p3 = ((tmp_56_fu_1306_p2[0:0]===1'b1)? max_j_1_phi_fu_607_p4: ap_reg_ppstg_mj_reg_499_pp0_it2);
assign neg_fu_1667_p2 = (ap_const_lv10_0 - tmp_137_fu_1663_p1);
assign newSel2_fu_1138_p3 = ((sel_tmp6_fu_1112_p2[0:0]===1'b1)? h_phi_fu_561_p4: h0);
assign newSel3_fu_1168_p3 = ((tmp_31_reg_2147[0:0]===1'b1)? tmp_eme_5_cast_fu_1165_p1: h_6_fu_1151_p1);
assign newSel4_fu_1175_p3 = ((or_cond_reg_2186[0:0]===1'b1)? newSel2_reg_2196: newSel3_fu_1168_p3);
assign newSel_fu_1123_p3 = ((tmp_31_reg_2147[0:0]===1'b1)? tmp_eme_2_fu_1072_p2: h_phi_fu_561_p4);
assign notlhs_fu_1760_p2 = (tmp_70_cast_fu_1720_p1 != prev_V_reg_2044? 1'b1: 1'b0);
assign oe_ins_fu_658_p2 = (e_ins + o_ins);
assign op2_assign_cast_fu_1756_p1 = op2_assign_fu_1750_p2;
assign op2_assign_fu_1750_p2 = ($signed(tmp_75_cast_fu_1733_p1) + $signed(tmp_76_cast_fu_1746_p1));
assign or_cond1_fu_1569_p2 = (tmp_43_fu_1557_p2 & tmp_44_fu_1563_p2);
assign or_cond_80_fu_1538_p2 = (tmp_37_fu_1532_p2 | grp_fu_640_p2);
assign or_cond_fu_1117_p2 = (sel_tmp6_fu_1112_p2 | sel_tmp2_fu_1095_p2);
assign p_0408_1_s_fu_1618_p3 = ((tmp_50_fu_1605_p2[0:0]===1'b1)? p_0408_1_reg_449: gscore_V_fu_1601_p1);
assign p_0408_3_fu_1634_p3 = ((tmp_46_fu_1597_p2[0:0]===1'b1)? p_0408_1_s_fu_1618_p3: p_0408_1_reg_449);
assign p_0414_1_s_fu_1611_p3 = ((tmp_50_fu_1605_p2[0:0]===1'b1)? p_0414_1_reg_438: max_ie_V_cast_reg_2124);
assign p_0414_3_fu_1626_p3 = ((tmp_46_fu_1597_p2[0:0]===1'b1)? p_0414_1_s_fu_1611_p3: p_0414_1_reg_438);
assign p_0420_2_fu_1687_p3 = ((tmp_73_fu_1648_p2[0:0]===1'b1)? max_ie_V_cast_reg_2124: p_2_fu_158);
assign p_cast_fu_989_p1 = p_s_reg_2101;
assign p_s_fu_907_p3 = ((tmp_129_fu_899_p3[0:0]===1'b1)? ap_const_lv7_0: tmp_128_fu_895_p1);
assign p_shl_fu_1028_p3 = {{tmp_131_fu_1020_p1}, {ap_const_lv2_0}};
assign phitmp1_fu_1777_p2 = (rev1_fu_1771_p2 & notlhs_fu_1760_p2);
assign phitmp_fu_1392_p2 = (ap_const_lv8_1 + backw_reg_2_fu_1298_p3);
assign prev_V_fu_762_p1 = val_assign_reg_360[9:0];
assign qle_ret_cast_fu_1857_p1 = qle_ret_fu_1851_p2;
assign qle_ret_fu_1851_p2 = ($signed(tmp_61_cast_fu_1847_p1) + $signed(ap_const_lv9_1));
assign qlen_end_1_fu_996_p3 = ((tmp_29_fu_992_p2[0:0]===1'b1)? qlen: end_1_reg_2118);
assign r_V_2_fu_955_p2 = ($signed(tmp_cast_reg_2077) + $signed(lhs_V_fu_919_p1));
assign r_V_3_fu_1045_p2 = (rhs_V_1_cast_fu_1041_p1 + lhs_V_2_cast_reg_2026);
assign r_V_4_fu_1658_p2 = ($signed(lhs_V_1_fu_1654_p1) - $signed(lhs_V_reg_2106));
assign r_V_fu_923_p2 = ($signed(lhs_V_fu_919_p1) - $signed(rhs_V_reg_2072));
assign rev1_fu_1771_p2 = (slt_fu_1765_p2 ^ ap_const_lv1_1);
assign rev_fu_744_p2 = (tmp_126_fu_736_p3 ^ ap_const_lv1_1);
assign rhs_V_1_cast_fu_1041_p1 = mj_phi_fu_502_p4;
assign rhs_V_cast_fu_855_p1 = $signed(aw1_fu_846_p3);
assign rhs_V_fu_851_p1 = $signed(aw1_fu_846_p3);
assign sel_tmp1_fu_1429_p2 = (tmp_60_fu_1402_p2 ^ ap_const_lv1_1);
assign sel_tmp2_fu_1095_p2 = (tmp_31_reg_2147 & tmp_39_fu_1060_p2);
assign sel_tmp3_fu_1435_p2 = (tmp_74_fu_1407_p2 & sel_tmp1_fu_1429_p2);
assign sel_tmp4_fu_1100_p2 = (tmp_39_fu_1060_p2 ^ ap_const_lv1_1);
assign sel_tmp5_fu_1441_p3 = ((sel_tmp3_fu_1435_p2[0:0]===1'b1)? forw_update_1_fu_1419_p1: forw_update_reg_533);
assign sel_tmp6_fu_1112_p2 = (tmp34_fu_1106_p2 & tmp_31_reg_2147);
assign sel_tmp7_fu_1457_p3 = ((sel_tmp3_fu_1435_p2[0:0]===1'b1)? forw_tmp_1_fu_1422_p3: forw_tmp_reg_545);
assign slt_fu_1765_p2 = ($signed(max_off_V_3_fu_154) < $signed(op2_assign_cast_fu_1756_p1)? 1'b1: 1'b0);
assign sum_fu_710_p2 = (o_del + e_del);
assign t_1_cast_fu_1473_p1 = t_1_reg_2266;
assign t_1_fu_1361_p3 = ((tmp_s_fu_1355_p2[0:0]===1'b1)? tmp_135_fu_1351_p1: ap_const_lv7_0);
assign t_2_fu_1369_p2 = (m_fu_1291_p3 - oe_ins_reg_2001);
assign t_3_cast_fu_1488_p1 = t_3_reg_2271;
assign t_3_fu_1384_p3 = ((tmp_86_fu_1378_p2[0:0]===1'b1)? tmp_136_fu_1374_p1: ap_const_lv7_0);
assign t_fu_1346_p2 = (m_fu_1291_p3 - sum_reg_2031);
assign tle_ret_cast_fu_1871_p1 = tle_ret_fu_1865_p2;
assign tle_ret_fu_1865_p2 = ($signed(tmp_62_cast_fu_1861_p1) + $signed(ap_const_lv13_1));
assign tmp33_fu_966_p2 = (ap_const_lv8_1 + tmp_130_fu_934_p1);
assign tmp34_fu_1106_p2 = (tmp_45_fu_1066_p2 & sel_tmp4_fu_1100_p2);
assign tmp41_fu_1196_p2 = (tmp_68_cast_fu_1192_p1 + tmp_65_cast_reg_2156);
assign tmp42_fu_1826_p2 = (ap_const_lv8_2 + forw_tmp_5_reg_2296);
assign tmp49_cast_fu_1201_p1 = tmp41_fu_1196_p2;
assign tmp_11_cast_fu_775_p1 = $signed(aw_tmp_fu_770_p2);
assign tmp_123_fu_664_p1 = max_ins[7:0];
assign tmp_124_fu_668_p1 = max_del[7:0];
assign tmp_125_fu_678_p1 = tmp_eme_fu_672_p2[6:0];
assign tmp_126_fu_736_p3 = p_1_reg_369[ap_const_lv32_1];
assign tmp_128_fu_895_p1 = h1_init_val_2_fu_890_p2[6:0];
assign tmp_129_fu_899_p3 = h1_init_val_2_fu_890_p2[ap_const_lv32_7];
assign tmp_12_fu_779_p2 = ($signed(tmp_11_cast_fu_775_p1) < $signed(max_ins)? 1'b1: 1'b0);
assign tmp_130_fu_934_p1 = max_ie_V_reg_426[7:0];
assign tmp_131_fu_1020_p1 = qs_V_q0[2:0];
assign tmp_133_fu_1077_p1 = tmp_eme_2_fu_1072_p2[6:0];
assign tmp_134_fu_1188_p1 = qs_V_q0[2:0];
assign tmp_135_fu_1351_p1 = t_fu_1346_p2[6:0];
assign tmp_136_fu_1374_p1 = t_2_fu_1369_p2[6:0];
assign tmp_137_fu_1663_p1 = r_V_4_fu_1658_p2[9:0];
assign tmp_13_cast_fu_791_p1 = $signed(aw_tmp_2_fu_784_p3);
assign tmp_14_fu_795_p2 = ($signed(tmp_13_cast_fu_791_p1) < $signed(max_del)? 1'b1: 1'b0);
assign tmp_16_fu_869_p2 = (max_ie_V_reg_426 < tlen_V? 1'b1: 1'b0);
assign tmp_18_fu_885_p1 = ts_baddr_t_V_fu_880_p2;
assign tmp_20_cast_fu_915_p1 = beg_reg_460;
assign tmp_22_fu_928_p2 = ($signed(tmp_20_cast_fu_915_p1) < $signed(r_V_fu_923_p2)? 1'b1: 1'b0);
assign tmp_24_fu_938_p2 = (tmp_130_fu_934_p1 - aw1_reg_2066);
assign tmp_25_cast_fu_951_p1 = end_reg_471;
assign tmp_27_fu_960_p2 = ($signed(tmp_25_cast_fu_951_p1) > $signed(r_V_2_fu_955_p2)? 1'b1: 1'b0);
assign tmp_29_fu_992_p2 = (end_1_reg_2118 > qlen? 1'b1: 1'b0);
assign tmp_30_fu_1002_p2 = (j_reg_2111 > qlen_end_1_fu_996_p3? 1'b1: 1'b0);
assign tmp_31_fu_1014_p2 = (max_ie_V_reg_426 == ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_32_fu_1036_p2 = (mj_phi_fu_502_p4 < qlen_end_1_reg_2135? 1'b1: 1'b0);
assign tmp_34_fu_1050_p1 = r_V_3_fu_1045_p2;
assign tmp_35_fu_1055_p1 = mj_phi_fu_502_p4;
assign tmp_36_fu_1519_p1 = qlen_end_1_reg_2135;
assign tmp_37_fu_1532_p2 = (forw_update_reg_533 != ap_const_lv8_0? 1'b1: 1'b0);
assign tmp_39_fu_1060_p2 = (mj_phi_fu_502_p4 == ap_const_lv8_0? 1'b1: 1'b0);
assign tmp_40_cast_fu_1544_p1 = beg_1_reg_2141;
assign tmp_41_cast_fu_1547_p1 = $signed(max_j_1_reg_603);
assign tmp_42_fu_1551_p2 = ($signed(tmp_41_cast_fu_1547_p1) + $signed(ap_const_lv9_2));
assign tmp_43_fu_1557_p2 = ($signed(tmp_40_cast_fu_1544_p1) < $signed(tmp_42_fu_1551_p2)? 1'b1: 1'b0);
assign tmp_44_fu_1563_p2 = (forw_tmp_reg_545 == ap_const_lv8_0? 1'b1: 1'b0);
assign tmp_45_fu_1066_p2 = (mj_phi_fu_502_p4 == ap_const_lv8_1? 1'b1: 1'b0);
assign tmp_46_fu_1597_p2 = (beg_1_reg_2141 == qlen? 1'b1: 1'b0);
assign tmp_47_fu_1081_p2 = ($signed(tmp_eme_2_fu_1072_p2) > $signed(8'b00000000)? 1'b1: 1'b0);
assign tmp_48_fu_1210_p1 = ap_const_lv8_1;
assign tmp_48_fu_1210_p10 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p11 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p12 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p13 = ap_const_lv8_1;
assign tmp_48_fu_1210_p14 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p15 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p16 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p17 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p18 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p19 = ap_const_lv8_1;
assign tmp_48_fu_1210_p2 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p20 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p21 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p22 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p23 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p24 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p25 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p26 = tmp_69_reg_2218;
assign tmp_48_fu_1210_p3 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p4 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p5 = ap_const_lv8_FF;
assign tmp_48_fu_1210_p6 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p7 = ap_const_lv8_1;
assign tmp_48_fu_1210_p8 = ap_const_lv8_FC;
assign tmp_48_fu_1210_p9 = ap_const_lv8_FC;
assign tmp_50_fu_1605_p2 = ($signed(p_0408_1_reg_449) > $signed(gscore_V_fu_1601_p1)? 1'b1: 1'b0);
assign tmp_51_fu_1642_p2 = (max_1_reg_591 == ap_const_lv8_0? 1'b1: 1'b0);
assign tmp_52_fu_1270_p2 = ($signed(h_3_fu_1265_p2) > $signed(e_reg_2211)? 1'b1: 1'b0);
assign tmp_54_fu_1286_p2 = ($signed(h_4_reg_2223) > $signed(f_phi_fu_573_p4)? 1'b1: 1'b0);
assign tmp_56_fu_1306_p2 = ($signed(max_1_phi_fu_595_p4) > $signed(m_fu_1291_p3)? 1'b1: 1'b0);
assign tmp_57_cast_fu_1398_p1 = ap_reg_ppstg_mj_reg_499_pp0_it3;
assign tmp_58_cast_fu_1336_p1 = $signed(mj_0_s_fu_1328_p3);
assign tmp_59_fu_1340_p2 = ($signed(ap_const_lv9_2) + $signed(tmp_58_cast_fu_1336_p1));
assign tmp_60_fu_1402_p2 = ($signed(tmp_57_cast_fu_1398_p1) < $signed(tmp_59_reg_2261)? 1'b1: 1'b0);
assign tmp_61_cast_fu_1847_p1 = $signed(max_j_fu_150);
assign tmp_62_cast_fu_1861_p1 = $signed(p_2_fu_158);
assign tmp_64_cast_fu_1875_p1 = $signed(p_0414_4_reg_615);
assign tmp_65_cast_fu_1024_p1 = tmp_131_fu_1020_p1;
assign tmp_66_fu_1716_p1 = $signed(max_fu_146);
assign tmp_68_cast_fu_1192_p1 = tmp_134_fu_1188_p1;
assign tmp_69_fu_1205_p2 = (p_shl_reg_2161 + tmp49_cast_fu_1201_p1);
assign tmp_6_fu_682_p2 = ($signed(tmp_eme_fu_672_p2) > $signed(8'b00000000)? 1'b1: 1'b0);
assign tmp_70_cast_fu_1720_p1 = $signed(max_fu_146);
assign tmp_73_fu_1648_p2 = ($signed(max_1_reg_591) > $signed(max_fu_146)? 1'b1: 1'b0);
assign tmp_74_fu_1407_p2 = (forw_update_reg_533 == ap_const_lv8_0? 1'b1: 1'b0);
assign tmp_75_cast_fu_1733_p1 = $signed(tmp_88_fu_1724_p4);
assign tmp_76_cast_fu_1746_p1 = $signed(tmp_89_fu_1737_p4);
assign tmp_7_fu_750_p2 = (isBreak_reg_404 & rev_fu_744_p2);
assign tmp_83_fu_1786_p2 = ($signed(max_off_V_3_fu_154) < $signed(max_off_V_fu_1783_p1)? 1'b1: 1'b0);
assign tmp_84_fu_1814_p2 = (ap_const_lv8_1 + max_j_1_reg_603);
assign tmp_85_fu_1476_p2 = ($signed(ap_reg_ppstg_e_1_reg_2229_pp0_it3) > $signed(t_1_cast_fu_1473_p1)? 1'b1: 1'b0);
assign tmp_86_fu_1378_p2 = ($signed(t_2_fu_1369_p2) > $signed(8'b00000000)? 1'b1: 1'b0);
assign tmp_87_fu_1496_p2 = ($signed(f_1_fu_1491_p2) > $signed(t_3_cast_fu_1488_p1)? 1'b1: 1'b0);
assign tmp_88_fu_1724_p4 = {{aw_tmp_reg_2049[ap_const_lv32_7 : ap_const_lv32_1]}};
assign tmp_89_fu_1737_p4 = {{aw_tmp_reg_2049[ap_const_lv32_7 : ap_const_lv32_2]}};
assign tmp_8_cast_fu_766_p1 = p_1_reg_369;
assign tmp_cast_fu_865_p1 = tmp_fu_859_p2;
assign tmp_eme_1_cast_fu_696_p1 = tmp_eme_1_fu_688_p3;
assign tmp_eme_1_fu_688_p3 = ((tmp_6_fu_682_p2[0:0]===1'b1)? tmp_125_fu_678_p1: ap_const_lv7_0);
assign tmp_eme_2_fu_1072_p2 = (h_phi_fu_561_p4 - e_ins);
assign tmp_eme_4_fu_1130_p3 = ((or_cond_fu_1117_p2[0:0]===1'b1)? h_phi_fu_561_p4: newSel_fu_1123_p3);
assign tmp_eme_5_cast_fu_1165_p1 = tmp_eme_5_reg_2181;
assign tmp_eme_5_fu_1087_p3 = ((tmp_47_fu_1081_p2[0:0]===1'b1)? tmp_133_fu_1077_p1: ap_const_lv7_0);
assign tmp_eme_fu_672_p2 = (h0 - oe_ins_fu_658_p2);
assign tmp_fu_859_p2 = ($signed(ap_const_lv9_1) + $signed(rhs_V_cast_fu_855_p1));
assign tmp_s_fu_1355_p2 = ($signed(t_fu_1346_p2) > $signed(8'b00000000)? 1'b1: 1'b0);
assign ts_baddr_t_V_fu_880_p2 = (ts_baddr_V + max_ie_V_reg_426);
assign w_ret_write_assign_fu_800_p1 = $signed(aw_tmp_s_reg_415);
always @ (posedge ap_clk)
begin
    tmp_eme_1_cast_reg_2016[7] <= 1'b0;
    lhs_V_2_cast_reg_2026[9] <= 1'b0;
    lhs_V_reg_2106[12:11] <= 2'b00;
    max_ie_V_cast_reg_2124[11] <= 1'b0;
    tmp_65_cast_reg_2156[3] <= 1'b0;
    p_shl_reg_2161[1:0] <= 2'b00;
end



endmodule //sw_pe_array_sw_extend