This repository contains the code developed during my Master's dissertation. The dissertation's goal was to create a new DSL for data analytics, for FPGA execution. The DSL compiler code is present in this repository. The compiler can target both CPU and CPU-FPGA systems. The current version of the compiler can be executed using the jar at the root of this repository. More information on the compiler usage can be found here.
The structure of the repository is the following:
MyDSLCompiler: This folder contains the compiler code. The folder contains a README with useful information regarding the compiler, in case you're interested in compiling or testing the code.Examples: This folder contains code examples. More information here.
To use the compiler, execute the following command: (requires Java)
java -jar MyDSLCompiler.jar [options] <input-file>
Upon compilation, the code generated is placed inside a folder named output.
The options are described in the following table:
| Option | Long alternative | Arguments | Description |
|---|---|---|---|
-h |
--help |
N/A | Display help information. This includes a description of the available options |
-t |
--target |
chosenTarget={CPU, FPGA} |
Sets the target. The choice can be either CPU or FPGA |
-m |
--measure |
N/A | Adds time measuring code to the generated pipeline (only works with SDSoC) |
-O0 |
N/A | N/A | Use no optimizations |
-O1 |
N/A | N/A | Optimize for speed and space (on FPGA) |
-O2 |
N/A | N/A | Optimize for speed (on FPGA) |
Note that the optimizations only work when the FPGA target is chosen (either through the command line switch or using pragmas).