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regression/verilog/SVA/cover_sequence2.desc
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+KNOWNBUG
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+cover_sequence2.sv
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+--bound 2
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+^\[main\.p0\] cover \(main\.x == 2 ##1 main\.x == 3 ##1 main\.x == 100\): PROVED$
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+^\[main\.p1\] cover \(main\.x == 98 ##1 main\.x == 99 ##1 main\.x == 100\): REFUTED up to bound 2$
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+^EXIT=10$
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+^SIGNAL=0$
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+--
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+^warning: ignoring
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regression/verilog/SVA/cover_sequence2.sv
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+module main(input clk);
+
+ // count up
+ reg [7:0] x = 0;
+ always @(posedge clk)
+ x++;
+ // expected to fail
+ p0: cover property (x==2 ##1 x==3 ##1 x==100);
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+ // expected to fail until bound reaches 100
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+ p1: cover property (x==98 ##1 x==99 ##1 x==100);
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+endmodule
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