Merge pull request #1075 from diffblue/empty_sequence1

KNOWNBUG test for empty SVA sequences

Author: tautschnig

regression/verilog/SVA/empty_sequence1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+empty_sequence1.sv
+--bound 5
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Repetition with zero is not implemented.

regression/verilog/SVA/empty_sequence1.sv

@@ -0,0 +1,14 @@
+module main(input clk);
+
+  reg [7:0] x = 0;
+
+  always @(posedge clk)
+    x<=x+1;
+
+  // The empty sequence does not match
+  initial p0: assert property (1[*0]);
+
+  // But can be concatenated
+  initial p1: assert property (1[*0] ##1 x == 0);
+
+endmodule