Merge pull request #408 from diffblue/ports5

Verilog: KNOWNBUG test for ports that have SystemVerilog datatypes

Author: tautschnig

regression/verilog/modules/ports5.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+ports5.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The grammar currently doesn't allow datatypes as port types.

regression/verilog/modules/ports5.sv

@@ -0,0 +1,6 @@
+// Ports may use SystemVerilog datatypes.
+module main(input logic [31:0] data);
+
+  always assert property1: $bits(data) == 32;
+
+endmodule