Increase the error verbosity of the Verilog parser

kroening · kroening · commit 529fd28042c9 · 2025-02-04T12:17:56.000Z
Bison is instructed to generate verbose error messages for the Verilog parser.

This results in more helpful syntax error messages at least in some cases.
diff --git a/regression/smv/syntax-errors/syntax1.desc b/regression/smv/syntax-errors/syntax1.desc
@@ -0,0 +1,7 @@
+CORE
+syntax1.smv
+
+^file .* line 3: syntax error, unexpected VAR, expecting string or "'" before 'VAR'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/smv/syntax-errors/syntax1.smv b/regression/smv/syntax-errors/syntax1.smv
@@ -0,0 +1,4 @@
+MODULE -- forgot the name
+
+VAR abc : BOOLEAN;
+
diff --git a/regression/smv/syntax-errors/syntax2.desc b/regression/smv/syntax-errors/syntax2.desc
@@ -0,0 +1,7 @@
+CORE
+syntax2.smv
+
+^file .* line 3: syntax error, unexpected VAR before 'VAR'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/smv/syntax-errors/syntax2.smv b/regression/smv/syntax-errors/syntax2.smv
@@ -0,0 +1,4 @@
+-- forgot the MODULE
+
+VAR abc : BOOLEAN;
+
diff --git a/regression/smv/syntax-errors/syntax3.desc b/regression/smv/syntax-errors/syntax3.desc
@@ -0,0 +1,7 @@
+CORE
+syntax3.smv
+
+^file .* line 3: syntax error, unexpected string, expecting number before 'not_a_number'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/smv/syntax-errors/syntax3.smv b/regression/smv/syntax-errors/syntax3.smv
@@ -0,0 +1,4 @@
+MODULE main
+
+VAR foobar : 1.. not_a_number;
+
diff --git a/regression/verilog/preprocessor/ifdef1.desc b/regression/verilog/preprocessor/ifdef1.desc
@@ -1,7 +1,7 @@
 CORE
 ifdef1.v
 
-^file ifdef1\.v line 4: syntax error before 'syntax'$
+^file ifdef1\.v line 4: syntax error, unexpected .* before 'syntax'$
 ^EXIT=1$
 ^SIGNAL=0$
 --
diff --git a/regression/verilog/preprocessor/ifdef2.desc b/regression/verilog/preprocessor/ifdef2.desc
@@ -1,7 +1,7 @@
 CORE
 ifdef2.v
 
-^file ifdef2\.v line 4: syntax error before 'syntax'$
+^file ifdef2\.v line 4: syntax error, unexpected .* before 'syntax'$
 ^EXIT=1$
 ^SIGNAL=0$
 --
diff --git a/regression/verilog/preprocessor/multi-line-define2.desc b/regression/verilog/preprocessor/multi-line-define2.desc
@@ -1,7 +1,7 @@
 CORE
 multi-line-define2.v
 
-^file multi-line-define2\.v line 4: syntax error before 'syntax'$
+^file multi-line-define2\.v line 4: syntax error, unexpected .* before 'syntax'$
 ^EXIT=1$
 ^SIGNAL=0$
 --
diff --git a/regression/verilog/preprocessor/multi-line-define3.desc b/regression/verilog/preprocessor/multi-line-define3.desc
@@ -1,7 +1,7 @@
 CORE
 multi-line-define3.v
 
-^file multi-line-define3\.v line 4: syntax error before 'syntax'$
+^file multi-line-define3\.v line 4: syntax error, unexpected .* before 'syntax'$
 ^EXIT=1$
 ^SIGNAL=0$
 --
diff --git a/regression/verilog/syntax-errors/syntax1.desc b/regression/verilog/syntax-errors/syntax1.desc
@@ -0,0 +1,7 @@
+CORE
+syntax1.sv
+
+^file .* line 1: syntax error, unexpected ';', expecting TOK_NON_TYPE_IDENTIFIER before ';'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/syntax-errors/syntax1.sv b/regression/verilog/syntax-errors/syntax1.sv
@@ -0,0 +1 @@
+module ;// forgot the name
diff --git a/regression/verilog/syntax-errors/syntax2.desc b/regression/verilog/syntax-errors/syntax2.desc
@@ -0,0 +1,7 @@
+CORE
+syntax2.sv
+
+^file syntax2.sv line 3: syntax error, unexpected byte, expecting ';' before 'byte'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/syntax-errors/syntax2.sv b/regression/verilog/syntax-errors/syntax2.sv
@@ -0,0 +1,6 @@
+module main // forgot the ;
+
+byte some_var;
+
+endmodule
+
diff --git a/regression/verilog/syntax-errors/syntax3.desc b/regression/verilog/syntax-errors/syntax3.desc
@@ -0,0 +1,7 @@
+CORE
+syntax3.sv
+
+^file syntax3.sv line 1: syntax error, unexpected ';' before ';'$
+^EXIT=1$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/syntax-errors/syntax3.sv b/regression/verilog/syntax-errors/syntax3.sv
@@ -0,0 +1 @@
+module main(; // forgot the )
diff --git a/src/smvlang/parser.y b/src/smvlang/parser.y
@@ -1,3 +1,4 @@
+/* increase verbosity of error messages, to include expected tokens */
 %define parse.error verbose
 
 %{
diff --git a/src/verilog/parser.y b/src/verilog/parser.y
@@ -1,3 +1,6 @@
+/* increase verbosity of error messages, to include expected tokens */
+%define parse.error verbose
+
 %{
 /*******************************************************************\
 

-Original file line number
+Diff line change
@@ @@ -0,0 +1,4 @@ @@
 +MODULE -- forgot the name
++
 +VAR abc : BOOLEAN;
++