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1 parent aac75f1 commit 5a80e1fCopy full SHA for 5a80e1f
regression/verilog/SVA/sequence4.sv
@@ -11,4 +11,6 @@ module main;
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// sequence concatenation
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initial p0: assert property (x == 0 ##1 x == 1 ##1 x == 2);
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+ initial p1: assert property (x == 0 ##0 x == 0 ##1 x == 1);
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+
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endmodule
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