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Merge pull request #1023 from diffblue/verilog-dx-dz
Verilog: 'dx, 'dz
2 parents 05d5c7d + 9924d2b commit 783d93d

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CHANGELOG

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@@ -3,6 +3,7 @@
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* SystemVerilog: typedefs from package scopes
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* SystemVerilog: assignment patterns with keys for structs
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* SystemVerilog: unbased unsigned literals '0, '1, 'x, 'z
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* Verilog: 'dx, 'dz
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* SMV: LTL V operator, xnor operator
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* SMV: word types and operators
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* --smv-word-level outputs the model as word-level SMV

regression/verilog/expressions/integer_literals1.sv

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@@ -20,4 +20,16 @@ module main;
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p10: assert final ($typename('x)=="logic[0:0]" && 'x===1'bx);
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p11: assert final ($typename('z)=="logic[0:0]" && 'z===1'bz);
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// decimals must not contain x/z "unless there is
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// exactly one digit in the token"
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p12: assert final ('dx===32'hxxxx_xxxx);
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p13: assert final ('dX===32'hxxxx_xxxx);
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p14: assert final ('dz===32'hzzzz_zzzz);
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p15: assert final ('dZ===32'hzzzz_zzzz);
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p16: assert final (4'dx===4'hx);
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p17: assert final (4'dX===4'hx);
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p18: assert final (4'dz===4'hz);
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p19: assert final (4'dZ===4'hz);
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p20: assert final ($typename(4'sdx)==="logic signed[3:0]");
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endmodule

src/verilog/convert_literals.cpp

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@@ -174,6 +174,26 @@ constant_exprt convert_integral_literal(const irep_idt &value)
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rest = rest.substr(1);
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}
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// special case for 'dx/'dX/'dz/'dZ
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// "The default length of x and z is the same as the default length of an integer."
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// Introduced by Verilog 1364-2001.
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if(rest == "dx" || rest == "dX")
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{
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std::size_t final_bits = bits_given ? bits : 32;
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auto type = s_flag_given
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? static_cast<typet>(verilog_signedbv_typet{final_bits})
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: verilog_unsignedbv_typet{final_bits};
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return constant_exprt{std::string(final_bits, 'x'), type};
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}
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else if(rest == "dz" || rest == "dZ")
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{
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std::size_t final_bits = bits_given ? bits : 32;
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auto type = s_flag_given
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? static_cast<typet>(verilog_signedbv_typet{final_bits})
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: verilog_unsignedbv_typet{final_bits};
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return constant_exprt{std::string(final_bits, 'z'), type};
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}
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unsigned base = 10;
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// base given?

src/verilog/scanner.l

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@@ -126,7 +126,7 @@ Word {LetterU}{WordNumUD}*
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EscapedWord "\\"[^\n \t\r]+
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Binary ({Number})?{WSst}'{WSst}[sS]?[bB]{WSst}[01xXzZ?]([01xXzZ?_])*
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Octal ({Number})?{WSst}'{WSst}[sS]?[oO]{WSst}[0-7xXzZ?]([0-7xXzZ?_])*
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Decimal ({Number})?{WSst}'{WSst}[sS]?[dD]{WSst}{Number}
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Decimal ({Number})?{WSst}'{WSst}[sS]?[dD]{WSst}({Number}|[xXzZ]_*)
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Hexdecimal ({Number})?{WSst}'{WSst}[sS]?[hH]{WSst}[0-9a-fA-FxXzZ?]([0-9a-fA-FxXzZ?_])*
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unbased_unsized '0|'1|'x|'X|'z|'Z
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Time {Number}(\.{Number})?("fs"|"ps"|"ns"|"us"|"ms"|"s")

src/verilog/verilog_typecheck_expr.cpp

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@@ -752,7 +752,7 @@ exprt verilog_typecheck_exprt::typename_string(const exprt &expr)
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{
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s = "bit";
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}
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else if(type.id() == ID_signedbv || type.id() == ID_verilog_signedbv)
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else if(type.id() == ID_signedbv)
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{
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if(verilog_type == ID_verilog_byte)
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s = "byte";

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