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2 parents aac75f1 + 5806a49 commit 7cfbb43Copy full SHA for 7cfbb43
regression/verilog/synthesis/rf1.desc
@@ -0,0 +1,9 @@
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+KNOWNBUG
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+rf1.sv
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+
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+^EXIT=0$
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+^SIGNAL=0$
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+--
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+^warning: ignoring
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+Results in an assertion violation.
regression/verilog/synthesis/rf1.sv
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+`define W 8
+`define R 32
+module rf(input clk, input [`W-1:0] data_in, input [`R-1:0] write_enable);
+ // index 0 is not used
+ reg [`W*`R-1:`W] registers;
+ always_ff @(posedge clk) begin
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+ integer r;
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+ for(r=1; r<`R; r++)
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+ if(write_enable[r])
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+ registers[r*`W+:`W] = data_in;
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+ end
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+ always assert property (0);
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+endmodule
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