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1 parent d7fd7c2 commit 8db794cCopy full SHA for 8db794c
regression/verilog/system-functions/past5.desc
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+KNOWNBUG
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+past5.sv
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+
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+^EXIT=0$
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+^SIGNAL=0$
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+--
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+^warning: ignoring
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+$past doesn't support the array.
regression/verilog/system-functions/past5.sv
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+module main;
+ logic [31:0] mem[123];
+ assert property (##1 mem == $past(mem));
+endmodule
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