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Merge pull request #514 from diffblue/verilog-standard-parse-tree
Verilog: standard version now tracked in parse tree
2 parents 1679d2b + 4b330e2 commit 8dbbd22

16 files changed

+88
-47
lines changed

src/verilog/scanner.l

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -71,34 +71,34 @@ static void preprocessor()
7171
TOK_NON_TYPE_IDENTIFIER; \
7272
}
7373
#define KEYWORD(s, x) \
74-
{ if(PARSER.mode >= verilog_standardt::s) \
74+
{ if(PARSER.parse_tree.standard >= verilog_standardt::s) \
7575
return x; \
7676
else \
7777
IDENTIFIER(yytext); \
7878
}
7979
#define SYSTEM_VERILOG_OPERATOR(token, text) \
80-
{ if(PARSER.mode >= verilog_standardt::SV2005) \
80+
{ if(PARSER.parse_tree.standard >= verilog_standardt::SV2005) \
8181
return token; \
8282
else \
8383
yyverilogerror(text " is a System Verilog operator"); \
8484
}
8585
#define VL2SMV_OR_SYSTEM_VERILOG_KEYWORD(x) \
86-
{ if(PARSER.mode >= verilog_standardt::SV2005 || \
87-
PARSER.mode == verilog_standardt::V2005_SMV) \
86+
{ if(PARSER.parse_tree.standard >= verilog_standardt::SV2005 || \
87+
PARSER.parse_tree.standard == verilog_standardt::V2005_SMV) \
8888
return x; \
8989
else \
9090
IDENTIFIER(yytext); \
9191
}
9292
#define VL2SMV_VERILOG_KEYWORD(x) \
93-
{ if(PARSER.mode == verilog_standardt::V2005_SMV) \
93+
{ if(PARSER.parse_tree.standard == verilog_standardt::V2005_SMV) \
9494
return x; \
9595
else \
9696
IDENTIFIER(yytext); \
9797
}
9898
#define VIS_OR_VL2SMV_OR_SYSTEM_VERILOG_KEYWORD(x) \
99-
{ if(PARSER.mode >= verilog_standardt::SV2005 || \
100-
PARSER.mode == verilog_standardt::V2005_SMV || \
101-
PARSER.mode == verilog_standardt::V2005_VIS) \
99+
{ if(PARSER.parse_tree.standard >= verilog_standardt::SV2005 || \
100+
PARSER.parse_tree.standard == verilog_standardt::V2005_SMV || \
101+
PARSER.parse_tree.standard == verilog_standardt::V2005_VIS) \
102102
return x; \
103103
else \
104104
IDENTIFIER(yytext); \

src/verilog/verilog_language.cpp

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -55,23 +55,27 @@ bool verilog_languaget::parse(
5555
const std::string &path,
5656
message_handlert &message_handler)
5757
{
58-
verilog_parsert verilog_parser;
59-
6058
std::stringstream str;
6159

6260
if(preprocess(instream, path, str, message_handler))
6361
return true;
6462

63+
verilog_standardt standard;
64+
65+
if(has_suffix(path, ".sv") || force_systemverilog)
66+
standard = verilog_standardt::SV2023;
67+
else if(vl2smv_extensions)
68+
standard = verilog_standardt::V2005_SMV;
69+
else
70+
standard = verilog_standardt::V2005_SMV;
71+
72+
verilog_parsert verilog_parser(standard);
73+
6574
verilog_parser.set_file(path);
6675
verilog_parser.in=&str;
6776
verilog_parser.log.set_message_handler(message_handler);
6877
verilog_parser.grammar=verilog_parsert::LANGUAGE;
6978

70-
if(has_suffix(path, ".sv") || force_systemverilog)
71-
verilog_parser.mode = verilog_standardt::SV2023;
72-
else if(vl2smv_extensions)
73-
verilog_parser.mode = verilog_standardt::V2005_SMV;
74-
7579
verilog_scanner_init();
7680

7781
bool result=verilog_parser.parse();
@@ -182,7 +186,8 @@ bool verilog_languaget::typecheck(
182186
messaget message(message_handler);
183187
message.debug() << "Synthesis " << module << messaget::eom;
184188

185-
if(verilog_synthesis(symbol_table, module, message_handler, options))
189+
if(verilog_synthesis(
190+
symbol_table, module, parse_tree.standard, message_handler, options))
186191
return true;
187192

188193
return false;
@@ -289,8 +294,10 @@ bool verilog_languaget::to_expr(
289294

290295
std::istringstream i_preprocessed(code);
291296

297+
verilog_standardt standard = verilog_standardt::V2005;
298+
292299
// parsing
293-
verilog_parsert verilog_parser;
300+
verilog_parsert verilog_parser(standard);
294301

295302
verilog_parser.set_file("");
296303
verilog_parser.in=&i_preprocessed;
@@ -304,12 +311,12 @@ bool verilog_languaget::to_expr(
304311
expr.swap(verilog_parser.parse_tree.expr);
305312

306313
// typecheck it
307-
result = verilog_typecheck(expr, module, message_handler, ns);
314+
result = verilog_typecheck(expr, module, standard, message_handler, ns);
308315
if(result)
309316
return true;
310317

311318
// synthesize it
312-
result = verilog_synthesis(expr, module, message_handler, ns);
319+
result = verilog_synthesis(expr, module, standard, message_handler, ns);
313320
if(result)
314321
return true;
315322

src/verilog/verilog_language.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,8 @@ class verilog_languaget:public languaget
8787
}
8888

8989
optionst options;
90-
91-
verilog_languaget()
90+
91+
verilog_languaget() : parse_tree(verilog_standardt::NOT_SET)
9292
{
9393
options.set_option("flatten_hierarchy", true);
9494
}

src/verilog/verilog_parameterize_module.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -288,7 +288,8 @@ irep_idt verilog_typecheckt::parameterize_module(
288288

289289
// recursive call
290290

291-
verilog_typecheckt verilog_typecheck(*new_symbol, symbol_table, get_message_handler());
291+
verilog_typecheckt verilog_typecheck(
292+
standard, *new_symbol, symbol_table, get_message_handler());
292293

293294
if(verilog_typecheck.typecheck_main())
294295
throw 0;

src/verilog/verilog_parse_tree.h

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,16 +9,24 @@ Author: Daniel Kroening, [email protected]
99
#ifndef CPROVER_VERILOG_PARSE_TREE_H
1010
#define CPROVER_VERILOG_PARSE_TREE_H
1111

12-
#include <list>
13-
#include <set>
14-
1512
#include <util/string_hash.h>
1613

1714
#include "verilog_module.h"
15+
#include "verilog_standard.h"
16+
17+
#include <list>
18+
#include <set>
1819

1920
class verilog_parse_treet
2021
{
2122
public:
23+
explicit verilog_parse_treet(verilog_standardt _standard)
24+
: standard(_standard)
25+
{
26+
}
27+
28+
verilog_standardt standard;
29+
2230
class verilog_typedeft
2331
{
2432
public:
@@ -93,6 +101,7 @@ class verilog_parse_treet
93101
parse_tree.items.swap(items);
94102
parse_tree.expr.swap(expr);
95103
parse_tree.module_map.swap(module_map);
104+
std::swap(parse_tree.standard, standard);
96105
}
97106

98107
void modules_provided(

src/verilog/verilog_parser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,12 +29,12 @@ verilog_parsert *verilog_parser_ptr = nullptr;
2929
3030
\*******************************************************************/
3131

32-
bool parse_verilog_file(const std::string &filename)
32+
bool parse_verilog_file(const std::string &filename, verilog_standardt standard)
3333
{
3434
std::ifstream in(widen_if_needed(filename));
3535
console_message_handlert console_message_handler;
3636

37-
verilog_parsert verilog_parser;
37+
verilog_parsert verilog_parser(standard);
3838

3939
verilog_parser.set_file(filename);
4040
verilog_parser.log.set_message_handler(console_message_handler);

src/verilog/verilog_parser.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,14 +33,12 @@ class verilog_parsert:public parsert
3333
typedef enum { LANGUAGE, EXPRESSION, TYPE } grammart;
3434
grammart grammar;
3535

36-
verilog_standardt mode;
37-
3836
virtual bool parse()
3937
{
4038
return yyverilogparse()!=0;
4139
}
4240

43-
verilog_parsert() : mode(verilog_standardt::V2005_VIS)
41+
explicit verilog_parsert(verilog_standardt standard) : parse_tree(standard)
4442
{
4543
PRECONDITION(verilog_parser_ptr == nullptr);
4644
verilog_parser_ptr = this;
@@ -131,7 +129,7 @@ class verilog_parsert:public parsert
131129
}
132130
};
133131

134-
bool parse_verilog_file(const std::string &filename);
132+
bool parse_verilog_file(const std::string &filename, verilog_standardt);
135133
void verilog_scanner_init();
136134

137135
#endif

src/verilog/verilog_standard.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ Author: Daniel Kroening, [email protected]
1616
// Verilog that the Cadence SMV model checker accepts.
1717
enum class verilog_standardt
1818
{
19+
NOT_SET,
1920
V1995,
2021
V2001_NOCONFIG,
2122
V2001,

src/verilog/verilog_synthesis.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,8 @@ exprt verilog_synthesist::expand_function_call(const function_call_exprt &call)
334334
else
335335
{
336336
// Attempt to constant fold.
337-
verilog_typecheck_exprt verilog_typecheck_expr(ns, get_message_handler());
337+
verilog_typecheck_exprt verilog_typecheck_expr(
338+
standard, ns, get_message_handler());
338339
auto result =
339340
verilog_typecheck_expr.elaborate_constant_system_function_call(call);
340341
if(!result.is_constant())
@@ -1404,7 +1405,7 @@ void verilog_synthesist::synth_module_instance(
14041405

14051406
// make sure the module is synthesized already
14061407
verilog_synthesis(
1407-
symbol_table, module_identifier, get_message_handler(), options);
1408+
symbol_table, module_identifier, standard, get_message_handler(), options);
14081409

14091410
for(auto &instance : statement.instances())
14101411
expand_module_instance(module_symbol, instance, trans);
@@ -3496,12 +3497,13 @@ Function: verilog_synthesis
34963497
bool verilog_synthesis(
34973498
symbol_table_baset &symbol_table,
34983499
const irep_idt &module,
3500+
verilog_standardt standard,
34993501
message_handlert &message_handler,
35003502
const optionst &options)
35013503
{
35023504
const namespacet ns(symbol_table);
35033505
verilog_synthesist verilog_synthesis(
3504-
ns, symbol_table, module, options, message_handler);
3506+
standard, ns, symbol_table, module, options, message_handler);
35053507
return verilog_synthesis.typecheck_main();
35063508
}
35073509

@@ -3520,6 +3522,7 @@ Function: verilog_synthesis
35203522
bool verilog_synthesis(
35213523
exprt &expr,
35223524
const irep_idt &module_identifier,
3525+
verilog_standardt standard,
35233526
message_handlert &message_handler,
35243527
const namespacet &ns)
35253528
{
@@ -3530,7 +3533,7 @@ bool verilog_synthesis(
35303533
message_handler.get_message_count(messaget::M_ERROR);
35313534

35323535
verilog_synthesist verilog_synthesis(
3533-
ns, symbol_table, module_identifier, options, message_handler);
3536+
standard, ns, symbol_table, module_identifier, options, message_handler);
35343537

35353538
try
35363539
{

src/verilog/verilog_synthesis.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,15 +13,19 @@ Author: Daniel Kroening, [email protected]
1313
#include <util/options.h>
1414
#include <util/symbol_table_base.h>
1515

16+
#include "verilog_standard.h"
17+
1618
bool verilog_synthesis(
1719
symbol_table_baset &,
1820
const irep_idt &module,
21+
verilog_standardt,
1922
message_handlert &,
2023
const optionst &);
2124

2225
bool verilog_synthesis(
2326
exprt &,
2427
const irep_idt &module_identifier,
28+
verilog_standardt,
2529
message_handlert &,
2630
const namespacet &);
2731

src/verilog/verilog_synthesis_class.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,12 +41,13 @@ class verilog_synthesist:
4141
{
4242
public:
4343
verilog_synthesist(
44+
verilog_standardt _standard,
4445
const namespacet &_ns,
4546
symbol_table_baset &_symbol_table,
4647
const irep_idt &_module,
4748
const optionst &_options,
4849
message_handlert &_message_handler)
49-
: verilog_typecheck_baset(_ns, _message_handler),
50+
: verilog_typecheck_baset(_standard, _ns, _message_handler),
5051
verilog_symbol_tablet(_symbol_table),
5152
options(_options),
5253
value_map(NULL),

src/verilog/verilog_typecheck.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1746,7 +1746,10 @@ bool verilog_typecheck(
17461746
}
17471747

17481748
return verilog_typecheck(
1749-
symbol_table, it->second->verilog_module, message_handler);
1749+
symbol_table,
1750+
it->second->verilog_module,
1751+
parse_tree.standard,
1752+
message_handler);
17501753
}
17511754

17521755
/*******************************************************************\
@@ -1764,6 +1767,7 @@ Function: verilog_typecheck
17641767
bool verilog_typecheck(
17651768
symbol_table_baset &symbol_table,
17661769
const verilog_modulet &verilog_module,
1770+
verilog_standardt standard,
17671771
message_handlert &message_handler)
17681772
{
17691773
// create symbol
@@ -1793,6 +1797,7 @@ bool verilog_typecheck(
17931797
return true;
17941798
}
17951799

1796-
verilog_typecheckt verilog_typecheck(*new_symbol, symbol_table, message_handler);
1800+
verilog_typecheckt verilog_typecheck(
1801+
standard, *new_symbol, symbol_table, message_handler);
17971802
return verilog_typecheck.typecheck_main();
17981803
}

src/verilog/verilog_typecheck.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,13 @@ bool verilog_typecheck(
2828
bool verilog_typecheck(
2929
symbol_table_baset &,
3030
const verilog_modulet &verilog_module,
31+
verilog_standardt,
3132
message_handlert &message_handler);
3233

3334
bool verilog_typecheck(
3435
symbol_table_baset &,
3536
const std::string &module_identifier,
37+
verilog_standardt,
3638
const exprt::operandst &parameters,
3739
message_handlert &message_handler);
3840

@@ -54,10 +56,11 @@ class verilog_typecheckt:
5456
{
5557
public:
5658
verilog_typecheckt(
59+
verilog_standardt _standard,
5760
symbolt &_module_symbol,
5861
symbol_table_baset &_symbol_table,
5962
message_handlert &_message_handler)
60-
: verilog_typecheck_exprt(ns, _message_handler),
63+
: verilog_typecheck_exprt(_standard, ns, _message_handler),
6164
verilog_symbol_tablet(_symbol_table),
6265
ns(_symbol_table),
6366
module_symbol(_module_symbol),

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