Verilog: better diagnostics on procedural assignment to net

Author: kroening

regression/verilog/synthesis/procedural_assignment_to_net.desc

@@ -0,0 +1,8 @@
+CORE
+procedural_assignment_to_net.v
+
+^EXIT=2$
+^SIGNAL=0$
+^file procedural_assignment_to_net\.v line 6: procedural assignment to a net$
+^Identifier main\.some_net is declared as bool on line 3\.$
+--

regression/verilog/synthesis/procedural_assignment_to_net.v

@@ -0,0 +1,8 @@
+module main(input i);
+
+  wire some_net;
+
+  // should error
+  always @i some_net = i;
+
+endmodule

src/verilog/verilog_typecheck.cpp

@@ -802,7 +802,10 @@ void verilog_typecheckt::check_lhs(
          !symbol.is_lvalue)
       {
         throw errort().with_location(lhs.source_location())
-          << "assignment to non-register";
+          << "procedural assignment to a net\n"
+          << "Identifier " << symbol.display_name() << " is declared as "
+          << to_string(symbol.type) << " on line " << symbol.location.get_line()
+          << '.';
       }
 
       break;