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Merge pull request #512 from diffblue/continuous_assignment_to_variable_verilog
Verilog: KNOWNBUG test for continuous assignments to variables
2 parents d560cae + 39ca096 commit aa7caf5

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-4
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regression/verilog/synthesis/continuous_assignment_to_variable.desc renamed to regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog.desc

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CORE
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continuous_assignment_to_variable.v
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continuous_assignment_to_variable_systemverilog.sv
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--bound 0
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^\[main\.property\.p1\] always main\.some_reg == main\.i: PROVED up to bound 0$
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^EXIT=0$
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module main(input i);
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reg some_reg;
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// continuous assignments to variables are allowed in SystemVerilog
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assign some_reg = i;
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// should pass
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p1: assert property (some_reg == i);
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endmodule
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KNOWNBUG
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continuous_assignment_to_variable_verilog.v
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--
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--
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This should error.

regression/verilog/synthesis/continuous_assignment_to_variable.v renamed to regression/verilog/synthesis/continuous_assignment_to_variable_verilog.v

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reg some_reg;
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// continuous assignment to variables are not allowed in Verilog
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assign some_reg = i;
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// should pass
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always assert p1: some_reg == i;
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endmodule

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