Merge pull request #512 from diffblue/continuous_assignment_to_variable_verilog

Verilog: KNOWNBUG test for continuous assignments to variables

Author: tautschnig

regression/verilog/synthesis/continuous_assignment_to_variable.desc renamed to regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog.desc

@@ -1,5 +1,5 @@
 CORE
-continuous_assignment_to_variable.v
+continuous_assignment_to_variable_systemverilog.sv
 --bound 0
 ^\[main\.property\.p1\] always main\.some_reg == main\.i: PROVED up to bound 0$
 ^EXIT=0$

regression/verilog/synthesis/continuous_assignment_to_variable_systemverilog.sv

@@ -0,0 +1,11 @@
+module main(input i);
+
+  reg some_reg;
+
+  // continuous assignments to variables are allowed in SystemVerilog
+  assign some_reg = i;
+
+  // should pass
+  p1: assert property (some_reg == i);
+
+endmodule

regression/verilog/synthesis/continuous_assignment_to_variable_verilog.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+continuous_assignment_to_variable_verilog.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This should error.

regression/verilog/synthesis/continuous_assignment_to_variable.v renamed to regression/verilog/synthesis/continuous_assignment_to_variable_verilog.v

@@ -2,9 +2,7 @@ module main(input i);
 
   reg some_reg;
 
+  // continuous assignment to variables are not allowed in Verilog
   assign some_reg = i;
 
-  // should pass
-  always assert p1: some_reg == i;
-
 endmodule