Verilog: add two KNOWNBUG tests for arrays

Author: kroening

regression/verilog/arrays/packed_real1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+packed_real1.sv
+--module main --bound 0
+^EXIT=10$
+^SIGNAL=0$
+--
+--
+A packed array of reals must be rejected.

regression/verilog/arrays/packed_real1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // Packed arrays can be made of single bit data types
+  // or other packed types.
+  typedef real my_real;
+  my_real [7:0] my_array;
+
+endmodule
+

regression/verilog/arrays/packed_typedef1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+packed_typedef1.sv
+--module main --bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+The packed array type must not be dropped.

regression/verilog/arrays/packed_typedef1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  typedef bit my_bit;
+  my_bit [7:0] my_vector;
+
+  always assert p0: ($bits(my_vector) == 8);
+
+endmodule