Merge pull request #400 from diffblue/verilog-throw-0

tautschnig · web-flow · commit df2274a3d72d · 2024-03-10T18:53:45.000+01:00
Verilog: use `errort()` instead of `throw 0`
diff --git a/src/verilog/verilog_elaborate.cpp b/src/verilog/verilog_elaborate.cpp
@@ -433,10 +433,8 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
 
         if(osymbol.type.id() == ID_code)
         {
-          error().source_location = decl.source_location();
-          error() << "symbol `" << symbol.base_name << "' is already declared"
-                  << eom;
-          throw 0;
+          throw errort().with_location(decl.source_location())
+            << "symbol `" << symbol.base_name << "' is already declared";
         }
 
         // change of type?
@@ -895,9 +893,7 @@ void verilog_typecheckt::elaborate_symbol_rec(irep_idt identifier)
   }
   else if(symbol.type.id() == ID_elaborating)
   {
-    error().source_location = symbol.location;
-    error() << "cyclic dependency when elaborating " << symbol.display_name()
-            << eom;
-    throw 0;
+    throw errort().with_location(symbol.location)
+      << "cyclic dependency when elaborating " << symbol.display_name();
   }
 }
diff --git a/src/verilog/verilog_generate.cpp b/src/verilog/verilog_generate.cpp
@@ -135,9 +135,8 @@ void verilog_typecheckt::elaborate_generate_if(
   if(statement.operands().size()!=3 &&
      statement.operands().size()!=2)
   {
-    error().source_location = statement.source_location();
-    error() << "generate_if expects two or three operands" << eom;
-    throw 0;
+    throw errort().with_location(statement.source_location())
+      << "generate_if expects two or three operands";
   }
 
   mp_integer condition =
@@ -172,9 +171,8 @@ void verilog_typecheckt::elaborate_generate_assign(
 {
   if(statement.lhs().id() != ID_symbol)
   {
-    error().source_location = statement.lhs().source_location();
-    error() << "expected symbol on left hand side of assignment" << eom;
-    throw 0;
+    throw errort().with_location(statement.lhs().source_location())
+      << "expected symbol on left hand side of assignment";
   }
 
   const irep_idt &identifier = to_symbol_expr(statement.lhs()).get_identifier();
@@ -183,18 +181,16 @@ void verilog_typecheckt::elaborate_generate_assign(
   
   if(it==genvars.end())
   {
-    error().source_location = statement.lhs().source_location();
-    error() << "expected genvar on left hand side of assignment" << eom;
-    throw 0;
+    throw errort().with_location(statement.lhs().source_location())
+      << "expected genvar on left hand side of assignment";
   }
 
   mp_integer rhs = convert_integer_constant_expression(statement.rhs());
 
   if(rhs<0)
   {
-    error().source_location = statement.rhs().source_location();
-    error() << "must not assign negative value to genvar" << eom;
-    throw 0;
+    throw errort().with_location(statement.rhs().source_location())
+      << "must not assign negative value to genvar";
   }
   
   it->second=rhs;
@@ -222,9 +218,8 @@ exprt verilog_typecheckt::generate_for_loop_index(
   }
   else
   {
-    error().source_location = initialization_statement.source_location();
-    error() << "failed to determine generate loop index" << eom;
-    throw 0;
+    throw errort().with_location(initialization_statement.source_location())
+      << "failed to determine generate loop index";
   }
 }
 
diff --git a/src/verilog/verilog_interfaces.cpp b/src/verilog/verilog_interfaces.cpp
@@ -121,10 +121,8 @@ void verilog_typecheckt::check_module_ports(
     if(symbol.is_input || symbol.is_output)
       if(port_names.find(symbol.base_name)==port_names.end())
       {
-        error().source_location=symbol.location;
-        error() << "port `" << symbol.base_name
-                << "' not in port list" << eom;
-        throw 0;
+        throw errort().with_location(symbol.location)
+          << "port `" << symbol.base_name << "' not in port list";
       }
   }
 }
@@ -190,11 +188,9 @@ void verilog_typecheckt::interface_inst(
 
   if(symbol_table.add(symbol))
   {
-    error().source_location = op.source_location();
-    error() << "duplicate definition of identifier `" 
-            << symbol.base_name << "' in module `"
-            << module_symbol.base_name << '\'' << eom;
-    throw 0;
+    throw errort().with_location(op.source_location())
+      << "duplicate definition of identifier `" << symbol.base_name
+      << "' in module `" << module_symbol.base_name << '\'';
   }
 }
 
@@ -316,8 +312,8 @@ void verilog_typecheckt::interface_statement(
   {
     if(statement.operands().size()!=2)
     {
-      error() << "event_guard expected to have two operands" << eom;
-      throw 0;
+      throw errort().with_location(statement.source_location())
+        << "event_guard expected to have two operands";
     }
 
     interface_statement(
@@ -327,8 +323,8 @@ void verilog_typecheckt::interface_statement(
   {
     if(statement.operands().size()!=2)
     {
-      error() << "delay expected to have two operands" << eom;
-      throw 0;
+      throw errort().with_location(statement.source_location())
+        << "delay expected to have two operands";
     }
 
     interface_statement(
@@ -382,11 +378,9 @@ void verilog_typecheckt::interface_block(
 
     if(symbol_table.add(symbol))
     {
-      error().source_location = statement.source_location();
-      error() << "duplicate definition of identifier `" 
-              << symbol.base_name << "' in module `"
-              << module_symbol.base_name << '\'' << eom;
-      throw 0;
+      throw errort().with_location(statement.source_location())
+        << "duplicate definition of identifier `" << symbol.base_name
+        << "' in module `" << module_symbol.base_name << '\'';
     }
 
     enter_named_block(base_name);
diff --git a/src/verilog/verilog_interpreter.cpp b/src/verilog/verilog_interpreter.cpp
@@ -34,9 +34,8 @@ void verilog_typecheckt::verilog_interpreter(
     exprt rhs = elaborate_constant_expression(assign.rhs());
     if(!rhs.is_constant())
     {
-      error().source_location=assign.rhs().source_location();
-      error() << "right-hand side of assignment is not constant" << eom;
-      throw 0;
+      throw errort().with_location(assign.rhs().source_location())
+        << "right-hand side of assignment is not constant";
     }
 
     if(assign.lhs().id()==ID_symbol)
@@ -76,9 +75,8 @@ void verilog_typecheckt::verilog_interpreter(
 
         if(to_integer_non_constant(cond, cond_i))
         {
-          error().source_location=verilog_for.source_location();
-          error() << "for condition is not constant: " << cond.pretty() << eom;
-          throw 0;
+          throw errort().with_location(verilog_for.source_location())
+            << "for condition is not constant: " << cond.pretty();
         }
 
         if(cond_i==0) break;
@@ -90,9 +88,7 @@ void verilog_typecheckt::verilog_interpreter(
   }
   else
   {
-    error().source_location=statement.source_location();
-    error() << "Don't know how to interpret statement `"
-            << statement.id() << '\'' << eom;
-    throw 0;
+    throw errort().with_location(statement.source_location())
+      << "Don't know how to interpret statement `" << statement.id() << '\'';
   }
 }
diff --git a/src/verilog/verilog_parameterize_module.cpp b/src/verilog/verilog_parameterize_module.cpp
@@ -129,9 +129,8 @@ std::list<exprt> verilog_typecheckt::get_parameter_values(
 
     if(p_it!=parameter_assignment.end())
     {
-      error().source_location = p_it->source_location();
-      error() << "too many parameter assignments" << eom;
-      throw 0;
+      throw errort().with_location(p_it->source_location())
+        << "too many parameter assignments";
     }
   }
   
@@ -218,12 +217,8 @@ irep_idt verilog_typecheckt::parameterize_module(
     symbol_table.symbols.find(module_identifier);
   
   if(it==symbol_table.symbols.end())
-  {
-    error().source_location=location;
-    error() << "module not found" << eom;
-    throw 0;
-  }
-  
+    throw errort().with_location(location) << "module not found";
+
   const symbolt &base_symbol=it->second;
 
   auto parameter_values = get_parameter_values(
@@ -249,10 +244,9 @@ irep_idt verilog_typecheckt::parameterize_module(
       mp_integer i;
       if(to_integer_non_constant(pv, i))
       {
-        error().source_location = pv.source_location();
-        error() << "parameter value expected to be constant, but got `"
-                << to_string(pv) << "'" << eom;
-        throw 0;
+        throw errort().with_location(pv.source_location())
+          << "parameter value expected to be constant, but got `"
+          << to_string(pv) << "'";
       }
       else
         suffix += integer2string(i);
@@ -288,10 +282,8 @@ irep_idt verilog_typecheckt::parameterize_module(
 
   if(symbol_table.move(symbol, new_symbol))
   {
-    error().source_location=location;
-    error() << "duplicate definition of parameterized module "
-            << symbol.base_name << eom;
-    throw 0;
+    throw errort().with_location(location)
+      << "duplicate definition of parameterized module " << symbol.base_name;
   }
 
   // recursive call
diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp
@@ -1821,7 +1821,7 @@ bool verilog_typecheck(
     messaget message(message_handler);
     message.error() << "duplicate definition of module " 
                     << symbol.base_name << messaget::eom;
-    throw 0;
+    return true;
   }
 
   verilog_typecheckt verilog_typecheck(*new_symbol, symbol_table, message_handler);
diff --git a/src/verilog/verilog_typecheck_base.cpp b/src/verilog/verilog_typecheck_base.cpp
@@ -122,8 +122,8 @@ mp_integer verilog_typecheck_baset::array_size(const array_typet &type)
 
   if(!size_opt.has_value())
   {
-    error() << "failed to get array size of array type" << eom;
-    throw 0;
+    throw errort().with_location(type.source_location())
+      << "failed to get array size of array type";
   }
 
   return size_opt.value();
@@ -148,9 +148,8 @@ mp_integer verilog_typecheck_baset::array_offset(const array_typet &type)
   if(to_integer_non_constant(
        static_cast<const exprt &>(type.find(ID_offset)), offset))
   {
-    error() << "failed to get array offset of type `"
-            << type.id() << '\'' << eom;
-    throw 0;
+    throw errort().with_location(type.source_location())
+      << "failed to get array offset of type `" << type.id() << '\'';
   }
 
   return offset;
@@ -194,9 +193,8 @@ std::size_t verilog_typecheck_baset::get_width(const typet &type)
   else if(type.id() == ID_verilog_time)
     return 64;
 
-  error() << "type `" << type.id() << "' has unknown width"
-          << eom;
-  throw 0;
+  throw errort().with_location(type.source_location())
+    << "type `" << type.id() << "' has unknown width";
 }
 
 /*******************************************************************\
diff --git a/src/verilog/verilog_typecheck_type.cpp b/src/verilog/verilog_typecheck_type.cpp
@@ -182,8 +182,7 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
   }
   else
   {
-    error().source_location = source_location;
-    error() << "unexpected type: `" << src.id() << "'" << eom;
-    throw 0;
+    throw errort().with_location(source_location)
+      << "unexpected type: `" << src.id() << "'";
   }
 }

Original file line number	Diff line number	Diff line change
`@@ -433,10 +433,8 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)`
`433`	`433`
`434`	`434`	`if(osymbol.type.id() == ID_code)`
`435`	`435`	`{`
`436`		`- error().source_location = decl.source_location();`
`437`		- error() << "symbol `" << symbol.base_name << "' is already declared"
`438`		`- << eom;`
`439`		`- throw 0;`
	`436`	`+ throw errort().with_location(decl.source_location())`
	`437`	+ << "symbol `" << symbol.base_name << "' is already declared";
`440`	`438`	`}`
`441`	`439`
`442`	`440`	`// change of type?`
`@@ -895,9 +893,7 @@ void verilog_typecheckt::elaborate_symbol_rec(irep_idt identifier)`
`895`	`893`	`}`
`896`	`894`	`else if(symbol.type.id() == ID_elaborating)`
`897`	`895`	`{`
`898`		`- error().source_location = symbol.location;`
`899`		`- error() << "cyclic dependency when elaborating " << symbol.display_name()`
`900`		`- << eom;`
`901`		`- throw 0;`
	`896`	`+ throw errort().with_location(symbol.location)`
	`897`	`+ << "cyclic dependency when elaborating " << symbol.display_name();`
`902`	`898`	`}`
`903`	`899`	`}`
Original file line number	Diff line number	Diff line change
`@@ -135,9 +135,8 @@ void verilog_typecheckt::elaborate_generate_if(`
`135`	`135`	`if(statement.operands().size()!=3 &&`
`136`	`136`	`statement.operands().size()!=2)`
`137`	`137`	`{`
`138`		`- error().source_location = statement.source_location();`
`139`		`- error() << "generate_if expects two or three operands" << eom;`
`140`		`- throw 0;`
	`138`	`+ throw errort().with_location(statement.source_location())`
	`139`	`+ << "generate_if expects two or three operands";`
`141`	`140`	`}`
`142`	`141`
`143`	`142`	`mp_integer condition =`
`@@ -172,9 +171,8 @@ void verilog_typecheckt::elaborate_generate_assign(`
`172`	`171`	`{`
`173`	`172`	`if(statement.lhs().id() != ID_symbol)`
`174`	`173`	`{`
`175`		`- error().source_location = statement.lhs().source_location();`
`176`		`- error() << "expected symbol on left hand side of assignment" << eom;`
`177`		`- throw 0;`
	`174`	`+ throw errort().with_location(statement.lhs().source_location())`
	`175`	`+ << "expected symbol on left hand side of assignment";`
`178`	`176`	`}`
`179`	`177`
`180`	`178`	`const irep_idt &identifier = to_symbol_expr(statement.lhs()).get_identifier();`
`@@ -183,18 +181,16 @@ void verilog_typecheckt::elaborate_generate_assign(`
`183`	`181`
`184`	`182`	`if(it==genvars.end())`
`185`	`183`	`{`
`186`		`- error().source_location = statement.lhs().source_location();`
`187`		`- error() << "expected genvar on left hand side of assignment" << eom;`
`188`		`- throw 0;`
	`184`	`+ throw errort().with_location(statement.lhs().source_location())`
	`185`	`+ << "expected genvar on left hand side of assignment";`
`189`	`186`	`}`
`190`	`187`
`191`	`188`	`mp_integer rhs = convert_integer_constant_expression(statement.rhs());`
`192`	`189`
`193`	`190`	`if(rhs<0)`
`194`	`191`	`{`
`195`		`- error().source_location = statement.rhs().source_location();`
`196`		`- error() << "must not assign negative value to genvar" << eom;`
`197`		`- throw 0;`
	`192`	`+ throw errort().with_location(statement.rhs().source_location())`
	`193`	`+ << "must not assign negative value to genvar";`
`198`	`194`	`}`
`199`	`195`
`200`	`196`	`it->second=rhs;`
`@@ -222,9 +218,8 @@ exprt verilog_typecheckt::generate_for_loop_index(`
`222`	`218`	`}`
`223`	`219`	`else`
`224`	`220`	`{`
`225`		`- error().source_location = initialization_statement.source_location();`
`226`		`- error() << "failed to determine generate loop index" << eom;`
`227`		`- throw 0;`
	`221`	`+ throw errort().with_location(initialization_statement.source_location())`
	`222`	`+ << "failed to determine generate loop index";`
`228`	`223`	`}`
`229`	`224`	`}`
`230`	`225`
Original file line number	Diff line number	Diff line change
`@@ -121,10 +121,8 @@ void verilog_typecheckt::check_module_ports(`
`121`	`121`	`if(symbol.is_input \|\| symbol.is_output)`
`122`	`122`	`if(port_names.find(symbol.base_name)==port_names.end())`
`123`	`123`	`{`
`124`		`- error().source_location=symbol.location;`
`125`		- error() << "port `" << symbol.base_name
`126`		`- << "' not in port list" << eom;`
`127`		`- throw 0;`
	`124`	`+ throw errort().with_location(symbol.location)`
	`125`	+ << "port `" << symbol.base_name << "' not in port list";
`128`	`126`	`}`
`129`	`127`	`}`
`130`	`128`	`}`
`@@ -190,11 +188,9 @@ void verilog_typecheckt::interface_inst(`
`190`	`188`
`191`	`189`	`if(symbol_table.add(symbol))`
`192`	`190`	`{`
`193`		`- error().source_location = op.source_location();`
`194`		- error() << "duplicate definition of identifier `"
`195`		- << symbol.base_name << "' in module `"
`196`		`- << module_symbol.base_name << '\'' << eom;`
`197`		`- throw 0;`
	`191`	`+ throw errort().with_location(op.source_location())`
	`192`	+ << "duplicate definition of identifier `" << symbol.base_name
	`193`	+ << "' in module `" << module_symbol.base_name << '\'';
`198`	`194`	`}`
`199`	`195`	`}`
`200`	`196`
`@@ -316,8 +312,8 @@ void verilog_typecheckt::interface_statement(`
`316`	`312`	`{`
`317`	`313`	`if(statement.operands().size()!=2)`
`318`	`314`	`{`
`319`		`- error() << "event_guard expected to have two operands" << eom;`
`320`		`- throw 0;`
	`315`	`+ throw errort().with_location(statement.source_location())`
	`316`	`+ << "event_guard expected to have two operands";`
`321`	`317`	`}`
`322`	`318`
`323`	`319`	`interface_statement(`
`@@ -327,8 +323,8 @@ void verilog_typecheckt::interface_statement(`
`327`	`323`	`{`
`328`	`324`	`if(statement.operands().size()!=2)`
`329`	`325`	`{`
`330`		`- error() << "delay expected to have two operands" << eom;`
`331`		`- throw 0;`
	`326`	`+ throw errort().with_location(statement.source_location())`
	`327`	`+ << "delay expected to have two operands";`
`332`	`328`	`}`
`333`	`329`
`334`	`330`	`interface_statement(`
`@@ -382,11 +378,9 @@ void verilog_typecheckt::interface_block(`
`382`	`378`
`383`	`379`	`if(symbol_table.add(symbol))`
`384`	`380`	`{`
`385`		`- error().source_location = statement.source_location();`
`386`		- error() << "duplicate definition of identifier `"
`387`		- << symbol.base_name << "' in module `"
`388`		`- << module_symbol.base_name << '\'' << eom;`
`389`		`- throw 0;`
	`381`	`+ throw errort().with_location(statement.source_location())`
	`382`	+ << "duplicate definition of identifier `" << symbol.base_name
	`383`	+ << "' in module `" << module_symbol.base_name << '\'';
`390`	`384`	`}`
`391`	`385`
`392`	`386`	`enter_named_block(base_name);`
Original file line number	Diff line number	Diff line change
`@@ -34,9 +34,8 @@ void verilog_typecheckt::verilog_interpreter(`
`34`	`34`	`exprt rhs = elaborate_constant_expression(assign.rhs());`
`35`	`35`	`if(!rhs.is_constant())`
`36`	`36`	`{`
`37`		`- error().source_location=assign.rhs().source_location();`
`38`		`- error() << "right-hand side of assignment is not constant" << eom;`
`39`		`- throw 0;`
	`37`	`+ throw errort().with_location(assign.rhs().source_location())`
	`38`	`+ << "right-hand side of assignment is not constant";`
`40`	`39`	`}`
`41`	`40`
`42`	`41`	`if(assign.lhs().id()==ID_symbol)`
`@@ -76,9 +75,8 @@ void verilog_typecheckt::verilog_interpreter(`
`76`	`75`
`77`	`76`	`if(to_integer_non_constant(cond, cond_i))`
`78`	`77`	`{`
`79`		`- error().source_location=verilog_for.source_location();`
`80`		`- error() << "for condition is not constant: " << cond.pretty() << eom;`
`81`		`- throw 0;`
	`78`	`+ throw errort().with_location(verilog_for.source_location())`
	`79`	`+ << "for condition is not constant: " << cond.pretty();`
`82`	`80`	`}`
`83`	`81`
`84`	`82`	`if(cond_i==0) break;`
`@@ -90,9 +88,7 @@ void verilog_typecheckt::verilog_interpreter(`
`90`	`88`	`}`
`91`	`89`	`else`
`92`	`90`	`{`
`93`		`- error().source_location=statement.source_location();`
`94`		- error() << "Don't know how to interpret statement `"
`95`		`- << statement.id() << '\'' << eom;`
`96`		`- throw 0;`
	`91`	`+ throw errort().with_location(statement.source_location())`
	`92`	+ << "Don't know how to interpret statement `" << statement.id() << '\'';
`97`	`93`	`}`
`98`	`94`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1821,7 +1821,7 @@ bool verilog_typecheck(`
`1821`	`1821`	`messaget message(message_handler);`
`1822`	`1822`	`message.error() << "duplicate definition of module "`
`1823`	`1823`	`<< symbol.base_name << messaget::eom;`
`1824`		`- throw 0;`
	`1824`	`+ return true;`
`1825`	`1825`	`}`
`1826`	`1826`
`1827`	`1827`	`verilog_typecheckt verilog_typecheck(*new_symbol, symbol_table, message_handler);`
Original file line number	Diff line number	Diff line change
`@@ -122,8 +122,8 @@ mp_integer verilog_typecheck_baset::array_size(const array_typet &type)`
`122`	`122`
`123`	`123`	`if(!size_opt.has_value())`
`124`	`124`	`{`
`125`		`- error() << "failed to get array size of array type" << eom;`
`126`		`- throw 0;`
	`125`	`+ throw errort().with_location(type.source_location())`
	`126`	`+ << "failed to get array size of array type";`
`127`	`127`	`}`
`128`	`128`
`129`	`129`	`return size_opt.value();`
`@@ -148,9 +148,8 @@ mp_integer verilog_typecheck_baset::array_offset(const array_typet &type)`
`148`	`148`	`if(to_integer_non_constant(`
`149`	`149`	`static_cast<const exprt &>(type.find(ID_offset)), offset))`
`150`	`150`	`{`
`151`		- error() << "failed to get array offset of type `"
`152`		`- << type.id() << '\'' << eom;`
`153`		`- throw 0;`
	`151`	`+ throw errort().with_location(type.source_location())`
	`152`	+ << "failed to get array offset of type `" << type.id() << '\'';
`154`	`153`	`}`
`155`	`154`
`156`	`155`	`return offset;`
`@@ -194,9 +193,8 @@ std::size_t verilog_typecheck_baset::get_width(const typet &type)`
`194`	`193`	`else if(type.id() == ID_verilog_time)`
`195`	`194`	`return 64;`
`196`	`195`
`197`		- error() << "type `" << type.id() << "' has unknown width"
`198`		`- << eom;`
`199`		`- throw 0;`
	`196`	`+ throw errort().with_location(type.source_location())`
	`197`	+ << "type `" << type.id() << "' has unknown width";
`200`	`198`	`}`
`201`	`199`
`202`	`200`	`/*******************************************************************\`
Original file line number	Diff line number	Diff line change
`@@ -182,8 +182,7 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)`
`182`	`182`	`}`
`183`	`183`	`else`
`184`	`184`	`{`
`185`		`- error().source_location = source_location;`
`186`		- error() << "unexpected type: `" << src.id() << "'" << eom;
`187`		`- throw 0;`
	`185`	`+ throw errort().with_location(source_location)`
	`186`	+ << "unexpected type: `" << src.id() << "'";
`188`	`187`	`}`
`189`	`188`	`}`