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BMC: implement weak/strong sequences
This implements strong semantics for SVA sequences in the word-level BMC engine. Strong semantics are used with an explicit strong(...) operator or for SVA cover. The difference between weak and strong semantics arises in BMC when the sequence reaches the end of the unwinding: using weak semantics, the sequence matches, whereas using strong semantics the sequence does not.
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13 files changed

+175
-64
lines changed

13 files changed

+175
-64
lines changed

regression/verilog/SVA/cover_sequence2.desc

Lines changed: 6 additions & 5 deletions
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@@ -1,11 +1,12 @@
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KNOWNBUG
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CORE
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cover_sequence2.sv
3-
--bound 2
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^\[main\.p0\] cover \(main\.x == 2 ##1 main\.x == 3 ##1 main\.x == 100\): PROVED$
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^\[main\.p1\] cover \(main\.x == 98 ##1 main\.x == 99 ##1 main\.x == 100\): REFUTED up to bound 2$
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--bound 5
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^\[main\.p0\] cover \(main\.x == 2 ##1 main\.x == 3 ##1 main\.x == 100\): REFUTED up to bound 5$
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^\[main\.p1\] cover \(main\.x == 98 ##1 main\.x == 99 ##1 main\.x == 100\): REFUTED up to bound 5$
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^\[main\.p2\] cover \(main\.x == 3 ##1 main\.x == 4 ##1 main\.x == 5\): PROVED$
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^\[main\.p3\] cover \(main\.x == 4 ##1 main\.x == 5 ##1 main\.x == 6\): REFUTED up to bound 5$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
11-
Cover property p0 cannot ever hold, but is shown proven when using a small bound.
Lines changed: 9 additions & 3 deletions
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@@ -1,15 +1,21 @@
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module main(input clk);
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// count up
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reg [7:0] x = 0;
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int x = 0;
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always @(posedge clk)
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always_ff @(posedge clk)
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x++;
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// expected to fail
1010
p0: cover property (x==2 ##1 x==3 ##1 x==100);
1111

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// expected to fail until bound reaches 100
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// expected to fail until x reaches 100
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p1: cover property (x==98 ##1 x==99 ##1 x==100);
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// expected to pass once x reaches 5
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p2: cover property (x==3 ##1 x==4 ##1 x==5);
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// expected to pass once x reaches 6
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p3: cover property (x==4 ##1 x==5 ##1 x==6);
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1521
endmodule
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CORE
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cover_sequence3.sv
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--bound 3
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^\[main\.p0\] cover \(1 \[\*10\]\): REFUTED up to bound 3$
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^\[main\.p1\] cover \(1 \[\*4:10\]\): PROVED$
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^\[main\.p2\] cover \(1 \[\*5:10\]\): REFUTED up to bound 3$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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module main(input clk);
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// count up
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int x = 0;
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always_ff @(posedge clk)
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x++;
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// passes with bound >=9
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p0: cover property (1[*10]);
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// passes with bound >=3
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p1: cover property (1[*4:10]);
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// passes with bound >=4
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p2: cover property (1[*5:10]);
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endmodule
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KNOWNBUG
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cover_sequence4.sv
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--bound 3
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^\[main\.p0\] cover \(1 \[=10\]\): REFUTED up to bound 3$
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^\[main\.p1\] cover \(1 \[=4:10\]\): PROVED$
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^\[main\.p2\] cover \(1 \[=5:10\]\): REFUTED up to bound 3$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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Implementation of [=x:y] is missing.
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module main(input clk);
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// count up
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int x = 0;
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always_ff @(posedge clk)
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x++;
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// passes with bound >=9
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p0: cover property (1[=10]);
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// passes with bound >=3
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p1: cover property (1[=4:10]);
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// passes with bound >=4
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p2: cover property (1[=5:10]);
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endmodule

regression/verilog/SVA/sequence2.desc

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KNOWNBUG
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CORE
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sequence2.sv
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--bound 10 --numbered-trace
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^\[main\.p0] ##\[0:\$\] main\.x == 10: PROVED up to bound 10$
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^\[main\.p1] ##\[0:\$\] main\.x == 10: REFUTED$
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--bound 10
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^\[main\.p0] weak\(##\[0:\$\] main\.x == 10\): PROVED up to bound 10$
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^\[main\.p1] strong\(##\[0:\$\] main\.x == 10\): REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
1010
--
11-
strong(...) is missing.

regression/verilog/SVA/sequence3.desc

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KNOWNBUG
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CORE
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sequence3.sv
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--bound 20 --numbered-trace
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^\[main\.p0\] ##\[\*\] main\.x == 6: REFUTED$
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^\[main\.p1\] ##\[\*\] main\.x == 5: PROVED up to bound 20$
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^\[main\.p2\] ##\[\+\] main\.x == 0: REFUTED$
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^\[main\.p3\] ##\[\+\] main\.x == 5: PROVED up to bound 20$
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^\[main\.p0\] strong\(##\[\*\] main\.x == 6\): REFUTED$
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^\[main\.p1\] strong\(##\[\*\] main\.x == 5\): PROVED up to bound 20$
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^\[main\.p2\] strong\(##\[\+\] main\.x == 0\): REFUTED$
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^\[main\.p3\] strong\(##\[\+\] main\.x == 5\): PROVED up to bound 20$
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^EXIT=10$
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^SIGNAL=0$
1010
--
1111
^warning: ignoring
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--
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strong(...) is missing

regression/verilog/SVA/strong1.desc

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@@ -1,7 +1,7 @@
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CORE
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strong1.sv
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--bound 20
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^\[main\.p0\] strong\(##\[0:9\] main\.x == 100\): REFUTED$
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--bound 4
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^\[main\.p0\] strong\(##\[0:9\] main\.x == 5\): REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--

regression/verilog/SVA/strong1.sv

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@@ -8,7 +8,7 @@ module main;
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always @(posedge clk)
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x<=x+1;
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// fails
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initial p0: assert property (strong(##[0:9] x==100));
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// fails if bound is too low
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initial p0: assert property (strong(##[0:9] x==5));
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endmodule

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