@@ -34,6 +34,8 @@ version (MIPS32) version = MIPS_Any;
3434version (MIPS64 ) version = MIPS_Any;
3535version (PPC ) version = PPC_Any;
3636version (PPC64 ) version = PPC_Any;
37+ version (RISCV32 ) version = RISCV_Any;
38+ version (RISCV64 ) version = RISCV_Any;
3739version (S390 ) version = IBMZ_Any;
3840version (SPARC ) version = SPARC_Any;
3941version (SPARC64 ) version = SPARC_Any;
@@ -128,6 +130,12 @@ version (GNUFP)
128130 alias fenv_t = double ;
129131 alias fexcept_t = uint ;
130132 }
133+ // https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/riscv/bits/fenv.h
134+ else version (RISCV_Any)
135+ {
136+ alias fenv_t = uint ;
137+ alias fexcept_t = uint ;
138+ }
131139 // https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/sparc/fpu/bits/fenv.h
132140 else version (SPARC64 )
133141 {
@@ -639,6 +647,28 @@ else
639647 FE_DOWNWARD = 3 , // /
640648 }
641649 }
650+ else version (RISCV_Any)
651+ {
652+ // Define bits representing exceptions in the FPSR status word.
653+ enum
654+ {
655+ FE_INEXACT = 0x01 , // /
656+ FE_UNDERFLOW = 0x02 , // /
657+ FE_OVERFLOW = 0x04 , // /
658+ FE_DIVBYZERO = 0x08 , // /
659+ FE_INVALID = 0x10 , // /
660+ FE_ALL_EXCEPT = 0x1f , // /
661+ }
662+
663+ // Define bits representing rounding modes in the FPCR Rmode field.
664+ enum
665+ {
666+ FE_TONEAREST = 0x0 , // /
667+ FE_TOWARDZERO = 0x1 , // /
668+ FE_DOWNWARD = 0x2 , // /
669+ FE_UPWARD = 0x3 , // /
670+ }
671+ }
642672 else version (SPARC_Any)
643673 {
644674 // Define bits representing the exception.
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