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tensorNet.cpp
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/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "tensorNet.h"
#include "randInt8Calibrator.h"
#include "cudaMappedMemory.h"
#include "cudaResize.h"
#include "filesystem.h"
#if NV_TENSORRT_MAJOR < 10
#include "NvCaffeParser.h"
#include "NvUffParser.h"
#endif
#if NV_TENSORRT_MAJOR >= 5
#include "NvOnnxParser.h"
#include "NvInferPlugin.h"
#endif
#include <iostream>
#include <fstream>
#include <map>
#if NV_TENSORRT_MAJOR > 1
#define CREATE_INFER_BUILDER nvinfer1::createInferBuilder
#define CREATE_INFER_RUNTIME nvinfer1::createInferRuntime
#else
#define CREATE_INFER_BUILDER createInferBuilder
#define CREATE_INFER_RUNTIME createInferRuntime
#endif
#if NV_TENSORRT_MAJOR < 10
#define TRT_DESTROY(x) x->destroy()
#else
#define TRT_DESTROY(x) delete x
#endif
#define LOG_DOWNLOADER_TOOL " if loading a built-in model, maybe it wasn't downloaded before.\n\n" \
" Run the Model Downloader tool again and select it for download:\n\n" \
" $ cd <jetson-inference>/tools\n" \
" $ ./download-models.sh\n"
#define USE_INPUT_TENSOR_CUDA_DEVICE_MEMORY
#define CHECKSUM_TYPE "sha256sum"
//---------------------------------------------------------------------
const char* precisionTypeToStr( precisionType type )
{
switch(type)
{
case TYPE_DISABLED: return "DISABLED";
case TYPE_FASTEST: return "FASTEST";
case TYPE_FP32: return "FP32";
case TYPE_FP16: return "FP16";
case TYPE_INT8: return "INT8";
}
return nullptr;
}
precisionType precisionTypeFromStr( const char* str )
{
if( !str )
return TYPE_DISABLED;
for( int n=0; n < NUM_PRECISIONS; n++ )
{
if( strcasecmp(str, precisionTypeToStr((precisionType)n)) == 0 )
return (precisionType)n;
}
return TYPE_DISABLED;
}
static inline nvinfer1::DataType precisionTypeToTRT( precisionType type )
{
switch(type)
{
case TYPE_FP16: return nvinfer1::DataType::kHALF;
#if NV_TENSORRT_MAJOR >= 4
case TYPE_INT8: return nvinfer1::DataType::kINT8;
#endif
}
return nvinfer1::DataType::kFLOAT;
}
#if NV_TENSORRT_MAJOR >= 8
static inline bool isFp16Enabled( nvinfer1::IBuilderConfig* config )
{
return config->getFlag(nvinfer1::BuilderFlag::kFP16);
}
static inline bool isInt8Enabled( nvinfer1::IBuilderConfig* config )
{
return config->getFlag(nvinfer1::BuilderFlag::kINT8);
}
#else // NV_TENSORRT_MAJOR <= 7
static inline bool isFp16Enabled( nvinfer1::IBuilder* builder )
{
#if NV_TENSORRT_MAJOR < 4
return builder->getHalf2Mode();
#else
return builder->getFp16Mode();
#endif
}
static inline bool isInt8Enabled( nvinfer1::IBuilder* builder )
{
#if NV_TENSORRT_MAJOR >= 4
return builder->getInt8Mode();
#else
return false;
#endif
}
#endif
#if NV_TENSORRT_MAJOR >= 4
static inline const char* dataTypeToStr( nvinfer1::DataType type )
{
switch(type)
{
case nvinfer1::DataType::kFLOAT: return "FP32";
case nvinfer1::DataType::kHALF: return "FP16";
case nvinfer1::DataType::kINT8: return "INT8";
case nvinfer1::DataType::kINT32: return "INT32";
}
LogWarning(LOG_TRT "warning -- unknown nvinfer1::DataType (%i)\n", (int)type);
return "UNKNOWN";
}
#if NV_TENSORRT_MAJOR <= 7
static inline const char* dimensionTypeToStr( nvinfer1::DimensionType type )
{
switch(type)
{
case nvinfer1::DimensionType::kSPATIAL: return "SPATIAL";
case nvinfer1::DimensionType::kCHANNEL: return "CHANNEL";
case nvinfer1::DimensionType::kINDEX: return "INDEX";
case nvinfer1::DimensionType::kSEQUENCE: return "SEQUENCE";
}
LogWarning(LOG_TRT "warning -- unknown nvinfer1::DimensionType (%i)\n", (int)type);
return "UNKNOWN";
}
#endif
#endif
#if NV_TENSORRT_MAJOR > 1
static inline nvinfer1::Dims validateDims( const nvinfer1::Dims& dims )
{
if( dims.nbDims == nvinfer1::Dims::MAX_DIMS )
return dims;
nvinfer1::Dims dims_out = dims;
// TRT doesn't set the higher dims, so make sure they are 1
for( int n=dims_out.nbDims; n < nvinfer1::Dims::MAX_DIMS; n++ )
dims_out.d[n] = 1;
return dims_out;
}
static inline void copyDims( Dims3* dest, const nvinfer1::Dims* src )
{
for( int n=0; n < src->nbDims; n++ )
dest->d[n] = src->d[n];
dest->nbDims = src->nbDims;
}
static inline size_t sizeDims( const nvinfer1::Dims& dims, const size_t elementSize=1 )
{
size_t sz = dims.d[0];
for ( int n=1; n < dims.nbDims; n++ )
sz *= dims.d[n];
return sz * elementSize;
}
#else
static inline nvinfer1::Dims3 validateDims( const nvinfer1::Dims3& dims )
{
nvinfer1::Dims3 out = dims;
if( DIMS_C(out) == 0 )
DIMS_C(out) = 1;
if( DIMS_H(out) == 0 )
DIMS_H(out) = 1;
if( DIMS_W(out) == 0 )
DIMS_W(out) = 1;
return out;
}
static inline void copyDims( Dims3* dest, const nvinfer1::Dims3* src )
{
memcpy(dest, src, sizeof(nvinfer1::Dims));
}
static inline size_t sizeDims( const Dims3& dims, const size_t elementSize=1 )
{
return DIMS_C(dims) * DIMS_H(dims) * DIMS_W(dims) * elementSize;
}
#endif
#if NV_TENSORRT_MAJOR >= 7
static inline nvinfer1::Dims shiftDims( const nvinfer1::Dims& dims )
{
// TensorRT 7.0 requires EXPLICIT_BATCH flag for ONNX models,
// which adds a batch dimension (4D NCHW), whereas historically
// 3D CHW was expected. Remove the batch dim (it is typically 1)
nvinfer1::Dims out = dims;
/*out.d[0] = dims.d[1];
out.d[1] = dims.d[2];
out.d[2] = dims.d[3];
out.d[3] = 1;*/
if( dims.nbDims == 1 )
return out;
for( int n=0; n < dims.nbDims; n++ )
out.d[n] = dims.d[n+1];
for( int n=dims.nbDims; n < nvinfer1::Dims::MAX_DIMS; n++ )
out.d[n] = 1;
out.nbDims -= 1;
return out;
}
#endif
const char* deviceTypeToStr( deviceType type )
{
switch(type)
{
case DEVICE_GPU: return "GPU";
case DEVICE_DLA_0: return "DLA_0";
case DEVICE_DLA_1: return "DLA_1";
}
return nullptr;
}
deviceType deviceTypeFromStr( const char* str )
{
if( !str )
return DEVICE_GPU;
for( int n=0; n < NUM_DEVICES; n++ )
{
if( strcasecmp(str, deviceTypeToStr((deviceType)n)) == 0 )
return (deviceType)n;
}
if( strcasecmp(str, "DLA") == 0 )
return DEVICE_DLA;
return DEVICE_GPU;
}
#if NV_TENSORRT_MAJOR >= 5
static inline nvinfer1::DeviceType deviceTypeToTRT( deviceType type )
{
switch(type)
{
case DEVICE_GPU: return nvinfer1::DeviceType::kGPU;
//case DEVICE_DLA: return nvinfer1::DeviceType::kDLA;
#if NV_TENSORRT_MAJOR == 5 && NV_TENSORRT_MINOR == 0 && NV_TENSORRT_PATCH == 0
case DEVICE_DLA_0: return nvinfer1::DeviceType::kDLA0;
case DEVICE_DLA_1: return nvinfer1::DeviceType::kDLA1;
#else
case DEVICE_DLA_0: return nvinfer1::DeviceType::kDLA;
case DEVICE_DLA_1: return nvinfer1::DeviceType::kDLA;
#endif
default: return nvinfer1::DeviceType::kGPU;
}
}
#endif
const char* modelTypeToStr( modelType format )
{
switch(format)
{
case MODEL_CUSTOM: return "custom";
case MODEL_CAFFE: return "caffe";
case MODEL_ONNX: return "ONNX";
case MODEL_UFF: return "UFF";
case MODEL_ENGINE: return "engine";
}
return nullptr;
}
modelType modelTypeFromStr( const char* str )
{
if( !str )
return MODEL_CUSTOM;
if( strcasecmp(str, "caffemodel") == 0 || strcasecmp(str, "caffe") == 0 )
return MODEL_CAFFE;
else if( strcasecmp(str, "onnx") == 0 )
return MODEL_ONNX;
else if( strcasecmp(str, "uff") == 0 )
return MODEL_UFF;
else if( strcasecmp(str, "engine") == 0 || strcasecmp(str, "plan") == 0 || strcasecmp(str, "trt") == 0 )
return MODEL_ENGINE;
return MODEL_CUSTOM;
}
modelType modelTypeFromPath( const char* path )
{
if( !path )
return MODEL_CUSTOM;
return modelTypeFromStr(fileExtension(path).c_str());
}
const char* profilerQueryToStr( profilerQuery query )
{
switch(query)
{
case PROFILER_PREPROCESS: return "Pre-Process";
case PROFILER_NETWORK: return "Network";
case PROFILER_POSTPROCESS: return "Post-Process";
case PROFILER_VISUALIZE: return "Visualize";
case PROFILER_TOTAL: return "Total";
}
return nullptr;
}
//---------------------------------------------------------------------
tensorNet::Logger tensorNet::gLogger;
// constructor
tensorNet::tensorNet()
{
mEngine = NULL;
mInfer = NULL;
mContext = NULL;
mStream = NULL;
mBindings = NULL;
mMaxBatchSize = 0;
mEnableDebug = false;
mEnableProfiler = false;
mModelType = MODEL_CUSTOM;
mPrecision = TYPE_FASTEST;
mDevice = DEVICE_GPU;
mAllowGPUFallback = false;
mProfilerQueriesUsed = 0;
mProfilerQueriesDone = 0;
memset(mEventsCPU, 0, sizeof(mEventsCPU));
memset(mEventsGPU, 0, sizeof(mEventsGPU));
memset(mProfilerTimes, 0, sizeof(mProfilerTimes));
#if NV_TENSORRT_MAJOR > 5
mWorkspaceSize = 32 << 20;
#else
mWorkspaceSize = 16 << 20;
#endif
}
// Destructor
tensorNet::~tensorNet()
{
if( mContext != NULL )
{
TRT_DESTROY(mContext);
mContext = NULL;
}
if( mEngine != NULL )
{
TRT_DESTROY(mEngine);
mEngine = NULL;
}
if( mInfer != NULL )
{
TRT_DESTROY(mInfer);
mInfer = NULL;
}
for( size_t n=0; n < mInputs.size(); n++ )
{
#ifdef USE_INPUT_TENSOR_CUDA_DEVICE_MEMORY
CUDA_FREE(mInputs[n].CUDA);
#else
CUDA_FREE_HOST(mInputs[n].CUDA);
#endif
}
for( size_t n=0; n < mOutputs.size(); n++ )
CUDA_FREE_HOST(mOutputs[n].CPU);
free(mBindings);
}
// EnableProfiler
void tensorNet::EnableLayerProfiler()
{
mEnableProfiler = true;
if( mContext != NULL )
mContext->setProfiler(&gProfiler);
}
// EnableDebug
void tensorNet::EnableDebug()
{
mEnableDebug = true;
}
// DetectNativePrecisions()
std::vector<precisionType> tensorNet::DetectNativePrecisions( deviceType device )
{
std::vector<precisionType> types;
Logger logger;
// create a temporary builder for querying the supported types
nvinfer1::IBuilder* builder = CREATE_INFER_BUILDER(logger);
if( !builder )
{
LogError(LOG_TRT "DetectNativePrecisions() failed to create TensorRT IBuilder instance\n");
return types;
}
#if NV_TENSORRT_MAJOR >= 5 && NV_TENSORRT_MAJOR <= 7
if( device == DEVICE_DLA_0 || device == DEVICE_DLA_1 )
builder->setFp16Mode(true);
builder->setDefaultDeviceType( deviceTypeToTRT(device) );
#endif
// FP32 is supported on all platforms
types.push_back(TYPE_FP32);
// detect fast (native) FP16
if( builder->platformHasFastFp16() )
types.push_back(TYPE_FP16);
#if NV_TENSORRT_MAJOR >= 4
// detect fast (native) INT8
if( builder->platformHasFastInt8() )
types.push_back(TYPE_INT8);
#endif
// print out supported precisions (optional)
const uint32_t numTypes = types.size();
LogVerbose(LOG_TRT "native precisions detected for %s: ", deviceTypeToStr(device));
for( uint32_t n=0; n < numTypes; n++ )
{
LogVerbose("%s", precisionTypeToStr(types[n]));
if( n < numTypes - 1 )
LogVerbose(", ");
}
LogVerbose("\n");
TRT_DESTROY(builder);
return types;
}
// DetectNativePrecision
bool tensorNet::DetectNativePrecision( const std::vector<precisionType>& types, precisionType type )
{
const uint32_t numTypes = types.size();
for( uint32_t n=0; n < numTypes; n++ )
{
if( types[n] == type )
return true;
}
return false;
}
// DetectNativePrecision
bool tensorNet::DetectNativePrecision( precisionType precision, deviceType device )
{
std::vector<precisionType> types = DetectNativePrecisions(device);
return DetectNativePrecision(types, precision);
}
// SelectPrecision
precisionType tensorNet::SelectPrecision( precisionType precision, deviceType device, bool allowInt8 )
{
LogVerbose(LOG_TRT "desired precision specified for %s: %s\n", deviceTypeToStr(device), precisionTypeToStr(precision));
if( precision == TYPE_DISABLED )
{
LogWarning(LOG_TRT "skipping network specified with precision TYPE_DISABLE\n");
LogWarning(LOG_TRT "please specify a valid precision to create the network\n");
}
else if( precision == TYPE_FASTEST )
{
if( !allowInt8 )
LogWarning(LOG_TRT "requested fasted precision for device %s without providing valid calibrator, disabling INT8\n", deviceTypeToStr(device));
precision = FindFastestPrecision(device, allowInt8);
LogVerbose(LOG_TRT "selecting fastest native precision for %s: %s\n", deviceTypeToStr(device), precisionTypeToStr(precision));
}
else
{
if( !DetectNativePrecision(precision, device) )
{
LogWarning(LOG_TRT "precision %s is not supported for device %s\n", precisionTypeToStr(precision), deviceTypeToStr(device));
precision = FindFastestPrecision(device, allowInt8);
LogWarning(LOG_TRT "falling back to fastest precision for device %s (%s)\n", deviceTypeToStr(device), precisionTypeToStr(precision));
}
if( precision == TYPE_INT8 && !allowInt8 )
LogWarning(LOG_TRT "warning: device %s using INT8 precision with RANDOM calibration\n", deviceTypeToStr(device));
}
return precision;
}
// FindFastestPrecision
precisionType tensorNet::FindFastestPrecision( deviceType device, bool allowInt8 )
{
std::vector<precisionType> types = DetectNativePrecisions(device);
if( allowInt8 && DetectNativePrecision(types, TYPE_INT8) )
return TYPE_INT8;
else if( DetectNativePrecision(types, TYPE_FP16) )
return TYPE_FP16;
else
return TYPE_FP32;
}
// Create an optimized GIE network from caffe prototxt and model file
bool tensorNet::ProfileModel(const std::string& deployFile, // name for caffe prototxt
const std::string& modelFile, // name for model
const std::vector<std::string>& inputs,
const std::vector<Dims3>& inputDims,
const std::vector<std::string>& outputs, // network outputs
unsigned int maxBatchSize, // batch size - NB must be at least as large as the batch we want to run with
precisionType precision,
deviceType device, bool allowGPUFallback,
nvinfer1::IInt8Calibrator* calibrator,
char** engineStream, size_t* engineSize) // output stream for the GIE model
{
if( !engineStream || !engineSize )
return false;
// create builder and network definition interfaces
nvinfer1::IBuilder* builder = CREATE_INFER_BUILDER(gLogger);
#if NV_TENSORRT_MAJOR >= 8
nvinfer1::INetworkDefinition* network = builder->createNetworkV2(0);
#else
nvinfer1::INetworkDefinition* network = builder->createNetwork();
#endif
LogInfo(LOG_TRT "device %s, loading %s %s\n", deviceTypeToStr(device), deployFile.c_str(), modelFile.c_str());
// parse the different types of model formats
if( mModelType == MODEL_CAFFE )
{
#if NV_TENSORRT_MAJOR < 10
// parse the caffe model to populate the network, then set the outputs
nvcaffeparser1::ICaffeParser* parser = nvcaffeparser1::createCaffeParser();
nvinfer1::DataType modelDataType = (precision == TYPE_FP16) ? nvinfer1::DataType::kHALF : nvinfer1::DataType::kFLOAT; // import INT8 weights as FP32
const nvcaffeparser1::IBlobNameToTensor* blobNameToTensor =
parser->parse(deployFile.c_str(), // caffe deploy file
modelFile.c_str(), // caffe model file
*network, // network definition that the parser will populate
modelDataType);
if( !blobNameToTensor )
{
LogError(LOG_TRT "device %s, failed to parse caffe network\n", deviceTypeToStr(device));
return false;
}
// the caffe file has no notion of outputs, so we need to manually say which tensors the engine should generate
const size_t num_outputs = outputs.size();
for( size_t n=0; n < num_outputs; n++ )
{
nvinfer1::ITensor* tensor = blobNameToTensor->find(outputs[n].c_str());
if( !tensor )
{
LogError(LOG_TRT "failed to retrieve tensor for Output \"%s\"\n", outputs[n].c_str());
}
else
{
#if NV_TENSORRT_MAJOR >= 4
nvinfer1::Dims3 dims = static_cast<nvinfer1::Dims3&&>(tensor->getDimensions());
LogVerbose(LOG_TRT "retrieved Output tensor \"%s\": %ix%ix%i\n", tensor->getName(), dims.d[0], dims.d[1], dims.d[2]);
#endif
}
network->markOutput(*tensor);
}
//parser->destroy();
#else
LogError(LOG_TRT "TensorRT %i.%i does not support legacy caffe models\n", NV_TENSORRT_MAJOR, NV_TENSORRT_MINOR);
return false;
#endif
}
#if NV_TENSORRT_MAJOR >= 5
else if( mModelType == MODEL_ONNX )
{
#if NV_TENSORRT_MAJOR >= 7
TRT_DESTROY(network);
network = builder->createNetworkV2(1U << (uint32_t)nvinfer1::NetworkDefinitionCreationFlag::kEXPLICIT_BATCH);
if( !network )
{
LogError(LOG_TRT "IBuilder::createNetworkV2(EXPLICIT_BATCH) failed\n");
return false;
}
#endif
nvonnxparser::IParser* parser = nvonnxparser::createParser(*network, gLogger);
if( !parser )
{
LogError(LOG_TRT "failed to create nvonnxparser::IParser instance\n");
return false;
}
#if NV_TENSORRT_MAJOR == 5 && NV_TENSORRT_MINOR == 0
const int parserLogLevel = (int)nvinfer1::ILogger::Severity::kINFO;
#else
const int parserLogLevel = (int)nvinfer1::ILogger::Severity::kVERBOSE;
#endif
if( !parser->parseFromFile(modelFile.c_str(), parserLogLevel) )
{
LogError(LOG_TRT "failed to parse ONNX model '%s'\n", modelFile.c_str());
return false;
}
//parser->destroy();
}
else if( mModelType == MODEL_UFF )
{
#if NV_TENSORRT_MAJOR < 10
// create parser instance
nvuffparser::IUffParser* parser = nvuffparser::createUffParser();
if( !parser )
{
LogError(LOG_TRT "failed to create UFF parser\n");
return false;
}
// register inputs
const size_t numInputs = inputs.size();
for( size_t n=0; n < numInputs; n++ )
{
if( !parser->registerInput(inputs[n].c_str(), inputDims[n], nvuffparser::UffInputOrder::kNCHW) )
{
LogError(LOG_TRT "failed to register input '%s' for UFF model '%s'\n", inputs[n].c_str(), modelFile.c_str());
return false;
}
}
// register outputs
/*const size_t numOutputs = outputs.size();
for( uint32_t n=0; n < numOutputs; n++ )
{
if( !parser->registerOutput(outputs[n].c_str()) )
printf(LOG_TRT "failed to register output '%s' for UFF model '%s'\n", outputs[n].c_str(), modelFile.c_str());
}*/
// UFF outputs are forwarded to 'MarkOutput_0'
if( !parser->registerOutput("MarkOutput_0") )
LogError(LOG_TRT "failed to register output '%s' for UFF model '%s'\n", "MarkOutput_0", modelFile.c_str());
// parse network
if( !parser->parse(modelFile.c_str(), *network, nvinfer1::DataType::kFLOAT) )
{
LogError(LOG_TRT "failed to parse UFF model '%s'\n", modelFile.c_str());
return false;
}
//parser->destroy();
#else
LogError(LOG_TRT "TensorRT %i.%i does not support legacy caffe models\n", NV_TENSORRT_MAJOR, NV_TENSORRT_MINOR);
return false;
#endif
}
#endif
#if NV_TENSORRT_MAJOR >= 4
if( precision == TYPE_INT8 && !calibrator )
{
// extract the dimensions of the network input blobs
std::map<std::string, nvinfer1::Dims3> inputDimensions;
for( int i=0, n=network->getNbInputs(); i < n; i++ )
{
nvinfer1::Dims dims = network->getInput(i)->getDimensions();
#if NV_TENSORRT_MAJOR >= 7
if( mModelType == MODEL_ONNX )
dims = shiftDims(dims); // change NCHW to CHW for EXPLICIT_BATCH
#endif
//nvinfer1::Dims3 dims = static_cast<nvinfer1::Dims3&&>(network->getInput(i)->getDimensions());
inputDimensions.insert(std::make_pair(network->getInput(i)->getName(), static_cast<nvinfer1::Dims3&&>(dims)));
LogVerbose(LOG_TRT "retrieved Input tensor '%s': %ix%ix%i\n", network->getInput(i)->getName(), dims.d[0], dims.d[1], dims.d[2]);
}
// default to random calibration
calibrator = new randInt8Calibrator(1, mCacheCalibrationPath, inputDimensions);
LogWarning(LOG_TRT "warning: device %s using INT8 precision with RANDOM calibration\n", deviceTypeToStr(device));
}
#endif
// configure the builder
#if NV_TENSORRT_MAJOR >= 8
nvinfer1::IBuilderConfig* builderConfig = builder->createBuilderConfig();
if( !ConfigureBuilder(builder, builderConfig, maxBatchSize, mWorkspaceSize,
precision, device, allowGPUFallback, calibrator) )
{
LogError(LOG_TRT "device %s, failed to configure builder\n", deviceTypeToStr(device));
return false;
}
// attempt to load the timing cache
const nvinfer1::ITimingCache* timingCache = NULL;
char timingCachePath[PATH_MAX];
sprintf(timingCachePath, "/usr/local/bin/networks/tensorrt.%i.timingcache", NV_TENSORRT_VERSION);
if( fileExists(timingCachePath) )
{
LogInfo(LOG_TRT "loading timing cache from %s\n", timingCachePath);
void* timingCacheBuffer = NULL;
const size_t timingCacheSize = loadFile(timingCachePath, &timingCacheBuffer);
if( timingCacheSize > 0 )
{
timingCache = builderConfig->createTimingCache(timingCacheBuffer, timingCacheSize);
free(timingCacheBuffer);
}
}
if( !timingCache )
{
timingCache = builderConfig->createTimingCache(NULL, 0); // create a new cache
if( !timingCache )
LogWarning(LOG_TRT "couldn't create new timing cache\n");
}
if( timingCache != NULL && !builderConfig->setTimingCache(*timingCache, false) )
LogWarning(LOG_TRT "failed to activate timing cache");
#else
if( !ConfigureBuilder(builder, maxBatchSize, mWorkspaceSize, precision, device, allowGPUFallback, calibrator) )
{
LogError(LOG_TRT "device %s, failed to configure builder\n", deviceTypeToStr(device));
return false;
}
#endif
// build CUDA engine
LogInfo(LOG_TRT "device %s, building CUDA engine (this may take a few minutes the first time a network is loaded)\n", deviceTypeToStr(device));
if( Log::GetLevel() < Log::VERBOSE )
LogInfo(LOG_TRT "info: to see status updates during engine building, enable verbose logging with --verbose\n");
#if NV_TENSORRT_MAJOR >= 10
nvinfer1::IHostMemory* serMem = builder->buildSerializedNetwork(*network, *builderConfig);
#else
#if NV_TENSORRT_MAJOR >= 8
nvinfer1::ICudaEngine* engine = builder->buildEngineWithConfig(*network, *builderConfig);
#else
nvinfer1::ICudaEngine* engine = builder->buildCudaEngine(*network);
#endif
if( !engine )
{
LogError(LOG_TRT "device %s, failed to build CUDA engine\n", deviceTypeToStr(device));
return false;
}
LogSuccess(LOG_TRT "device %s, completed building CUDA engine\n", deviceTypeToStr(device));
#endif
#if NV_TENSORRT_MAJOR >= 8
if( timingCache != NULL )
{
// save the updated timing cache
nvinfer1::IHostMemory* timingCacheMem = timingCache->serialize();
if( timingCacheMem != NULL )
{
const char* timingCacheBuffer = (char*)timingCacheMem->data();
const size_t timingCacheSize = timingCacheMem->size();
LogVerbose(LOG_TRT "saving timing cache to %s (%zu bytes)\n", timingCachePath, timingCacheSize);
// write the cache file
FILE* timingCacheFile = NULL;
timingCacheFile = fopen(timingCachePath, "wb");
if( timingCacheFile != NULL )
{
if( fwrite(timingCacheBuffer, 1, timingCacheSize, timingCacheFile) != timingCacheSize )
LogWarning(LOG_TRT "failed to write %zu bytes to timing cache file %s\n", timingCacheSize, timingCachePath);
fclose(timingCacheFile);
}
else
{
LogWarning(LOG_TRT "failed to open timing cache file for writing %s\n", timingCachePath);
}
TRT_DESTROY(timingCacheMem);
}
delete timingCache;
}
TRT_DESTROY(builderConfig);
#endif
// we don't need the network definition any more, and we can destroy the parser
TRT_DESTROY(network);
//parser->destroy();
#if NV_TENSORRT_MAJOR >= 2
#if NV_TENSORRT_MAJOR < 10
nvinfer1::IHostMemory* serMem = engine->serialize(); // serialize the engine
#endif
if( !serMem )
{
LogError(LOG_TRT "device %s, failed to serialize CUDA engine\n", deviceTypeToStr(device));
return false;
}
const char* serData = (char*)serMem->data();
const size_t serSize = serMem->size();
// allocate memory to store the bitstream
char* engineMemory = (char*)malloc(serSize);
if( !engineMemory )
{
LogError(LOG_TRT "failed to allocate %zu bytes to store CUDA engine\n", serSize);
return false;
}
memcpy(engineMemory, serData, serSize);
*engineStream = engineMemory;
*engineSize = serSize;
TRT_DESTROY(serMem);
#else
engine->serialize(modelStream);
#endif
#if NV_TENSORRT_MAJOR < 10
TRT_DESTROY(engine);
#endif
TRT_DESTROY(builder);
return true;
}
// ConfigureBuilder
#if NV_TENSORRT_MAJOR >= 8
bool tensorNet::ConfigureBuilder( nvinfer1::IBuilder* builder, nvinfer1::IBuilderConfig* config,
uint32_t maxBatchSize, uint32_t workspaceSize, precisionType precision,
deviceType device, bool allowGPUFallback,
nvinfer1::IInt8Calibrator* calibrator )
{
if( !builder )
return false;
LogVerbose(LOG_TRT "device %s, configuring network builder\n", deviceTypeToStr(device));
#if NV_TENSORRT_MAJOR < 10
builder->setMaxBatchSize(maxBatchSize);
config->setMaxWorkspaceSize(workspaceSize); // config->setMemoryPoolLimit(MemoryPoolType::kWORKSPACE) in TRT10 - but now already defaults to the max
config->setMinTimingIterations(3); // allow time for GPU to spin up
#endif
config->setAvgTimingIterations(2);
if( mEnableDebug )
config->setFlag(nvinfer1::BuilderFlag::kDEBUG);
// set up the builder for the desired precision
if( precision == TYPE_INT8 )
{
config->setFlag(nvinfer1::BuilderFlag::kINT8);
//config->setFlag(nvinfer1::BuilderFlag::kFP16); // TODO: experiment for benefits of both INT8/FP16
if( !calibrator )
{
LogError(LOG_TRT "device %s, INT8 requested but calibrator is NULL\n", deviceTypeToStr(device));
return false;
}
config->setInt8Calibrator(calibrator);
}
else if( precision == TYPE_FP16 )
{
config->setFlag(nvinfer1::BuilderFlag::kFP16);
}
// set the default device type
config->setDefaultDeviceType(deviceTypeToTRT(device));
if( allowGPUFallback )
config->setFlag(nvinfer1::BuilderFlag::kGPU_FALLBACK);
LogInfo(LOG_TRT "device %s, building FP16: %s\n", deviceTypeToStr(device), isFp16Enabled(config) ? "ON" : "OFF");
LogInfo(LOG_TRT "device %s, building INT8: %s\n", deviceTypeToStr(device), isInt8Enabled(config) ? "ON" : "OFF");
LogInfo(LOG_TRT "device %s, workspace size: %u\n", deviceTypeToStr(device), workspaceSize);
return true;
}
#else // NV_TENSORRT_MAJOR <= 7
bool tensorNet::ConfigureBuilder( nvinfer1::IBuilder* builder, uint32_t maxBatchSize,
uint32_t workspaceSize, precisionType precision,
deviceType device, bool allowGPUFallback,
nvinfer1::IInt8Calibrator* calibrator )
{
if( !builder )
return false;
LogVerbose(LOG_TRT "device %s, configuring network builder\n", deviceTypeToStr(device));
builder->setMaxBatchSize(maxBatchSize);
builder->setMaxWorkspaceSize(workspaceSize);
builder->setDebugSync(mEnableDebug);
builder->setMinFindIterations(3); // allow time for GPU to spin up
builder->setAverageFindIterations(2);
// set up the builder for the desired precision
if( precision == TYPE_INT8 )
{
#if NV_TENSORRT_MAJOR >= 4
builder->setInt8Mode(true);
//builder->setFp16Mode(true); // TODO: experiment for benefits of both INT8/FP16
if( !calibrator )
{
LogError(LOG_TRT "device %s, INT8 requested but calibrator is NULL\n", deviceTypeToStr(device));
return false;