diff --git a/.gitmodules b/.gitmodules index a8d69154..f6129a8a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,17 @@ [submodule "core/lib/threadx"] path = core/lib/threadx - url = https://github.com/azure-rtos/threadx.git + # url = https://github.com/azure-rtos/threadx.git + url = https://github.com/Linaro/threadx.git + branch = mps3_an524 [submodule "core/lib/netxduo"] path = core/lib/netxduo url = https://github.com/azure-rtos/netxduo.git [submodule "core/lib/jsmn/src"] path = core/lib/jsmn/src url = https://github.com/zserge/jsmn +[submodule "core/lib/tfm"] + path = core/lib/tfm + url = https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git +[submodule "core/lib/tf-m-tests"] + path = core/lib/tf-m-tests + url = https://git.trustedfirmware.org/TF-M/tf-m-tests.git diff --git a/Arm/MPS3_AN524/CMakeLists.txt b/Arm/MPS3_AN524/CMakeLists.txt new file mode 100644 index 00000000..81271512 --- /dev/null +++ b/Arm/MPS3_AN524/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT License. + +cmake_minimum_required(VERSION 3.13 FATAL_ERROR) +set(CMAKE_C_STANDARD 99) + +set(GSG_BASE_DIR ${CMAKE_SOURCE_DIR}/../..) +set(CORE_SRC_DIR ${GSG_BASE_DIR}/core/src) +set(CORE_LIB_DIR ${GSG_BASE_DIR}/core/lib) + +# use the repo version of ninja on Windows as there is no Ninja installer +if(WIN32) + set(CMAKE_MAKE_PROGRAM ${GSG_BASE_DIR}/cmake/ninja CACHE STRING "Ninja location") +endif() + +# Set the toolchain if not defined +if(NOT CMAKE_TOOLCHAIN_FILE) + set(CMAKE_TOOLCHAIN_FILE "${GSG_BASE_DIR}/cmake/arm-gcc-cortex-m33.cmake") +endif() + +include(${GSG_BASE_DIR}/cmake/utilities.cmake) + +# Define the Project +# The project name must be mps3_524 to conform to the 8.3 naming convention +project(mps3_524 C ASM) + +# Exceptions required by CMSIS UART driver (-Wno-ignored-qualifiers -Wno-return-type) +# Make threadx run in non-secure mode (-DTX_SINGLE_MODE_NON_SECURE) +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wno-ignored-qualifiers -Wno-return-type -DTX_SINGLE_MODE_NON_SECURE") +set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -DTX_SINGLE_MODE_NON_SECURE") + +# add_subdirectory(${CORE_SRC_DIR} core_src) +add_subdirectory(lib) +add_subdirectory(app) diff --git a/Arm/MPS3_AN524/app/CMakeLists.txt b/Arm/MPS3_AN524/app/CMakeLists.txt new file mode 100644 index 00000000..0561d5a2 --- /dev/null +++ b/Arm/MPS3_AN524/app/CMakeLists.txt @@ -0,0 +1,120 @@ +# Copyright (c) 2021 Linaro Limited. +# Licensed under the MIT License. + +set(APP_CONFIG_OPTIONS "${CMAKE_CURRENT_LIST_DIR}/config.cmake" CACHE FILEPATH + "Configuration Options" +) + +include(${APP_CONFIG_OPTIONS}) + +set(LINKER_SCRIPT "${CMAKE_CURRENT_LIST_DIR}/startup/mps3_an524.ld") + +set(SOURCES + startup/startup_cmsdk_mps3_an524_bl2.S + main.c + board_init.c + console.c +) + +add_executable(${PROJECT_NAME} ${SOURCES}) + +target_compile_definitions(${PROJECT_NAME} + PRIVATE + $<$:TFM_REGRESSION> + $<$:TFM_PSA_TEST> +) + +target_link_libraries(${PROJECT_NAME} + PUBLIC + azrtos::threadx + threadx-cmsis + + # app_common + # jsmn + AN524 + tfm_api + # netx_driver +) + +target_link_options(${PROJECT_NAME} + PRIVATE + -T${LINKER_SCRIPT} -Wl,-Map=${PROJECT_NAME}.map) + +set_target_properties(${PROJECT_NAME} + PROPERTIES + LINK_DEPENDS ${LINKER_SCRIPT} + SUFFIX ".elf" +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + . +) + +if(BUILD_WITH_TFM) + if (NOT TFM_MCUBOOT_IMAGE_NUMBER STREQUAL "OFF") + set(TFM_MCUBOOT_IMAGE_NUMBER_OPTION "MCUBOOT_IMAGE_NUMBER ${TFM_MCUBOOT_IMAGE_NUMBER}") + endif() + if (TFM_ISOLATION_LEVEL) + set(TFM_ISOLATION_LEVEL_OPTION "ISOLATION_LEVEL ${TFM_ISOLATION_LEVEL}") + endif() + if (TFM_KEY_FILE_S) + set(TFM_KEY_FILE_S_OPTION "KEY_FILE_S ${TFM_KEY_FILE_S}") + endif() + if (TFM_KEY_FILE_NS) + set(TFM_KEY_FILE_NS_OPTION "KEY_FILE_NS ${TFM_KEY_FILE_NS}") + endif() + if (TFM_PROFILE) + set(TFM_PROFILE_OPTION BUILD_PROFILE ${TFM_PROFILE}) + endif() + if (TFM_BL2) + set(TFM_BL2_OPTION "BL2") + endif() + if (TFM_IPC) + set(TFM_IPC_OPTION "IPC") + endif() + if (TFM_PSA_TEST) + set(TFM_PSA_TEST_OPTION PSA_TEST_SUITE ${TFM_PSA_TEST}) + endif() + if (TFM_REGRESSION) + set(TFM_REGRESSION_OPTION "REGRESSION") + endif() + if (TFM_PARTITION_PROTECTED_STORAGE) + list(APPEND PARTITIONS "TFM_PARTITION_PROTECTED_STORAGE") + endif() + if (TFM_PARTITION_INTERNAL_TRUSTED_STORAGE) + list(APPEND PARTITIONS "TFM_PARTITION_INTERNAL_TRUSTED_STORAGE") + endif() + if (TFM_PARTITION_PLATFORM) + list(APPEND PARTITIONS "TFM_PARTITION_PLATFORM") + endif() + if (TFM_PARTITION_CRYPTO) + list(APPEND PARTITIONS "TFM_PARTITION_CRYPTO") + endif() + if (TFM_PARTITION_INITIAL_ATTESTATION) + list(APPEND PARTITIONS "TFM_PARTITION_INITIAL_ATTESTATION") + endif() + if (TFM_PARTITION_AUDIT_LOG) + list(APPEND PARTITIONS "TFM_PARTITION_AUDIT_LOG") + endif() + if (TFM_PARTITION_FIRMWARE_UPDATE) + list(APPEND PARTITIONS "TFM_PARTITION_FIRMWARE_UPDATE") + endif() + if (PARTITIONS) + set(PARTITIONS_OPTION "ENABLED_PARTITIONS ${PARTITIONS}") + endif() + trusted_firmware_build( + BINARY_DIR ${CMAKE_BINARY_DIR}/tfm + BOARD arm/mps3/an524 + ${TFM_PROFILE_OPTION} + ${TFM_PSA_TEST_OPTION} + ${TFM_MCUBOOT_IMAGE_NUMBER_OPTION} + ${TFM_ISOLATION_LEVEL_OPTION} + ${TFM_KEY_FILE_S_OPTION} + ${TFM_KEY_FILE_NS_OPTION} + ${TFM_BL2_OPTION} + ${TFM_IPC_OPTION} + ${TFM_REGRESSION_OPTION} + ${PARTITIONS_OPTION} + ) +endif() diff --git a/Arm/MPS3_AN524/app/board_init.c b/Arm/MPS3_AN524/app/board_init.c new file mode 100644 index 00000000..64c1748b --- /dev/null +++ b/Arm/MPS3_AN524/app/board_init.c @@ -0,0 +1,35 @@ +/* Copyright (c) 2021 Linaro Limited. */ + +#include +#include + +#include "board_init.h" + +/* Initialise uart console */ +static void console_init() +{ + int32_t ret; + + /* Initialize the USART driver */ + ret = Driver_USART0.Initialize(NULL); + assert(ret == ARM_DRIVER_OK); + + /* Power up the USART peripheral */ + ret = Driver_USART0.PowerControl(ARM_POWER_FULL); + assert(ret == ARM_DRIVER_OK); + + /* Configure the USART to 115200 (DEFAULT_UART_BAUDRATE) Bits/sec */ + ret = Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, + DEFAULT_UART_BAUDRATE); + assert(ret == ARM_DRIVER_OK); + + /* Enable Transmitter line */ + Driver_USART0.Control(ARM_USART_CONTROL_TX, 1); +} + +/* Initialise the board */ +void board_init() +{ + /* Initialise uart console */ + console_init(); +} diff --git a/Arm/MPS3_AN524/app/board_init.h b/Arm/MPS3_AN524/app/board_init.h new file mode 100644 index 00000000..ade80b9a --- /dev/null +++ b/Arm/MPS3_AN524/app/board_init.h @@ -0,0 +1,14 @@ +/* Copyright (c) 2021 Linaro Limited. */ + +#ifndef _BOARD_INIT_H +#define _BOARD_INIT_H + +#include "Driver_USART.h" +#include "device_cfg.h" + +/* USART0 driver */ +extern ARM_DRIVER_USART Driver_USART0; + +void board_init(); + +#endif // _BOARD_INIT_H diff --git a/Arm/MPS3_AN524/app/config.cmake b/Arm/MPS3_AN524/app/config.cmake new file mode 100644 index 00000000..ec68036b --- /dev/null +++ b/Arm/MPS3_AN524/app/config.cmake @@ -0,0 +1,159 @@ +# Copyright (c) 2021 Linaro Limited. +# Licensed under the MIT License. + +set(TX_TFM_BASE_DIR ${GSG_BASE_DIR}/core/lib/tfm) +set(TX_TFM_BL2_DIR ${TX_TFM_BASE_DIR}/bl2/ext/mcuboot) + +option(BUILD_WITH_TFM "Build with TF-M as the Secure Execution Environment" ON) +include(CMakeDependentOption) +set(TFM_KEY_FILE_S + "${TX_TFM_BL2_DIR}/root-RSA-3072.pem" + CACHE FILEPATH + "The path and filename for the .pem file containing the private key + that should be used by the BL2 bootloader when signing secure + firmware images." +) + +set(TFM_KEY_FILE_NS + "${TX_TFM_BL2_DIR}/root-RSA-3072_1.pem" + CACHE FILEPATH + "The path and filename for the .pem file containing the private key + that should be used by the BL2 bootloader when signing non-secure + firmware images." +) + +set(TFM_PROFILE + OFF + CACHE STRING + "The build profile used for TFM Secure image." +) + +set(TFM_ISOLATION_LEVEL + "1" + CACHE STRING + "Manually set the required TFM isolation level. Possible values are + 1,2 or 3; the default is set by build configuration." +) + +cmake_dependent_option(TFM_BL2 + "TFM is designed to run with MCUboot in a certain configuration. + This config adds MCUboot to the build - built via TFM's build system." + ON + BUILD_WITH_TFM OFF +) + +set(TFM_MCUBOOT_IMAGE_NUMBER + "1" + CACHE STRING + "How many images the bootloader sees when it looks at TFM and the app. + When this is 1, the S and NS are considered as 1 image and must be + updated in one atomic operation. When this is 2, they are split and + can be updated independently if dependency requirements are met." +) + +cmake_dependent_option(TFM_PARTITION_PROTECTED_STORAGE + "Setting this option will cause '-DTFM_PARTITION_PROTECTED_STORAGE' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE + "Setting this option will cause '-DTFM_PARTITION_INTERNAL_TRUSTED_STORAGE' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_CRYPTO + "Setting this option will cause '-DTFM_PARTITION_CRYPTO' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_INITIAL_ATTESTATION + "Setting this option will cause '-DTFM_PARTITION_INITIAL_ATTESTATION' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_PLATFORM + "Setting this option will cause '-DTFM_PARTITION_PLATFORM' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_AUDIT_LOG + "Setting this option will cause '-DTFM_PARTITION_AUDIT_LOG' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_PARTITION_FIRMWARE_UPDATE + "Setting this option will cause '-DTFM_PARTITION_FIRMWARE_UPDATE' + to be passed to the TF-M build system. Look at 'config_default.cmake' + in the trusted-firmware-m repository for details regarding this + parameter. Any dependencies between the various TFM_PARTITION_* + options are handled by the build system in the trusted-firmware-m + repository." + On + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_IPC + "When enabled, this option signifies that the TF-M build supports + the PSA API (IPC mode) instead of the secure library mode." + ON + BUILD_WITH_TFM OFF +) + +cmake_dependent_option(TFM_REGRESSION + "When enabled, this option signifies that the TF-M build includes + the Secure and the Non-Secure regression tests." + OFF + BUILD_WITH_TFM OFF +) + +set(TFM_PSA_TEST + "" + CACHE STRING + "Enable a PSA test suite. Available test suites include CRYPTO, + PROTECTED_STORAGE, INTERNAL_TRUSTED_STORAGE, STORAGE and + INITIAL_ATTESTATION." +) + +set(APP_CONFIG OFF CACHE FILEPATH + "Configuration file for the MPS3 AN524 example app" +) + +if (APP_CONFIG) + include(${APP_CONFIG}) +endif() diff --git a/Arm/MPS3_AN524/app/console.c b/Arm/MPS3_AN524/app/console.c new file mode 100644 index 00000000..8db39032 --- /dev/null +++ b/Arm/MPS3_AN524/app/console.c @@ -0,0 +1,22 @@ +/* Copyright (c) 2021 Linaro Limited. */ + +#include +#include + +#include "board_init.h" + +/* Override `_write` function to redirect printf to uart console */ +int _write(int fd, char *str, int len) +{ + (void)fd; + int32_t ret; + + /* Send string and return the number of characters written */ + ret = Driver_USART0.Send(str, len); + assert(ret == ARM_DRIVER_OK); + + /* Add a busy wait after sending. */ + while (Driver_USART0.GetStatus().tx_busy); + + return Driver_USART0.GetTxCount(); +} diff --git a/Arm/MPS3_AN524/app/main.c b/Arm/MPS3_AN524/app/main.c new file mode 100644 index 00000000..7e7a57c7 --- /dev/null +++ b/Arm/MPS3_AN524/app/main.c @@ -0,0 +1,132 @@ +/* Copyright (c) 2021 Linaro Limited. */ + +#include + +#include "tx_api.h" +#include "tx_cmsis_os2.h" + +#include "board_init.h" +#include "cmsis.h" +#include "tfm_api.h" +#include "tfm_ns_interface.h" +#ifdef TFM_PSA_API +#include "psa_manifest/sid.h" +#endif + +#ifdef TFM_REGRESSION +#include "test_framework_integ_test.h" +#endif + +#define AZURE_THREAD_STACK_SIZE 4096 +#define AZURE_THREAD_PRIORITY 4 + +int tfm_log_printf(const char *fmt, ...) +{ + printf(fmt); +} + +static __inline void systick_interval_set(uint32_t ticks) +{ + // 1. Disable the counter + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + // 2. Update the Systick timer period + SysTick->LOAD = SystemCoreClock / ticks - 1; + + // 3. Clear the current value + SysTick->VAL = 0; + + // 4. Enable the counter + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +TX_MUTEX tfm_ns_dispatch_mutex; + +int32_t tfm_ns_interface_dispatch(veneer_fn fn, + uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + int32_t ret = 0; + tx_mutex_get(&tfm_ns_dispatch_mutex, TX_WAIT_FOREVER); + ret = fn(arg0, arg1, arg2, arg3); + tx_mutex_put(&tfm_ns_dispatch_mutex); + return ret; +} + +TX_THREAD azure_thread; +ULONG azure_thread_stack[AZURE_THREAD_STACK_SIZE / sizeof(ULONG)]; + +void azure_thread_entry(ULONG parameter); +void tx_application_define(void* first_unused_memory); + +void azure_thread_entry(ULONG parameter) +{ + uint32_t version; + printf("Starting Azure thread\r\n"); + version = psa_framework_version(); + if (version == PSA_FRAMEWORK_VERSION) { + printf("The version of the PSA Framework API is %lu.\n", + version); + } else { + printf("The version of the PSA Framework API is not valid!\n"); + return; + } + +#ifdef TFM_REGRESSION + psa_handle_t handle; + + handle = psa_connect(IPC_SERVICE_TEST_BASIC_SID, + IPC_SERVICE_TEST_BASIC_VERSION); + if (handle > 0) { + printf("Connect success!\n"); + } else { + printf("The RoT Service has refused the connection!\n"); + return; + } + psa_close(handle); + + /* Start TF-M NS regression tests */ + tfm_non_secure_client_run_tests(); +#endif /* TFM_REGRESSION */ + +#ifdef TFM_PSA_TEST + extern void val_entry(void); + val_entry(); +#endif /* TFM_PSA_TEST */ +} + +void tx_application_define(void* first_unused_memory) +{ + systick_interval_set(TX_TIMER_TICKS_PER_SECOND); + + // Create Azure thread + UINT status = tx_thread_create(&azure_thread, + "Azure Thread", + azure_thread_entry, + 0, + azure_thread_stack, + AZURE_THREAD_STACK_SIZE, + AZURE_THREAD_PRIORITY, + AZURE_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + printf("Azure IoT thread creation failed\r\n"); + } +} + +int main(void) +{ + /* Initialise the board */ + board_init(); + + printf("Azure RTOS running on MPS3 board\n"); + + tx_mutex_create(&tfm_ns_dispatch_mutex, "TF-M Dispatch Mutex", TX_INHERIT); + init_cmsis_os2(); + tx_kernel_enter(); + + return 0; +} diff --git a/Arm/MPS3_AN524/app/startup/mps3_an524.ld b/Arm/MPS3_AN524/app/startup/mps3_an524.ld new file mode 100644 index 00000000..6201c6de --- /dev/null +++ b/Arm/MPS3_AN524/app/startup/mps3_an524.ld @@ -0,0 +1,187 @@ +;/* +; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * +; * This file is derivative of CMSIS V5.00 gcc_arm.ld +; */ + +/* Linker script to configure memory regions. */ +/* This file will be run through the pre-processor. */ + +/* #include "region_defs.h" */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x000C0400, LENGTH = (0x40000 - 0x400) /* 256 KB */ + /* Total RAM size is 128KB, out of which 96KB is allocated to TF-M */ + RAM (rwx) : ORIGIN = 0x20018000, LENGTH = 0x8000 /* 32 KB */ +} + +__heap_size__ = 0x0001000; +__msp_stack_size__ = 0x0001000; + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __Vectors_Start = .; + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors_Start; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * define etext2/data2_start/data2_end and + * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps3_an524_bl2.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (DEFINED(__etext2) ? __etext2 : 0) + LONG (DEFINED(__data2_start__) ? __data2_start__ : 0) + LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0) + __copy_table_end__ = .; + } > FLASH + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps3_an524_bl2.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0) + LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0) + __zero_table_end__ = .; + } > FLASH + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + Image$$ER_DATA$$Base = ADDR(.data); + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .msp_stack : ALIGN(32) + { + . += __msp_stack_size__; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .heap : ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + __RAM_segment_used_end__ = .; + + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); +} diff --git a/Arm/MPS3_AN524/app/startup/startup_cmsdk_mps3_an524_bl2.S b/Arm/MPS3_AN524/app/startup/startup_cmsdk_mps3_an524_bl2.S new file mode 100644 index 00000000..67b5c388 --- /dev/null +++ b/Arm/MPS3_AN524/app/startup/startup_cmsdk_mps3_an524_bl2.S @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.01 startup_ARMCM33.S + * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75 + */ + + .syntax unified + .arch armv8-m.main + + .section .vectors + .align 2 + .globl _vectors +_vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + + /* Core interrupts */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long SecureFault_Handler /* Secure Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ + .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ + .long S32K_TIMER_Handler /* 2: S32K Timer Handler */ + .long TIMER0_Handler /* 3: TIMER 0 Handler */ + .long TIMER1_Handler /* 4: TIMER 1 Handler */ + .long DUALTIMER_Handler /* 5: Dual Timer Handler */ + .long MHU0_Handler /* 6: Message Handling Unit 0 */ + .long MHU1_Handler /* 7: Message Handling Unit 1 */ + .long 0 /* 8: Reserved */ + .long MPC_Handler /* 9: MPC Combined (Secure) Handler */ + .long PPC_Handler /* 10: PPC Combined (Secure) Handler */ + .long MSC_Handler /* 11: MSC Combined (Secure) Handler */ + .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */ + .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */ + .long 0 /* 14: Reserved */ + .long SYS_PPU_Handler /* 15: SYS PPU Handler */ + .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */ + .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */ + .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */ + .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */ + .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */ + .long CORDIO_PPU_Handler /* 21: CORDIO PPU Handler */ + .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */ + .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */ + .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */ + .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */ + .long DBG_PPU_Handler /* 26: DEBUG_PPU Handler */ + .long 0 /* 27: Reserved */ + .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */ + .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */ + .long 0 /* 30: Reserved */ + .long 0 /* 31: Reserved */ + /* External Interrupts */ + .long UARTRX0_Handler /* 32: UART 0 RX Handler */ + .long UARTTX0_Handler /* 33: UART 0 TX Handler */ + .long UARTRX1_Handler /* 34: UART 1 RX Handler */ + .long UARTTX1_Handler /* 35: UART 1 TX Handler */ + .long UARTRX2_Handler /* 36: UART 2 RX Handler */ + .long UARTTX2_Handler /* 37: UART 2 TX Handler */ + .long UARTRX3_Handler /* 38: UART 3 RX Handler */ + .long UARTTX3_Handler /* 39: UART 3 TX Handler */ + .long UARTRX4_Handler /* 40: UART 4 RX Handler */ + .long UARTTX4_Handler /* 41: UART 4 TX Handler */ + .long UART0_Handler /* 42: UART 0 combined Handler */ + .long UART1_Handler /* 43: UART 1 combined Handler */ + .long UART2_Handler /* 44: UART 2 combined Handler */ + .long UART3_Handler /* 45: UART 3 combined Handler */ + .long UART4_Handler /* 46: UART 4 combined Handler */ + .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */ + .long ETHERNET_Handler /* 48: Ethernet Handler */ + .long I2S_Handler /* 49: I2S Handler */ + .long TSC_Handler /* 50: Touch Screen Handler */ + .long 0 /* 51: Reserved */ + .long SPI0_Handler /* 52: SPI ADC Handler */ + .long SPI1_Handler /* 53: SPI (Shield 0) Handler */ + .long SPI2_Handler /* 54: SPI (Shield 1) Handler */ + .long 0 /* 55: Reserved */ + .long 0 /* 56: Reserved */ + .long 0 /* 57: Reserved */ + .long 0 /* 58: Reserved */ + .long 0 /* 59: Reserved */ + .long 0 /* 50: Reserved */ + .long 0 /* 61: Reserved */ + .long 0 /* 62: Reserved */ + .long 0 /* 63: Reserved */ + .long 0 /* 64: Reserved */ + .long 0 /* 65: Reserved */ + .long 0 /* 66: Reserved */ + .long 0 /* 67: Reserved */ + .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */ + .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */ + .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */ + .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */ + .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */ + .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */ + .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */ + .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */ + .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */ + .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */ + .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */ + .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */ + .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */ + .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */ + .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */ + .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */ + .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */ + .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */ + .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */ + .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */ + .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */ + .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */ + .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */ + .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */ + .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */ + .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */ + .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */ + .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */ + .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */ + .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */ + .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */ + .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */ + .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */ + .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */ + .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */ + .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */ + .long GPIO2_0_Handler /* 104: All P2 I/O pins used as irq source */ + .long GPIO2_1_Handler /* 105 There are 15 pins in total */ + .long GPIO2_2_Handler /* 106 */ + .long GPIO2_3_Handler /* 107 */ + .long GPIO2_4_Handler /* 108 */ + .long GPIO2_5_Handler /* 109 */ + .long GPIO2_6_Handler /* 110 */ + .long GPIO2_7_Handler /* 111 */ + .long GPIO2_8_Handler /* 112 */ + .long GPIO2_9_Handler /* 113 */ + .long GPIO2_10_Handler /* 114 */ + .long GPIO2_11_Handler /* 115 */ + .long GPIO2_12_Handler /* 116 */ + .long GPIO2_13_Handler /* 117 */ + .long GPIO2_14_Handler /* 118 */ + .long GPIO2_15_Handler /* 119 */ + .long GPIO3_0_Handler /* 120: All P3 I/O pins used as irq source */ + .long GPIO3_1_Handler /* 121 There are 4 pins in total */ + .long GPIO3_2_Handler /* 122 */ + .long GPIO3_3_Handler /* 123 */ + .long UARTRX5_Handler /* 124 */ + .long UARTTX5_Handler /* 125 */ + .long UART5_Handler /* 126 */ + .long HDLCD_Handler /* 127 */ + + .size _vectors, . - _vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + + /* Only run on core 0 */ + mov r0, #0x40000000 + add r0, #0x0001F000 + ldr r0, [r0] + cmp r0,#0 +not_the_core_to_run_on: + bne not_the_core_to_run_on + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + bl SystemInit + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + +/* Macro to define default handlers. */ + .macro def_irq_handler handler_name + .thumb_func + .weak \handler_name + \handler_name: + b \handler_name + .endm + + /* Core interrupts */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ + def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ + def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */ + def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */ + def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */ + def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */ + def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */ + def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */ + def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */ + def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */ + def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */ + def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */ + def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */ + def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */ + def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */ + def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */ + def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */ + def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */ + def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */ + def_irq_handler CORDIO_PPU_Handler /* 21 CORDIO PPU Handler */ + def_irq_handler RAM0_PPU_Handler /* 22 RAM1 PPU Handler */ + def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */ + def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */ + def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */ + def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */ + def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */ + def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */ + /* External interrupts */ + def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */ + def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */ + def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */ + def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */ + def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */ + def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */ + def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */ + def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */ + def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */ + def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */ + def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */ + def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */ + def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */ + def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */ + def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */ + def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */ + def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */ + def_irq_handler I2S_Handler /* 49: I2S Handler */ + def_irq_handler TSC_Handler /* 50: Touch Screen Handler */ + def_irq_handler SPI0_Handler /* 52: SPI ADC Handler */ + def_irq_handler SPI1_Handler /* 53: SPI (Shield 0) Handler */ + def_irq_handler SPI2_Handler /* 54: SPI (Shield 1) Handler */ + def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */ + def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */ + def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */ + def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */ + def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */ + def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */ + def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */ + def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */ + def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */ + def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */ + def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */ + def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */ + def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */ + def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */ + def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */ + def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */ + def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */ + def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */ + def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */ + def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */ + def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */ + def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */ + def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */ + def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */ + def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */ + def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */ + def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */ + def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */ + def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */ + def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */ + def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */ + def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */ + def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */ + def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */ + def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */ + def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */ + def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */ + def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */ + def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */ + def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */ + def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */ + def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */ + def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */ + def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */ + def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */ + def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */ + def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */ + def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */ + def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */ + def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */ + def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */ + def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */ + def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */ + def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_0 Handler */ + def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_0 Handler */ + def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_0 Handler */ + def_irq_handler UARTRX5_Handler /* 124: */ + def_irq_handler UARTTX5_Handler /* 125: */ + def_irq_handler UART5_Handler /* 126: */ + def_irq_handler HDLCD_Handler /* 127: */ + + .end diff --git a/Arm/MPS3_AN524/lib/AN524/CMakeLists.txt b/Arm/MPS3_AN524/lib/AN524/CMakeLists.txt new file mode 100644 index 00000000..11b5c75f --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT License. + +set(SOURCES + src/CMSIS/Driver_USART.c + src/device/source/system_core_init.c + src/device/source/device_definition.c + src/native_drivers/uart_cmsdk_drv.c +) + +set(TARGET AN524) + +add_library(${TARGET} OBJECT + ${SOURCES} +) + +target_compile_definitions(${TARGET} + PUBLIC + # TODO: Add defines +) + +target_include_directories(${TARGET} + PUBLIC + src/CMSIS/config + src/CMSIS/include + src/device/config + src/device/include + src/native_drivers +) diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_Flash.c b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_Flash.c new file mode 100644 index 00000000..0582300f --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_Flash.c @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file is a derivative of a previous version of + * platform/ext/target/musca_b1/CMSIS_Driver/Driver_Flash.c + * Git SHA: 9f3da0b83e45e6d26ad0be45c090d2e4382fb04f + */ + +/* FIXME: This interim flash driver uses BRAM to emulate flash for PS. + * Code is still running on QSPI, and only direct read is supported, + * write is not supported yet. + * It should be replaced with a real flash driver. + */ + +#include +#include +#include "Driver_Flash.h" +#include "RTE_Device.h" +#include "flash_layout.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) ((void)arg) +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +#define FLASH_REDIRECT_BASE FLASH_PS_AREA_OFFSET +#define FLASH_REDIRECT_LIMIT (FLASH_REDIRECT_BASE \ + + FLASH_PS_AREA_SIZE \ + + FLASH_ITS_AREA_SIZE \ + + FLASH_NV_COUNTERS_AREA_SIZE) +#define FLASH_REDIRECT_DEST 0x38000000 + +#define FLASH0_BASE_S 0x10000000 +#define FLASH0_BASE_NS 0x00000000 +#define FLASH0_SIZE 0x00800000 /* 8 MB */ +#define FLASH0_SECTOR_SIZE 0x00001000 /* 4 kB */ +#define FLASH0_PAGE_SIZE 0x00001000 /* 4 kB */ +#define FLASH0_PROGRAM_UNIT 0x1 /* Minimum write size */ + +/* + * ARM FLASH device structure + */ +struct arm_flash_dev_t { + const uint32_t memory_base; /*!< FLASH memory base address */ + ARM_FLASH_INFO *data; /*!< FLASH data */ +}; + +/* Flash Status */ +static ARM_FLASH_STATUS FlashStatus = {0, 0, 0}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_FLASH_API_VERSION, + ARM_FLASH_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + 0, /* event_ready */ + 2, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ + 1 /* erase_chip */ +}; + +static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev, + uint32_t offset) +{ + uint32_t flash_limit = 0; + int32_t rc = 0; + + flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size) + - 1; + + if (offset > flash_limit) { + rc = -1; + } + return rc; +} + +static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev, + uint32_t param) +{ + int32_t rc = 0; + + if ((param % flash_dev->data->program_unit) != 0) { + rc = -1; + } + return rc; +} + +static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev, + uint32_t offset) +{ + int32_t rc = 0; + + if ((offset % flash_dev->data->sector_size) != 0) { + rc = -1; + } + return rc; +} + +#if (RTE_FLASH0) +static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE, + .sector_size = FLASH0_SECTOR_SIZE, + .page_size = FLASH0_PAGE_SIZE, + .program_unit = FLASH0_PROGRAM_UNIT, + .erased_value = 0xFF}; + +static struct arm_flash_dev_t ARM_FLASH0_DEV = { +#if (__DOMAIN_NS == 1) + .memory_base = FLASH0_BASE_NS, +#else + .memory_base = FLASH0_BASE_S, +#endif /* __DOMAIN_NS == 1 */ + .data = &(ARM_FLASH0_DEV_DATA)}; + +struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV; + +/* + * Functions + */ + +static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + break; + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) +{ + volatile uint32_t mem_base = FLASH0_DEV->memory_base; + uint32_t start_addr = mem_base + addr; + int32_t rc = 0; + + /* Check flash memory boundaries */ + rc = is_range_valid(FLASH0_DEV, addr + cnt); + if (rc != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Redirecting PS storage to BRAM */ + if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) { + start_addr = FLASH_REDIRECT_DEST + (addr - FLASH_REDIRECT_BASE); + } + + memcpy(data, (void *)start_addr, cnt); + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, + uint32_t cnt) +{ + volatile uint32_t mem_base = FLASH0_DEV->memory_base; + uint32_t start_addr = mem_base + addr; + int32_t rc = 0; + + /* Check flash memory boundaries and alignment with minimal write size */ + rc = is_range_valid(FLASH0_DEV, addr + cnt); + rc |= is_write_aligned(FLASH0_DEV, addr); + rc |= is_write_aligned(FLASH0_DEV, cnt); + if (rc != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Redirecting PS storage to BRAM */ + if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) { + start_addr = FLASH_REDIRECT_DEST + (addr - FLASH_REDIRECT_BASE); + /* PS Flash is emulated over BRAM. use memcpy function. */ + memcpy((void *)start_addr, data, cnt); + } else { + /* Flash driver for QSPI is not ready */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_EraseSector(uint32_t addr) +{ + uint32_t rc = 0; + + rc = is_range_valid(FLASH0_DEV, addr); + rc |= is_sector_aligned(FLASH0_DEV, addr); + if (rc != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Redirecting PS storage to BRAM */ + if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) { + /* PS Flash IS emulated over BRAM. use memcpy function. */ + memset((void *)(FLASH_REDIRECT_DEST + + (addr - FLASH_REDIRECT_BASE)), + FLASH0_DEV->data->erased_value, + FLASH0_DEV->data->sector_size); + } else { + /* Flash driver for QSPI is not ready */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_EraseChip(void) +{ + uint32_t i; + uint32_t addr = FLASH0_DEV->memory_base; + int32_t rc = ARM_DRIVER_ERROR_UNSUPPORTED; + + /* Check driver capability erase_chip bit */ + if (DriverCapabilities.erase_chip == 1) { + for (i = 0; i < FLASH0_DEV->data->sector_count; i++) { + /* Redirecting PS storage to BRAM */ + if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) { + memset((void *)(FLASH_REDIRECT_DEST + + (addr - FLASH0_DEV->memory_base - FLASH_REDIRECT_BASE)), + FLASH0_DEV->data->erased_value, + FLASH0_DEV->data->sector_size); + } + /* else { + * Flash driver for QSPI is not ready, fall through. + * } + */ + + addr += FLASH0_DEV->data->sector_size; + rc = ARM_DRIVER_OK; + } + } + return rc; +} + +static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) +{ + return FlashStatus; +} + +static ARM_FLASH_INFO *ARM_Flash_GetInfo(void) +{ + return FLASH0_DEV->data; +} + +ARM_DRIVER_FLASH Driver_FLASH0 = { + ARM_Flash_GetVersion, + ARM_Flash_GetCapabilities, + ARM_Flash_Initialize, + ARM_Flash_Uninitialize, + ARM_Flash_PowerControl, + ARM_Flash_ReadData, + ARM_Flash_ProgramData, + ARM_Flash_EraseSector, + ARM_Flash_EraseChip, + ARM_Flash_GetStatus, + ARM_Flash_GetInfo +}; +#endif /* RTE_FLASH0 */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_MPC.c b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_MPC.c new file mode 100644 index 00000000..5894ad86 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_MPC.c @@ -0,0 +1,1750 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_MPC.h" + +#include "cmsis_driver_config.h" +#include "RTE_Device.h" + +/* driver version */ +#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_MPC_API_VERSION, + ARM_MPC_DRV_VERSION +}; + +static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void) +{ + return DriverVersion; +} + +/* + * \brief Translates error codes from native API to CMSIS API. + * + * \param[in] err Error code to translate (\ref mpc_sie200_error_t). + * + * \return Returns CMSIS error code. + */ +static int32_t error_trans(enum mpc_sie200_error_t err) +{ + switch(err) { + case MPC_SIE200_ERR_NONE: + return ARM_DRIVER_OK; + case MPC_SIE200_INVALID_ARG: + return ARM_DRIVER_ERROR_PARAMETER; + case MPC_SIE200_NOT_INIT: + return ARM_MPC_ERR_NOT_INIT; + case MPC_SIE200_ERR_NOT_IN_RANGE: + return ARM_MPC_ERR_NOT_IN_RANGE; + case MPC_SIE200_ERR_NOT_ALIGNED: + return ARM_MPC_ERR_NOT_ALIGNED; + case MPC_SIE200_ERR_INVALID_RANGE: + return ARM_MPC_ERR_INVALID_RANGE; + case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE: + return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + default: + return ARM_MPC_ERR_UNSPECIFIED; + } +} + +#if (RTE_ISRAM0_MPC) +/* Ranges controlled by this ISRAM0_MPC */ +static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = { + .base = MPC_ISRAM0_RANGE_BASE_S, + .limit = MPC_ISRAM0_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = { + .base = MPC_ISRAM0_RANGE_BASE_NS, + .limit = MPC_ISRAM0_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_ISRAM0_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN] = { + &MPC_ISRAM0_RANGE_S, + &MPC_ISRAM0_RANGE_NS + }; + +/* ISRAM0_MPC Driver wrapper functions */ +static int32_t ISRAM0_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_ISRAM0_DEV, + MPC_ISRAM0_RANGE_LIST, + MPC_ISRAM0_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ISRAM0_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV, base, limit, + (enum mpc_sie200_sec_attr_t*)attr); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t ISRAM0_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV); + + return error_trans(ret); +} + +static void ISRAM0_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_ISRAM0_DEV); +} + + +static void ISRAM0_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_ISRAM0_DEV); +} + +static uint32_t ISRAM0_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_ISRAM0_DEV); +} + +static int32_t ISRAM0_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_ISRAM0_DEV); +} + +/* ISRAM0_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_ISRAM0_MPC; +ARM_DRIVER_MPC Driver_ISRAM0_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = ISRAM0_MPC_Initialize, + .Uninitialize = ISRAM0_MPC_Uninitialize, + .GetBlockSize = ISRAM0_MPC_GetBlockSize, + .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig, + .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig, + .ConfigRegion = ISRAM0_MPC_ConfigRegion, + .GetRegionConfig = ISRAM0_MPC_GetRegionConfig, + .EnableInterrupt = ISRAM0_MPC_EnableInterrupt, + .DisableInterrupt = ISRAM0_MPC_DisableInterrupt, + .ClearInterrupt = ISRAM0_MPC_ClearInterrupt, + .InterruptState = ISRAM0_MPC_InterruptState, + .LockDown = ISRAM0_MPC_LockDown, +}; +#endif /* RTE_ISRAM0_MPC */ + +#if (RTE_ISRAM1_MPC) +/* Ranges controlled by this ISRAM1_MPC */ +static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = { + .base = MPC_ISRAM1_RANGE_BASE_S, + .limit = MPC_ISRAM1_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = { + .base = MPC_ISRAM1_RANGE_BASE_NS, + .limit = MPC_ISRAM1_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_ISRAM1_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN] = { + &MPC_ISRAM1_RANGE_S, + &MPC_ISRAM1_RANGE_NS + }; + +/* ISRAM1_MPC Driver wrapper functions */ +static int32_t ISRAM1_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_ISRAM1_DEV, + MPC_ISRAM1_RANGE_LIST, + MPC_ISRAM1_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ISRAM1_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t ISRAM1_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV); + + return error_trans(ret); +} + +static void ISRAM1_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_ISRAM1_DEV); +} + + +static void ISRAM1_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_ISRAM1_DEV); +} + +static uint32_t ISRAM1_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_ISRAM1_DEV); +} + +static int32_t ISRAM1_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_ISRAM1_DEV); +} + +/* ISRAM1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_ISRAM1_MPC; +ARM_DRIVER_MPC Driver_ISRAM1_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = ISRAM1_MPC_Initialize, + .Uninitialize = ISRAM1_MPC_Uninitialize, + .GetBlockSize = ISRAM1_MPC_GetBlockSize, + .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig, + .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig, + .ConfigRegion = ISRAM1_MPC_ConfigRegion, + .GetRegionConfig = ISRAM1_MPC_GetRegionConfig, + .EnableInterrupt = ISRAM1_MPC_EnableInterrupt, + .DisableInterrupt = ISRAM1_MPC_DisableInterrupt, + .ClearInterrupt = ISRAM1_MPC_ClearInterrupt, + .InterruptState = ISRAM1_MPC_InterruptState, + .LockDown = ISRAM1_MPC_LockDown, +}; +#endif /* RTE_ISRAM1_MPC */ + +#if (RTE_ISRAM2_MPC) +/* Ranges controlled by this ISRAM2_MPC */ +static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = { + .base = MPC_ISRAM2_RANGE_BASE_S, + .limit = MPC_ISRAM2_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = { + .base = MPC_ISRAM2_RANGE_BASE_NS, + .limit = MPC_ISRAM2_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_ISRAM2_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN] = { + &MPC_ISRAM2_RANGE_S, + &MPC_ISRAM2_RANGE_NS + }; + +/* ISRAM2_MPC Driver wrapper functions */ +static int32_t ISRAM2_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_ISRAM2_DEV, + MPC_ISRAM2_RANGE_LIST, + MPC_ISRAM2_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ISRAM2_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t ISRAM2_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV); + + return error_trans(ret); +} + +static void ISRAM2_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_ISRAM2_DEV); +} + +static void ISRAM2_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_ISRAM2_DEV); +} + +static uint32_t ISRAM2_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_ISRAM2_DEV); +} + +static int32_t ISRAM2_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_ISRAM2_DEV); +} + +/* ISRAM2_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_ISRAM2_MPC; +ARM_DRIVER_MPC Driver_ISRAM2_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = ISRAM2_MPC_Initialize, + .Uninitialize = ISRAM2_MPC_Uninitialize, + .GetBlockSize = ISRAM2_MPC_GetBlockSize, + .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig, + .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig, + .ConfigRegion = ISRAM2_MPC_ConfigRegion, + .GetRegionConfig = ISRAM2_MPC_GetRegionConfig, + .EnableInterrupt = ISRAM2_MPC_EnableInterrupt, + .DisableInterrupt = ISRAM2_MPC_DisableInterrupt, + .ClearInterrupt = ISRAM2_MPC_ClearInterrupt, + .InterruptState = ISRAM2_MPC_InterruptState, + .LockDown = ISRAM2_MPC_LockDown, +}; +#endif /* RTE_ISRAM2_MPC */ + +#if (RTE_ISRAM3_MPC) +/* Ranges controlled by this ISRAM3_MPC */ +static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = { + .base = MPC_ISRAM3_RANGE_BASE_S, + .limit = MPC_ISRAM3_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = { + .base = MPC_ISRAM3_RANGE_BASE_NS, + .limit = MPC_ISRAM3_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_ISRAM3_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN] = { + &MPC_ISRAM3_RANGE_S, + &MPC_ISRAM3_RANGE_NS + }; + +/* ISRAM3_MPC Driver wrapper functions */ +static int32_t ISRAM3_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_ISRAM3_DEV, + MPC_ISRAM3_RANGE_LIST, + MPC_ISRAM3_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ISRAM3_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t ISRAM3_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV); + + return error_trans(ret); +} + +static void ISRAM3_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_ISRAM3_DEV); +} + + +static void ISRAM3_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_ISRAM3_DEV); +} + +static uint32_t ISRAM3_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_ISRAM3_DEV); +} + +static int32_t ISRAM3_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_ISRAM3_DEV); +} + +/* ISRAM3_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_ISRAM3_MPC; +ARM_DRIVER_MPC Driver_ISRAM3_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = ISRAM3_MPC_Initialize, + .Uninitialize = ISRAM3_MPC_Uninitialize, + .GetBlockSize = ISRAM3_MPC_GetBlockSize, + .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig, + .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig, + .ConfigRegion = ISRAM3_MPC_ConfigRegion, + .GetRegionConfig = ISRAM3_MPC_GetRegionConfig, + .EnableInterrupt = ISRAM3_MPC_EnableInterrupt, + .DisableInterrupt = ISRAM3_MPC_DisableInterrupt, + .ClearInterrupt = ISRAM3_MPC_ClearInterrupt, + .InterruptState = ISRAM3_MPC_InterruptState, + .LockDown = ISRAM3_MPC_LockDown, +}; +#endif /* RTE_ISRAM3_MPC */ + +#if (RTE_CODE_SRAM_MPC) +/* Ranges controlled by this CODE_SRAM_MPC */ +static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_S = { + .base = MPC_CODE_SRAM_RANGE_BASE_S, + .limit = MPC_CODE_SRAM_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_NS = { + .base = MPC_CODE_SRAM_RANGE_BASE_NS, + .limit = MPC_CODE_SRAM_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_CODE_SRAM_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_CODE_SRAM_RANGE_LIST[MPC_CODE_SRAM_RANGE_LIST_LEN] = { + &MPC_CODE_SRAM_RANGE_S, + &MPC_CODE_SRAM_RANGE_NS + }; + +/* CODE_SRAM_MPC Driver wrapper functions */ +static int32_t CODE_SRAM_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_CODE_SRAM_DEV, + MPC_CODE_SRAM_RANGE_LIST, + MPC_CODE_SRAM_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t CODE_SRAM_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_CODE_SRAM_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t CODE_SRAM_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM_DEV); + + return error_trans(ret); +} + +static void CODE_SRAM_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_CODE_SRAM_DEV); +} + + +static void CODE_SRAM_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_CODE_SRAM_DEV); +} + +static uint32_t CODE_SRAM_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_CODE_SRAM_DEV); +} + +static int32_t CODE_SRAM_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_CODE_SRAM_DEV); +} + +/* CODE_SRAM_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC; +ARM_DRIVER_MPC Driver_CODE_SRAM_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = CODE_SRAM_MPC_Initialize, + .Uninitialize = CODE_SRAM_MPC_Uninitialize, + .GetBlockSize = CODE_SRAM_MPC_GetBlockSize, + .GetCtrlConfig = CODE_SRAM_MPC_GetCtrlConfig, + .SetCtrlConfig = CODE_SRAM_MPC_SetCtrlConfig, + .ConfigRegion = CODE_SRAM_MPC_ConfigRegion, + .GetRegionConfig = CODE_SRAM_MPC_GetRegionConfig, + .EnableInterrupt = CODE_SRAM_MPC_EnableInterrupt, + .DisableInterrupt = CODE_SRAM_MPC_DisableInterrupt, + .ClearInterrupt = CODE_SRAM_MPC_ClearInterrupt, + .InterruptState = CODE_SRAM_MPC_InterruptState, + .LockDown = CODE_SRAM_MPC_LockDown, +}; +#endif /* RTE_CODE_SRAM_MPC */ + +#if (RTE_SSRAM1_MPC) +/* Ranges controlled by this SSRAM1_MPC */ +static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_S = { + .base = MPC_SSRAM1_RANGE_BASE_S, + .limit = MPC_SSRAM1_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_NS = { + .base = MPC_SSRAM1_RANGE_BASE_NS, + .limit = MPC_SSRAM1_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_SSRAM1_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_SSRAM1_RANGE_LIST[MPC_SSRAM1_RANGE_LIST_LEN] = { + &MPC_SSRAM1_RANGE_S, + &MPC_SSRAM1_RANGE_NS + }; + +/* SSRAM1_MPC Driver wrapper functions */ +static int32_t SSRAM1_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SSRAM1_DEV, + MPC_SSRAM1_RANGE_LIST, + MPC_SSRAM1_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SSRAM1_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SSRAM1_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SSRAM1_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SSRAM1_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SSRAM1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SSRAM1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SSRAM1_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SSRAM1_DEV); + + return error_trans(ret); +} + +static void SSRAM1_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SSRAM1_DEV); +} + + +static void SSRAM1_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SSRAM1_DEV); +} + +static uint32_t SSRAM1_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SSRAM1_DEV); +} + +static int32_t SSRAM1_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SSRAM1_DEV); +} + +/* SSRAM1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM1_MPC; +ARM_DRIVER_MPC Driver_SRAM1_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SSRAM1_MPC_Initialize, + .Uninitialize = SSRAM1_MPC_Uninitialize, + .GetBlockSize = SSRAM1_MPC_GetBlockSize, + .GetCtrlConfig = SSRAM1_MPC_GetCtrlConfig, + .SetCtrlConfig = SSRAM1_MPC_SetCtrlConfig, + .ConfigRegion = SSRAM1_MPC_ConfigRegion, + .GetRegionConfig = SSRAM1_MPC_GetRegionConfig, + .EnableInterrupt = SSRAM1_MPC_EnableInterrupt, + .DisableInterrupt = SSRAM1_MPC_DisableInterrupt, + .ClearInterrupt = SSRAM1_MPC_ClearInterrupt, + .InterruptState = SSRAM1_MPC_InterruptState, + .LockDown = SSRAM1_MPC_LockDown, +}; +#endif /* RTE_SSRAM1_MPC */ + +#if (RTE_SSRAM2_MPC) +/* Ranges controlled by this SSRAM2_MPC */ +static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_S = { + .base = MPC_SSRAM2_RANGE_BASE_S, + .limit = MPC_SSRAM2_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_NS = { + .base = MPC_SSRAM2_RANGE_BASE_NS, + .limit = MPC_SSRAM2_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_SSRAM2_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_SSRAM2_RANGE_LIST[MPC_SSRAM2_RANGE_LIST_LEN] = { + &MPC_SSRAM2_RANGE_S, + &MPC_SSRAM2_RANGE_NS + }; + +/* SSRAM2_MPC Driver wrapper functions */ +static int32_t SSRAM2_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SSRAM2_DEV, + MPC_SSRAM2_RANGE_LIST, + MPC_SSRAM2_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SSRAM2_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SSRAM2_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SSRAM2_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SSRAM2_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SSRAM2_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SSRAM2_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SSRAM2_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SSRAM2_DEV); + + return error_trans(ret); +} + +static void SSRAM2_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SSRAM2_DEV); +} + + +static void SSRAM2_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SSRAM2_DEV); +} + +static uint32_t SSRAM2_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SSRAM2_DEV); +} + +static int32_t SSRAM2_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SSRAM2_DEV); +} + +/* SSRAM2_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM2_MPC; +ARM_DRIVER_MPC Driver_SRAM2_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SSRAM2_MPC_Initialize, + .Uninitialize = SSRAM2_MPC_Uninitialize, + .GetBlockSize = SSRAM2_MPC_GetBlockSize, + .GetCtrlConfig = SSRAM2_MPC_GetCtrlConfig, + .SetCtrlConfig = SSRAM2_MPC_SetCtrlConfig, + .ConfigRegion = SSRAM2_MPC_ConfigRegion, + .GetRegionConfig = SSRAM2_MPC_GetRegionConfig, + .EnableInterrupt = SSRAM2_MPC_EnableInterrupt, + .DisableInterrupt = SSRAM2_MPC_DisableInterrupt, + .ClearInterrupt = SSRAM2_MPC_ClearInterrupt, + .InterruptState = SSRAM2_MPC_InterruptState, + .LockDown = SSRAM2_MPC_LockDown, +}; +#endif /* RTE_SSRAM2_MPC */ + +#if (RTE_SSRAM3_MPC) +/* Ranges controlled by this SSRAM3_MPC */ +static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_S = { + .base = MPC_SSRAM3_RANGE_BASE_S, + .limit = MPC_SSRAM3_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_NS = { + .base = MPC_SSRAM3_RANGE_BASE_NS, + .limit = MPC_SSRAM3_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_SSRAM3_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_SSRAM3_RANGE_LIST[MPC_SSRAM3_RANGE_LIST_LEN] = { + &MPC_SSRAM3_RANGE_S, + &MPC_SSRAM3_RANGE_NS + }; + +/* SSRAM3_MPC Driver wrapper functions */ +static int32_t SSRAM3_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SSRAM3_DEV, + MPC_SSRAM3_RANGE_LIST, + MPC_SSRAM3_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SSRAM3_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SSRAM3_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SSRAM3_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SSRAM3_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SSRAM3_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SSRAM3_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SSRAM3_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SSRAM3_DEV); + + return error_trans(ret); +} + +static void SSRAM3_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SSRAM3_DEV); +} + + +static void SSRAM3_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SSRAM3_DEV); +} + +static uint32_t SSRAM3_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SSRAM3_DEV); +} + +static int32_t SSRAM3_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SSRAM3_DEV); +} + +/* SSRAM3_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SSRAM3_MPC; +ARM_DRIVER_MPC Driver_SSRAM3_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SSRAM3_MPC_Initialize, + .Uninitialize = SSRAM3_MPC_Uninitialize, + .GetBlockSize = SSRAM3_MPC_GetBlockSize, + .GetCtrlConfig = SSRAM3_MPC_GetCtrlConfig, + .SetCtrlConfig = SSRAM3_MPC_SetCtrlConfig, + .ConfigRegion = SSRAM3_MPC_ConfigRegion, + .GetRegionConfig = SSRAM3_MPC_GetRegionConfig, + .EnableInterrupt = SSRAM3_MPC_EnableInterrupt, + .DisableInterrupt = SSRAM3_MPC_DisableInterrupt, + .ClearInterrupt = SSRAM3_MPC_ClearInterrupt, + .InterruptState = SSRAM3_MPC_InterruptState, + .LockDown = SSRAM3_MPC_LockDown, +}; +#endif /* RTE_SSRAM3_MPC */ + +#if (RTE_QSPI_MPC) +/* Ranges controlled by this QSPI_MPC */ +static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_S = { + .base = MPC_QSPI_RANGE_BASE_S, + .limit = MPC_QSPI_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_NS = { + .base = MPC_QSPI_RANGE_BASE_NS, + .limit = MPC_QSPI_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_QSPI_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_QSPI_RANGE_LIST[MPC_QSPI_RANGE_LIST_LEN] = { + &MPC_QSPI_RANGE_S, + &MPC_QSPI_RANGE_NS + }; + +/* QSPI_MPC Driver wrapper functions */ +static int32_t QSPI_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_QSPI_DEV, + MPC_QSPI_RANGE_LIST, + MPC_QSPI_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t QSPI_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_QSPI_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_QSPI_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_QSPI_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_QSPI_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_QSPI_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t QSPI_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_QSPI_DEV); + + return error_trans(ret); +} + +static void QSPI_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_QSPI_DEV); +} + + +static void QSPI_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_QSPI_DEV); +} + +static uint32_t QSPI_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_QSPI_DEV); +} + +static int32_t QSPI_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_QSPI_DEV); +} + +/* QSPI1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_QSPI_MPC; +ARM_DRIVER_MPC Driver_QSPI_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = QSPI_MPC_Initialize, + .Uninitialize = QSPI_MPC_Uninitialize, + .GetBlockSize = QSPI_MPC_GetBlockSize, + .GetCtrlConfig = QSPI_MPC_GetCtrlConfig, + .SetCtrlConfig = QSPI_MPC_SetCtrlConfig, + .ConfigRegion = QSPI_MPC_ConfigRegion, + .GetRegionConfig = QSPI_MPC_GetRegionConfig, + .EnableInterrupt = QSPI_MPC_EnableInterrupt, + .DisableInterrupt = QSPI_MPC_DisableInterrupt, + .ClearInterrupt = QSPI_MPC_ClearInterrupt, + .InterruptState = QSPI_MPC_InterruptState, + .LockDown = QSPI_MPC_LockDown, +}; +#endif /* RTE_QSPI_MPC */ + +#if (RTE_EFLASH0_MPC) +/* Ranges controlled by this EFLASH0_MPC */ +static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_S = { + .base = MPC_EFLASH0_RANGE_BASE_S, + .limit = MPC_EFLASH0_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_NS = { + .base = MPC_EFLASH0_RANGE_BASE_NS, + .limit = MPC_EFLASH0_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_EFLASH0_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_EFLASH0_RANGE_LIST[MPC_EFLASH0_RANGE_LIST_LEN]= + {&MPC_EFLASH0_RANGE_S, &MPC_EFLASH0_RANGE_NS}; + +/* EFLASH0_MPC Driver wrapper functions */ +static int32_t EFLASH0_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_EFLASH0_DEV, + MPC_EFLASH0_RANGE_LIST, + MPC_EFLASH0_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t EFLASH0_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_EFLASH0_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_EFLASH0_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_EFLASH0_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_EFLASH0_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_EFLASH0_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t EFLASH0_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_EFLASH0_DEV); + + return error_trans(ret); +} + +static void EFLASH0_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_EFLASH0_DEV); +} + + +static void EFLASH0_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_EFLASH0_DEV); +} + +static uint32_t EFLASH0_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_EFLASH0_DEV); +} + +static int32_t EFLASH0_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_EFLASH0_DEV); +} + +/* EFLASH0_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_EFLASH0_MPC; +ARM_DRIVER_MPC Driver_EFLASH0_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = EFLASH0_MPC_Initialize, + .Uninitialize = EFLASH0_MPC_Uninitialize, + .GetBlockSize = EFLASH0_MPC_GetBlockSize, + .GetCtrlConfig = EFLASH0_MPC_GetCtrlConfig, + .SetCtrlConfig = EFLASH0_MPC_SetCtrlConfig, + .ConfigRegion = EFLASH0_MPC_ConfigRegion, + .GetRegionConfig = EFLASH0_MPC_GetRegionConfig, + .EnableInterrupt = EFLASH0_MPC_EnableInterrupt, + .DisableInterrupt = EFLASH0_MPC_DisableInterrupt, + .ClearInterrupt = EFLASH0_MPC_ClearInterrupt, + .InterruptState = EFLASH0_MPC_InterruptState, + .LockDown = EFLASH0_MPC_LockDown, +}; +#endif /* RTE_EFLASH0_MPC */ + +#if (RTE_EFLASH1_MPC) +/* Ranges controlled by this EFLASH1_MPC */ +static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_S = { + .base = MPC_EFLASH1_RANGE_BASE_S, + .limit = MPC_EFLASH1_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_NS = { + .base = MPC_EFLASH1_RANGE_BASE_NS, + .limit = MPC_EFLASH1_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_EFLASH1_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_EFLASH1_RANGE_LIST[MPC_EFLASH1_RANGE_LIST_LEN]= + {&MPC_EFLASH1_RANGE_S, &MPC_EFLASH1_RANGE_NS}; + +/* EFLASH1_MPC Driver wrapper functions */ +static int32_t EFLASH1_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_EFLASH1_DEV, + MPC_EFLASH1_RANGE_LIST, + MPC_EFLASH1_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t EFLASH1_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_EFLASH1_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_EFLASH1_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_EFLASH1_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_EFLASH1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_EFLASH1_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t EFLASH1_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_EFLASH1_DEV); + + return error_trans(ret); +} + +static void EFLASH1_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_EFLASH1_DEV); +} + + +static void EFLASH1_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_EFLASH1_DEV); +} + +static uint32_t EFLASH1_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_EFLASH1_DEV); +} + +static int32_t EFLASH1_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_EFLASH1_DEV); +} + +/* EFLASH1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_EFLASH1_MPC; +ARM_DRIVER_MPC Driver_EFLASH1_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = EFLASH1_MPC_Initialize, + .Uninitialize = EFLASH1_MPC_Uninitialize, + .GetBlockSize = EFLASH1_MPC_GetBlockSize, + .GetCtrlConfig = EFLASH1_MPC_GetCtrlConfig, + .SetCtrlConfig = EFLASH1_MPC_SetCtrlConfig, + .ConfigRegion = EFLASH1_MPC_ConfigRegion, + .GetRegionConfig = EFLASH1_MPC_GetRegionConfig, + .EnableInterrupt = EFLASH1_MPC_EnableInterrupt, + .DisableInterrupt = EFLASH1_MPC_DisableInterrupt, + .ClearInterrupt = EFLASH1_MPC_ClearInterrupt, + .InterruptState = EFLASH1_MPC_InterruptState, + .LockDown = EFLASH1_MPC_LockDown, +}; +#endif /* RTE_EFLASH1_MPC */ + +#if (RTE_BRAM_MPC) +/* Ranges controlled by this BRAM_MPC */ +static const struct mpc_sie200_memory_range_t MPC_BRAM_RANGE_S = { + .base = MPC_BRAM_RANGE_BASE_S, + .limit = MPC_BRAM_RANGE_LIMIT_S, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_SECURE +}; + +static const struct mpc_sie200_memory_range_t MPC_BRAM_RANGE_NS = { + .base = MPC_BRAM_RANGE_BASE_NS, + .limit = MPC_BRAM_RANGE_LIMIT_NS, + .range_offset = 0, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE +}; + +#define MPC_BRAM_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t* + MPC_BRAM_RANGE_LIST[MPC_BRAM_RANGE_LIST_LEN]= { + &MPC_BRAM_RANGE_S, + &MPC_BRAM_RANGE_NS + }; + +/* BRAM_MPC Driver wrapper functions */ +static int32_t BRAM_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_BRAM_DEV, + MPC_BRAM_RANGE_LIST, + MPC_BRAM_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t BRAM_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_BRAM_DEV, blk_size); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_BRAM_DEV, ctrl_val); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_BRAM_DEV, ctrl); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_BRAM_DEV, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_BRAM_DEV, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t BRAM_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_BRAM_DEV); + + return error_trans(ret); +} + +static void BRAM_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_BRAM_DEV); +} + + +static void BRAM_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_BRAM_DEV); +} + +static uint32_t BRAM_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_BRAM_DEV); +} + +static int32_t BRAM_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_BRAM_DEV); +} + +/* BRAM_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_BRAM_MPC; +ARM_DRIVER_MPC Driver_BRAM_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = BRAM_MPC_Initialize, + .Uninitialize = BRAM_MPC_Uninitialize, + .GetBlockSize = BRAM_MPC_GetBlockSize, + .GetCtrlConfig = BRAM_MPC_GetCtrlConfig, + .SetCtrlConfig = BRAM_MPC_SetCtrlConfig, + .ConfigRegion = BRAM_MPC_ConfigRegion, + .GetRegionConfig = BRAM_MPC_GetRegionConfig, + .EnableInterrupt = BRAM_MPC_EnableInterrupt, + .DisableInterrupt = BRAM_MPC_DisableInterrupt, + .ClearInterrupt = BRAM_MPC_ClearInterrupt, + .InterruptState = BRAM_MPC_InterruptState, + .LockDown = BRAM_MPC_LockDown, +}; +#endif /* RTE_BRAM_MPC */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_PPC.c b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_PPC.c new file mode 100644 index 00000000..9ffc35f5 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_PPC.c @@ -0,0 +1,965 @@ +/* + * Copyright (c) 2016-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_PPC.h" + +#include "cmsis_driver_config.h" +#include "RTE_Device.h" + +/* Driver version */ +#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_PPC_API_VERSION, + ARM_PPC_DRV_VERSION +}; + +static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void) +{ + return DriverVersion; +} + +#if (RTE_AHB_PPC0) +/* AHB PPC0 Driver wrapper functions */ +static int32_t AHB_PPC0_Initialize(void) +{ + ppc_sse200_init(&AHB_PPC0_DEV, AHB_PPC0); + + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPC0_Uninitialize(void) +{ + /* Nothing to be done*/ + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&AHB_PPC0_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t AHB_PPC0_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&AHB_PPC0_DEV, periph); +} + +static uint32_t AHB_PPC0_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&AHB_PPC0_DEV, periph); +} + +static int32_t AHB_PPC0_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&AHB_PPC0_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void AHB_PPC0_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&AHB_PPC0_DEV); +} + +static void AHB_PPC0_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&AHB_PPC0_DEV); +} + +static uint32_t AHB_PPC0_InterruptState(void) +{ + return ppc_sse200_irq_state(&AHB_PPC0_DEV); +} + +/* AHB PPC0 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_AHB_PPC0; +ARM_DRIVER_PPC Driver_AHB_PPC0 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = AHB_PPC0_Initialize, + .Uninitialize = AHB_PPC0_Uninitialize, + .ConfigPeriph = AHB_PPC0_ConfigPeriph, + .IsPeriphSecure = AHB_PPC0_IsPeriphSecure, + .IsPeriphPrivOnly = AHB_PPC0_IsPeriphPrivOnly, + .EnableInterrupt = AHB_PPC0_EnableInterrupt, + .DisableInterrupt = AHB_PPC0_DisableInterrupt, + .ClearInterrupt = AHB_PPC0_ClearInterrupt, + .InterruptState = AHB_PPC0_InterruptState +}; +#endif /* RTE_AHB_PPC0 */ + +#if (RTE_AHB_PPCEXP0) +/* AHB PPCEXP0 Driver wrapper functions */ +static int32_t AHB_PPCEXP0_Initialize(void) +{ + ppc_sse200_init(&AHB_PPCEXP0_DEV, AHB_PPC_EXP0); + + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP0_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV, periph); +} + +static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV, periph); +} + +static int32_t AHB_PPCEXP0_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void AHB_PPCEXP0_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV); +} + +static void AHB_PPCEXP0_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV); +} + +static uint32_t AHB_PPCEXP0_InterruptState(void) +{ + return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV); +} + +/* AHB PPCEXP0 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0; +ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = AHB_PPCEXP0_Initialize, + .Uninitialize = AHB_PPCEXP0_Uninitialize, + .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph, + .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure, + .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly, + .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt, + .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt, + .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt, + .InterruptState = AHB_PPCEXP0_InterruptState +}; +#endif /* RTE_AHB_PPCEXP0 */ + +#if (RTE_AHB_PPCEXP1) +/* AHB PPCEXP1 Driver wrapper functions */ +static int32_t AHB_PPCEXP1_Initialize(void) +{ + ppc_sse200_init(&AHB_PPCEXP1_DEV, AHB_PPC_EXP1); + + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP1_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV, periph); +} + +static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV, periph); +} + +static int32_t AHB_PPCEXP1_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void AHB_PPCEXP1_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV); +} + +static void AHB_PPCEXP1_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV); +} + +static uint32_t AHB_PPCEXP1_InterruptState(void) +{ + return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV); +} + +/* AHB PPCEXP1 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1; +ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = AHB_PPCEXP1_Initialize, + .Uninitialize = AHB_PPCEXP1_Uninitialize, + .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph, + .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure, + .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly, + .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt, + .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt, + .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt, + .InterruptState = AHB_PPCEXP1_InterruptState +}; +#endif /* RTE_AHB_PPCEXP1 */ + +#if (RTE_AHB_PPCEXP2) +/* AHB PPCEXP2 Driver wrapper functions */ +static int32_t AHB_PPCEXP2_Initialize(void) +{ + ppc_sse200_init(&AHB_PPCEXP2_DEV, AHB_PPC_EXP2); + + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP2_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV, periph); +} + +static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV, periph); +} + +static int32_t AHB_PPCEXP2_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void AHB_PPCEXP2_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV); +} + +static void AHB_PPCEXP2_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV); +} + +static uint32_t AHB_PPCEXP2_InterruptState(void) +{ + return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV); +} + +/* AHB PPCEXP2 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2; +ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = AHB_PPCEXP2_Initialize, + .Uninitialize = AHB_PPCEXP2_Uninitialize, + .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph, + .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure, + .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly, + .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt, + .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt, + .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt, + .InterruptState = AHB_PPCEXP2_InterruptState +}; +#endif /* RTE_AHB_PPCEXP2 */ + +#if (RTE_AHB_PPCEXP3) +/* AHB PPCEXP3 Driver wrapper functions */ +static int32_t AHB_PPCEXP3_Initialize(void) +{ + ppc_sse200_init(&AHB_PPCEXP3_DEV, AHB_PPC_EXP3); + + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP3_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV, periph); +} + +static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV, periph); +} + +static int32_t AHB_PPCEXP3_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void AHB_PPCEXP3_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV); +} + +static void AHB_PPCEXP3_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV); +} + +static uint32_t AHB_PPCEXP3_InterruptState(void) +{ + return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV); +} + +/* AHB PPCEXP3 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3; +ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = AHB_PPCEXP3_Initialize, + .Uninitialize = AHB_PPCEXP3_Uninitialize, + .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph, + .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure, + .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly, + .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt, + .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt, + .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt, + .InterruptState = AHB_PPCEXP3_InterruptState +}; +#endif /* RTE_AHB_PPCEXP3 */ + +#if (RTE_APB_PPC0) +/* APB PPC0 Driver wrapper functions */ +static int32_t APB_PPC0_Initialize(void) +{ + ppc_sse200_init(&APB_PPC0_DEV, APB_PPC0); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPC0_Uninitialize(void) +{ + /* Nothing to be done*/ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPC0_DEV, periph); +} + +static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV, periph); +} + +static int32_t APB_PPC0_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPC0_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPC0_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPC0_DEV); +} + +static void APB_PPC0_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPC0_DEV); +} + +static uint32_t APB_PPC0_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPC0_DEV); +} + +/* APB PPC0 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPC0; +ARM_DRIVER_PPC Driver_APB_PPC0 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPC0_Initialize, + .Uninitialize = APB_PPC0_Uninitialize, + .ConfigPeriph = APB_PPC0_ConfigPeriph, + .IsPeriphSecure = APB_PPC0_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPC0_EnableInterrupt, + .DisableInterrupt = APB_PPC0_DisableInterrupt, + .ClearInterrupt = APB_PPC0_ClearInterrupt, + .InterruptState = APB_PPC0_InterruptState +}; +#endif /* RTE_APB_PPC0 */ + +#if (RTE_APB_PPC1) +/* APB PPC1 Driver wrapper functions */ +static int32_t APB_PPC1_Initialize(void) +{ + ppc_sse200_init(&APB_PPC1_DEV, APB_PPC1); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPC1_Uninitialize(void) +{ + /* Nothing to be done*/ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPC1_DEV, periph); +} + +static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV, periph); +} +static int32_t APB_PPC1_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPC1_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPC1_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPC1_DEV); +} + +static void APB_PPC1_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPC1_DEV); +} + +static uint32_t APB_PPC1_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPC1_DEV); +} + +/* APB PPC1 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPC1; +ARM_DRIVER_PPC Driver_APB_PPC1 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPC1_Initialize, + .Uninitialize = APB_PPC1_Uninitialize, + .ConfigPeriph = APB_PPC1_ConfigPeriph, + .IsPeriphSecure = APB_PPC1_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPC1_EnableInterrupt, + .DisableInterrupt = APB_PPC1_DisableInterrupt, + .ClearInterrupt = APB_PPC1_ClearInterrupt, + .InterruptState = APB_PPC1_InterruptState +}; +#endif /* RTE_APB_PPC1 */ + +#if (RTE_APB_PPCEXP0) +/* APB PPCEXP0 Driver wrapper functions */ +static int32_t APB_PPCEXP0_Initialize(void) +{ + ppc_sse200_init(&APB_PPCEXP0_DEV, APB_PPC_EXP0); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP0_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV, periph); +} + +static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV, periph); +} + +static int32_t APB_PPCEXP0_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPCEXP0_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPCEXP0_DEV); +} + +static void APB_PPCEXP0_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPCEXP0_DEV); +} + +static uint32_t APB_PPCEXP0_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPCEXP0_DEV); +} + +/* APB PPCEXP0 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPCEXP0; +ARM_DRIVER_PPC Driver_APB_PPCEXP0 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPCEXP0_Initialize, + .Uninitialize = APB_PPCEXP0_Uninitialize, + .ConfigPeriph = APB_PPCEXP0_ConfigPeriph, + .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPCEXP0_EnableInterrupt, + .DisableInterrupt = APB_PPCEXP0_DisableInterrupt, + .ClearInterrupt = APB_PPCEXP0_ClearInterrupt, + .InterruptState = APB_PPCEXP0_InterruptState +}; +#endif /* RTE_APB_PPCEXP0 */ + +#if (RTE_APB_PPCEXP1) +/* APB PPCEXP1 Driver wrapper functions */ +static int32_t APB_PPCEXP1_Initialize(void) +{ + ppc_sse200_init(&APB_PPCEXP1_DEV, APB_PPC_EXP1); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP1_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV, periph); +} + +static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV, periph); +} + +static int32_t APB_PPCEXP1_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPCEXP1_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPCEXP1_DEV); +} + +static void APB_PPCEXP1_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPCEXP1_DEV); +} + +static uint32_t APB_PPCEXP1_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPCEXP1_DEV); +} + +/* APB PPCEXP1 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPCEXP1; +ARM_DRIVER_PPC Driver_APB_PPCEXP1 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPCEXP1_Initialize, + .Uninitialize = APB_PPCEXP1_Uninitialize, + .ConfigPeriph = APB_PPCEXP1_ConfigPeriph, + .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPCEXP1_EnableInterrupt, + .DisableInterrupt = APB_PPCEXP1_DisableInterrupt, + .ClearInterrupt = APB_PPCEXP1_ClearInterrupt, + .InterruptState = APB_PPCEXP1_InterruptState +}; +#endif /* RTE_APB_PPCEXP1 */ + +#if (RTE_APB_PPCEXP2) +/* APB PPCEXP2 Driver wrapper functions */ +static int32_t APB_PPCEXP2_Initialize(void) +{ + ppc_sse200_init(&APB_PPCEXP2_DEV, APB_PPC_EXP2); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP2_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV, periph); +} + +static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV, periph); +} + +static int32_t APB_PPCEXP2_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPCEXP2_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPCEXP2_DEV); +} + +static void APB_PPCEXP2_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPCEXP2_DEV); +} + +static uint32_t APB_PPCEXP2_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPCEXP2_DEV); +} + +/* APB PPCEXP2 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPCEXP2; +ARM_DRIVER_PPC Driver_APB_PPCEXP2 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPCEXP2_Initialize, + .Uninitialize = APB_PPCEXP2_Uninitialize, + .ConfigPeriph = APB_PPCEXP2_ConfigPeriph, + .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPCEXP2_EnableInterrupt, + .DisableInterrupt = APB_PPCEXP2_DisableInterrupt, + .ClearInterrupt = APB_PPCEXP2_ClearInterrupt, + .InterruptState = APB_PPCEXP2_InterruptState +}; +#endif /* RTE_APB_PPCEXP2 */ + +#if (RTE_APB_PPCEXP3) +/* APB PPCEXP3 Driver wrapper functions */ +static int32_t APB_PPCEXP3_Initialize(void) +{ + ppc_sse200_init(&APB_PPCEXP3_DEV, APB_PPC_EXP3); + + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP3_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t APB_PPCEXP3_ConfigPeriph( + uint8_t periph, ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV, periph, + (enum ppc_sse200_sec_attr_t)sec_attr, + (enum ppc_sse200_priv_attr_t)priv_attr); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph) +{ + return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV, periph); +} + +static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph) +{ + return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV, periph); +} + +static int32_t APB_PPCEXP3_EnableInterrupt(void) +{ + enum ppc_sse200_error_t ret; + + ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV); + + if (ret != PPC_SSE200_ERR_NONE) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +static void APB_PPCEXP3_DisableInterrupt(void) +{ + ppc_sse200_irq_disable(&APB_PPCEXP3_DEV); +} + +static void APB_PPCEXP3_ClearInterrupt(void) +{ + ppc_sse200_clear_irq(&APB_PPCEXP3_DEV); +} + +static uint32_t APB_PPCEXP3_InterruptState(void) +{ + return ppc_sse200_irq_state(&APB_PPCEXP3_DEV); +} + +/* APB PPCEXP3 Driver CMSIS access structure */ +extern ARM_DRIVER_PPC Driver_APB_PPCEXP3; +ARM_DRIVER_PPC Driver_APB_PPCEXP3 = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = APB_PPCEXP3_Initialize, + .Uninitialize = APB_PPCEXP3_Uninitialize, + .ConfigPeriph = APB_PPCEXP3_ConfigPeriph, + .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure, + .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly, + .EnableInterrupt = APB_PPCEXP3_EnableInterrupt, + .DisableInterrupt = APB_PPCEXP3_DisableInterrupt, + .ClearInterrupt = APB_PPCEXP3_ClearInterrupt, + .InterruptState = APB_PPCEXP3_InterruptState +}; +#endif /* RTE_APB_PPCEXP3 */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_USART.c b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_USART.c new file mode 100644 index 00000000..f127e761 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/Driver_USART.c @@ -0,0 +1,701 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_USART.h" + +#include "cmsis_driver_config.h" +#include "RTE_Device.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +/* Driver version */ +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */ + 0 /* Reserved */ +}; + +static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +typedef struct { + struct uart_cmsdk_dev_t *dev; /* UART device structure */ + uint32_t tx_nbr_bytes; /* Number of bytes transfered */ + uint32_t rx_nbr_bytes; /* Number of bytes recevied */ + ARM_USART_SignalEvent_t cb_event; /* Callback function for events */ +} UARTx_Resources; + +static int32_t ARM_USARTx_Initialize(UARTx_Resources *uart_dev) +{ + /* Initializes generic UART driver */ + uart_cmsdk_init(uart_dev->dev, PeripheralClock); + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_PowerControl(UARTx_Resources *uart_dev, + ARM_POWER_STATE state) +{ + ARG_UNUSED(uart_dev); + + switch (state) { + case ARM_POWER_OFF: + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + /* default: The default is not defined intentionally to force the + * compiler to check that all the enumeration values are + * covered in the switch.*/ + } +} + +static int32_t ARM_USARTx_Send(UARTx_Resources *uart_dev, const void *data, + uint32_t num) +{ + const uint8_t *p_data = (const uint8_t *)data; + + if ((data == NULL) || (num == 0U)) { + /* Invalid parameters */ + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Resets previous TX counter */ + uart_dev->tx_nbr_bytes = 0; + + while (uart_dev->tx_nbr_bytes != num) { + /* Waits until UART is ready to transmit */ + while (!uart_cmsdk_tx_ready(uart_dev->dev)) { + }; + + /* As UART is ready to transmit at this point, the write function can + * not return any transmit error */ + (void)uart_cmsdk_write(uart_dev->dev, *p_data); + + uart_dev->tx_nbr_bytes++; + p_data++; + } + + /* Waits until character is transmited */ + while (!uart_cmsdk_tx_ready(uart_dev->dev)) { + }; + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Receive(UARTx_Resources *uart_dev, + void *data, uint32_t num) +{ + uint8_t *p_data = (uint8_t *)data; + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Resets previous RX counter */ + uart_dev->rx_nbr_bytes = 0; + + while (uart_dev->rx_nbr_bytes != num) { + /* Waits until one character is received */ + while (!uart_cmsdk_rx_ready(uart_dev->dev)){}; + + /* As UART has received one byte, the read can not + * return any receive error at this point */ + (void)uart_cmsdk_read(uart_dev->dev, p_data); + + uart_dev->rx_nbr_bytes++; + p_data++; + } + + return ARM_DRIVER_OK; +} + +static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources *uart_dev) +{ + return uart_dev->tx_nbr_bytes; +} + +static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources *uart_dev) +{ + return uart_dev->rx_nbr_bytes; +} + +static int32_t ARM_USARTx_Control(UARTx_Resources *uart_dev, uint32_t control, + uint32_t arg) +{ + switch (control & ARM_USART_CONTROL_Msk) { + case ARM_USART_MODE_ASYNCHRONOUS: + if (uart_cmsdk_set_baudrate(uart_dev->dev, arg) + != UART_CMSDK_ERR_NONE) { + return ARM_USART_ERROR_BAUDRATE; + } + break; + /* Unsupported command */ + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Data bits */ + if (control & ARM_USART_DATA_BITS_Msk) { + /* Data bit is not configurable */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Parity */ + if (control & ARM_USART_PARITY_Msk) { + /* Parity is not configurable */ + return ARM_USART_ERROR_PARITY; + } + + /* USART Stop bits */ + if (control & ARM_USART_STOP_BITS_Msk) { + /* Stop bit is not configurable */ + return ARM_USART_ERROR_STOP_BITS; + } + + return ARM_DRIVER_OK; +} + +#if (RTE_USART0) +/* USART0 Driver wrapper functions */ +static UARTx_Resources USART0_DEV = { + .dev = &UART0_CMSDK_DEV, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART0_DEV); +} + +static int32_t ARM_USART0_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART0_DEV, state); +} + +static int32_t ARM_USART0_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART0_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART0_DEV); +} + +static uint32_t ARM_USART0_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART0_DEV); +} +static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART0_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART0_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART0; +ARM_DRIVER_USART Driver_USART0 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART0_Initialize, + ARM_USART0_Uninitialize, + ARM_USART0_PowerControl, + ARM_USART0_Send, + ARM_USART0_Receive, + ARM_USART0_Transfer, + ARM_USART0_GetTxCount, + ARM_USART0_GetRxCount, + ARM_USART0_Control, + ARM_USART0_GetStatus, + ARM_USART0_SetModemControl, + ARM_USART0_GetModemStatus +}; +#endif /* RTE_USART0 */ + +#if (RTE_USART1) +/* USART1 Driver wrapper functions */ +static UARTx_Resources USART1_DEV = { + .dev = &UART1_CMSDK_DEV, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART1_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART1_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART1_DEV); +} + +static int32_t ARM_USART1_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART1_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART1_DEV, state); +} + +static int32_t ARM_USART1_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART1_DEV, data, num); +} + +static int32_t ARM_USART1_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART1_DEV, data, num); +} + +static int32_t ARM_USART1_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART1_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART1_DEV); +} + +static uint32_t ARM_USART1_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART1_DEV); +} +static int32_t ARM_USART1_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART1_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART1_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART1_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART1_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART1; +ARM_DRIVER_USART Driver_USART1 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART1_Initialize, + ARM_USART1_Uninitialize, + ARM_USART1_PowerControl, + ARM_USART1_Send, + ARM_USART1_Receive, + ARM_USART1_Transfer, + ARM_USART1_GetTxCount, + ARM_USART1_GetRxCount, + ARM_USART1_Control, + ARM_USART1_GetStatus, + ARM_USART1_SetModemControl, + ARM_USART1_GetModemStatus +}; +#endif /* RTE_USART1 */ + +#if (RTE_USART2) +/* USART2 Driver wrapper functions */ +static UARTx_Resources USART2_DEV = { + .dev = &UART2_CMSDK_DEV, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART2_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART2_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART2_DEV); +} + +static int32_t ARM_USART2_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART2_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART2_DEV, state); +} + +static int32_t ARM_USART2_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART2_DEV, data, num); +} + +static int32_t ARM_USART2_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART2_DEV, data, num); +} + +static int32_t ARM_USART2_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART2_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART2_DEV); +} + +static uint32_t ARM_USART2_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART2_DEV); +} +static int32_t ARM_USART2_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART2_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART2_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART2_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART2_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART2; +ARM_DRIVER_USART Driver_USART2 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART2_Initialize, + ARM_USART2_Uninitialize, + ARM_USART2_PowerControl, + ARM_USART2_Send, + ARM_USART2_Receive, + ARM_USART2_Transfer, + ARM_USART2_GetTxCount, + ARM_USART2_GetRxCount, + ARM_USART2_Control, + ARM_USART2_GetStatus, + ARM_USART2_SetModemControl, + ARM_USART2_GetModemStatus +}; +#endif /* RTE_USART2 */ + +#if (RTE_USART3) +/* USART3 Driver wrapper functions */ +static UARTx_Resources USART3_DEV = { + .dev = &UART3_CMSDK_DEV, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART3_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART3_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART3_DEV); +} + +static int32_t ARM_USART3_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART3_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART3_DEV, state); +} + +static int32_t ARM_USART3_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART3_DEV, data, num); +} + +static int32_t ARM_USART3_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART3_DEV, data, num); +} + +static int32_t ARM_USART3_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART3_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART3_DEV); +} + +static uint32_t ARM_USART3_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART3_DEV); +} +static int32_t ARM_USART3_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART3_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART3_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART3_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART3_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART3; +ARM_DRIVER_USART Driver_USART3 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART3_Initialize, + ARM_USART3_Uninitialize, + ARM_USART3_PowerControl, + ARM_USART3_Send, + ARM_USART3_Receive, + ARM_USART3_Transfer, + ARM_USART3_GetTxCount, + ARM_USART3_GetRxCount, + ARM_USART3_Control, + ARM_USART3_GetStatus, + ARM_USART3_SetModemControl, + ARM_USART3_GetModemStatus +}; +#endif /* RTE_USART3 */ + +#if (RTE_USART4) +/* USART4 Driver wrapper functions */ +static UARTx_Resources USART4_DEV = { + .dev = &UART4_CMSDK_DEV, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART4_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART4_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART4_DEV); +} + +static int32_t ARM_USART4_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART4_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART4_DEV, state); +} + +static int32_t ARM_USART4_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART4_DEV, data, num); +} + +static int32_t ARM_USART4_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART4_DEV, data, num); +} + +static int32_t ARM_USART4_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART4_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART4_DEV); +} + +static uint32_t ARM_USART4_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART4_DEV); +} +static int32_t ARM_USART4_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART4_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART4_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART4_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART4_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART4; +ARM_DRIVER_USART Driver_USART4 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART4_Initialize, + ARM_USART4_Uninitialize, + ARM_USART4_PowerControl, + ARM_USART4_Send, + ARM_USART4_Receive, + ARM_USART4_Transfer, + ARM_USART4_GetTxCount, + ARM_USART4_GetRxCount, + ARM_USART4_Control, + ARM_USART4_GetStatus, + ARM_USART4_SetModemControl, + ARM_USART4_GetModemStatus +}; +#endif /* RTE_USART4 */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/RTE_Device.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/RTE_Device.h new file mode 100644 index 00000000..0f110647 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/RTE_Device.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 0 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::Drivers:USART +#define RTE_USART2 0 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2] + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::Drivers:USART +#define RTE_USART3 0 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3] + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::Drivers:USART +#define RTE_USART4 0 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4] + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::Drivers:USART +#define RTE_USART5 0 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5] + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 1 +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 1 +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] + +// MPC (Memory Protection Controller) [Driver_ISRAM2_MPC] +// Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC +#define RTE_ISRAM2_MPC 1 +// MPC (Memory Protection Controller) [Driver_ISRAM2_MPC] + +// MPC (Memory Protection Controller) [Driver_ISRAM3_MPC] +// Configuration settings for Driver_ISRAM3_MPC in component ::Drivers:MPC +#define RTE_ISRAM3_MPC 1 +// MPC (Memory Protection Controller) [Driver_ISRAM3_MPC] + +// MPC (Memory Protection Controller) [Driver_BRAM_MPC] +// Configuration settings for Driver_BRAM_MPC in component ::Drivers:MPC +#define RTE_BRAM_MPC 0 +// MPC (Memory Protection Controller) [Driver_SRAM1_MPC] + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 1 +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] + +// MPC (Memory Protection Controller) [Driver_DDR4_MPC] +// Configuration settings for Driver_DDR4_MPC in component ::Drivers:MPC +#define RTE_DDR4_MPC 0 +// MPC (Memory Protection Controller) [Driver_DDR4_MPC] + +// PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0] +// Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:MPC +#define RTE_AHB_PPCEXP0 1 +// PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0] + +// PPC (Peripheral Protection Controller) [Driver_APB_PPC0] +// Configuration settings for Driver_APB_PPC0 in component ::Drivers:MPC +#define RTE_APB_PPC0 1 +// PPC (Peripheral Protection Controller) [Driver_APB_PPC0] + +// PPC (Peripheral Protection Controller) [Driver_APB_PPC1] +// Configuration settings for Driver_APB_PPC1 in component ::Drivers:MPC +#define RTE_APB_PPC1 1 +// PPC (Peripheral Protection Controller) [Driver_APB_PPC1] + +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0] +// Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:MPC +#define RTE_APB_PPCEXP0 1 +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0] + +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1] +// Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:MPC +#define RTE_APB_PPCEXP1 1 +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1] + +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2] +// Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:MPC +#define RTE_APB_PPCEXP2 1 +// PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2] + +// Flash device emulated by BRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 +// Flash device emulated by BRAM [Driver_Flash0] + +#endif /* __RTE_DEVICE_H */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/cmsis_driver_config.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/cmsis_driver_config.h new file mode 100644 index 00000000..0644561e --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/config/cmsis_driver_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "platform_description.h" +#include "device_definition.h" + +#define UART0_CMSDK_DEV ARM_UART0_DEV_NS + +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#define MPC_ISRAM1_DEV MPC_ISRAM1_DEV_S +#define MPC_ISRAM2_DEV MPC_ISRAM2_DEV_S +#define MPC_ISRAM3_DEV MPC_ISRAM3_DEV_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +#define AHB_PPCEXP0_DEV AHB_PPCEXP0_DEV_S +#define APB_PPC0_DEV APB_PPC0_DEV_S +#define APB_PPC1_DEV APB_PPC1_DEV_S +#define APB_PPCEXP0_DEV APB_PPCEXP0_DEV_S +#define APB_PPCEXP1_DEV APB_PPCEXP1_DEV_S +#define APB_PPCEXP2_DEV APB_PPCEXP2_DEV_S + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Common.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Common.h new file mode 100644 index 00000000..cdf44b33 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Common.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Jan 2014 + * $Revision: V2.00 + * + * Project: Common Driver definitions + */ + +/* History: + * Version 2.00 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_COMMON_H +#define __DRIVER_COMMON_H + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* __DRIVER_COMMON_H */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Flash.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Flash.h new file mode 100644 index 00000000..287add13 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_Flash.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.1 + * + * Project: Flash Driver definitions + */ + +/* History: + * Version 2.1 + * ARM_FLASH_STATUS made volatile + * Version 2.0 + * Renamed driver NOR -> Flash (more generic) + * Non-blocking operation + * Added Events, Status and Capabilities + * Linked Flash information (GetInfo) + * Version 1.11 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_FLASH_H_ +#define DRIVER_FLASH_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */ + + +#define _ARM_Driver_Flash_(n) Driver_Flash##n +#define ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n) + + +#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 } + +/** +\brief Flash Sector information +*/ +typedef struct _ARM_FLASH_SECTOR { + uint32_t start; ///< Sector Start address + uint32_t end; ///< Sector End address (start+size-1) +} const ARM_FLASH_SECTOR; + +/** +\brief Flash information +*/ +typedef struct _ARM_FLASH_INFO { + ARM_FLASH_SECTOR *sector_info; ///< Sector layout information (NULL=Uniform sectors) + uint32_t sector_count; ///< Number of sectors + uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used) + uint32_t page_size; ///< Optimal programming page size in bytes + uint32_t program_unit; ///< Smallest programmable unit in bytes + uint8_t erased_value; ///< Contents of erased memory (usually 0xFF) +} const ARM_FLASH_INFO; + + +/** +\brief Flash Status +*/ +typedef volatile struct _ARM_FLASH_STATUS { + uint32_t busy : 1; ///< Flash busy flag + uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) + uint32_t reserved : 30; +} ARM_FLASH_STATUS; + + +/****** Flash Event *****/ +#define ARM_FLASH_EVENT_READY (1UL << 0) ///< Flash Ready +#define ARM_FLASH_EVENT_ERROR (1UL << 1) ///< Read/Program/Erase Error + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_FLASH_CAPABILITIES +*/ +/** + \fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event) + \brief Initialize the Flash Interface. + \param[in] cb_event Pointer to \ref ARM_Flash_SignalEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_Uninitialize (void) + \brief De-initialize the Flash Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state) + \brief Control the Flash interface power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt) + \brief Read data from Flash. + \param[in] addr Data address. + \param[out] data Pointer to a buffer storing the data read from Flash. + \param[in] cnt Number of data items to read. + \return number of data items read or \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt) + \brief Program data to Flash. + \param[in] addr Data address. + \param[in] data Pointer to a buffer containing the data to be programmed to Flash. + \param[in] cnt Number of data items to program. + \return number of data items programmed or \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_EraseSector (uint32_t addr) + \brief Erase Flash Sector. + \param[in] addr Sector address + \return \ref execution_status +*/ +/** + \fn int32_t ARM_Flash_EraseChip (void) + \brief Erase complete Flash. + Optional function for faster full chip erase. + \return \ref execution_status +*/ +/** + \fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void) + \brief Get Flash status. + \return Flash status \ref ARM_FLASH_STATUS +*/ +/** + \fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void) + \brief Get Flash information. + \return Pointer to Flash information \ref ARM_FLASH_INFO +*/ + +/** + \fn void ARM_Flash_SignalEvent (uint32_t event) + \brief Signal Flash event. + \param[in] event Event notification mask + \return none +*/ + +typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event. + + +/** +\brief Flash Driver Capabilities. +*/ +typedef struct _ARM_FLASH_CAPABILITIES { + uint32_t event_ready : 1; ///< Signal Flash Ready event + uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit + uint32_t erase_chip : 1; ///< Supports EraseChip operation + uint32_t reserved : 28; ///< Reserved (must be zero) +} ARM_FLASH_CAPABILITIES; + + +/** +\brief Access structure of the Flash Driver +*/ +typedef struct _ARM_DRIVER_FLASH { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version. + ARM_FLASH_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_Flash_SignalEvent_t cb_event); ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power. + int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash. + int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash. + int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector. + int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash. + ARM_FLASH_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status. + ARM_FLASH_INFO * (*GetInfo) (void); ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information. +} const ARM_DRIVER_FLASH; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_FLASH_H_ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_MPC.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_MPC.h new file mode 100644 index 00000000..9ed84ba7 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_MPC.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __DRIVER_MPC_H +#define __DRIVER_MPC_H + +#include "Driver_Common.h" + +/* API version */ +#define ARM_MPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +/* Error code returned by the driver functions */ +#define ARM_MPC_ERR_NOT_INIT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< MPC not initialized */ +#define ARM_MPC_ERR_NOT_IN_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Address does not belong to a range controlled by the MPC */ +#define ARM_MPC_ERR_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Address is not aligned on the block size of this MPC */ +#define ARM_MPC_ERR_INVALID_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given address range to configure is invalid +#define ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given range cannot be accessed with the wanted security attributes */ +#define ARM_MPC_ERR_UNSPECIFIED (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Unspecified error */ + +/* Security attribute used in various place of the API */ +typedef enum _ARM_MPC_SEC_ATTR { + ARM_MPC_ATTR_SECURE, ///< Secure attribute + ARM_MPC_ATTR_NONSECURE, ///< Non-secure attribute + /* Used when getting the configuration of a memory range and some blocks are + * secure whereas some other are non secure */ + ARM_MPC_ATTR_MIXED, ///< Mixed attribute +} ARM_MPC_SEC_ATTR; + +/* Function documentation */ +/** + \fn ARM_DRIVER_VERSION ARM_MPC_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn int32_t ARM_MPC_Initialize (void) + \brief Initialize MPC Interface. + \return Returns error code. + + \fn int32_t ARM_MPC_Uninitialize (void) + \brief De-initialize MPC Interface. The controlled memory region + should not be accessed after a call to this function, as + it is allowed to configure everything to be secure (to + prevent information leak for example). + \return Returns error code. + + \fn int32_t ARM_MPC_GetBlockSize (uint32_t* blk_size) + \brief Get the block size of the MPC. All regions must be aligned + on this block size (base address and limit+1 address). + \param[out] blk_size: The block size in bytes. + \return Returns error code. + + \fn int32_t ARM_MPC_GetCtrlConfig (uint32_t* ctrl_val) + \brief Get some information on how the MPC IP is configured. + \param[out] ctrl_val: MPC control configuration + \return Returns error code. + + \fn int32_t ARM_MPC_SetCtrlConfig (uint32_t ctrl) + \brief Set new control configuration for the MPC IP. + \param[in] ctrl: New control configuration. + \return Returns error code. + + \fn int32_t ARM_MPC_ConfigRegion (uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) + \brief Configure a memory region (base and limit included). + Both base and limit addresses must belong to the same + memory range, and this range must be managed by this MPC. + Also, some ranges are only allowed to be configured as + secure/non-secure, because of hardware requirements + (security aliases), and only a relevant security attribute + is therefore allowed for such ranges. + \param[in] base: Base address of the region to configure. This + bound is included in the configured region. + This must be aligned on the block size of this MPC. + \param[in] limit: Limit address of the region to configure. This + bound is included in the configured region. + Limit+1 must be aligned on the block size of this MPC. + \param[in] attr: Wanted security attribute of the region. + \return Returns error code. + + \fn int32_t ARM_MPC_GetRegionConfig (uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) + \brief Gets a memory region (base and limit included). + \param[in] base: Base address of the region to poll. This + bound is included. It does not need to be aligned + in any way. + \param[in] limit: Limit address of the region to poll. This + bound is included. (limit+1) does not need to be aligned + in any way. + \param[out] attr: Security attribute of the region. + If the region has mixed secure/non-secure, + a special value is returned (\ref ARM_MPC_SEC_ATTR). + + In case base and limit+1 addresses are not aligned on + the block size, the enclosing region with base and + limit+1 aligned on block size will be queried. + In case of early termination of the function (error), the + security attribute will be set to ARM_MPC_ATTR_MIXED. + \return Returns error code. + + \fn int32_t ARM_MPC_EnableInterrupt (void) + \brief Enable MPC interrupt. + \return Returns error code. + + \fn void ARM_MPC_DisableInterrupt (void) + \brief Disable MPC interrupt. + + \fn void ARM_MPC_ClearInterrupt (void) + \brief Clear MPC interrupt. + + \fn uint32_t ARM_MPC_InterruptState (void) + \brief MPC interrupt state. + \return Returns 1 if the interrupt is active, 0 otherwise. + + \fn int32_t ARM_MPC_LockDown (void) + \brief Lock down the MPC configuration. + \return Returns error code. +*/ + +/** + * \brief Access structure of the MPC Driver. + */ +typedef struct _ARM_DRIVER_MPC { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MPC_GetVersion : Get driver version. + int32_t (*Initialize) (void); ///< Pointer to \ref ARM_MPC_Initialize : Initialize the MPC Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MPC_Uninitialize : De-initialize the MPC Interface. + int32_t (*GetBlockSize) (uint32_t* blk_size); ///< Pointer to \ref ARM_MPC_GetBlockSize : Get MPC block size + int32_t (*GetCtrlConfig) (uint32_t* ctrl_val); ///< Pointer to \ref ARM_MPC_GetCtrlConfig : Get the MPC control configuration flags. + int32_t (*SetCtrlConfig) (uint32_t ctrl); ///< Pointer to \ref ARM_MPC_SetCtrlConfig : Set the MPC control configuration flags. + int32_t (*ConfigRegion) (uintptr_t base, uintptr_t limit, ARM_MPC_SEC_ATTR attr); ///< Pointer to \ref ARM_MPC_ConfigRegion : Configure a region using the driver for the specific MPC. + int32_t (*GetRegionConfig) (uintptr_t base, uintptr_t limit, ARM_MPC_SEC_ATTR *attr); ///< Pointer to \ref ARM_MPC_GetRegionConfig : Get the configuration of a specific region on this MPC. + int32_t (*EnableInterrupt) (void); ///< Pointer to \ref ARM_MPC_EnableInterrupt : Enable MPC interrupt. + void (*DisableInterrupt) (void); ///< Pointer to \ref ARM_MPC_DisableInterrupt : Disable MPC interrupt. + void (*ClearInterrupt) (void); ///< Pointer to \ref ARM_MPC_ClearInterrupt : Clear MPC interrupt. + uint32_t (*InterruptState) (void); ///< Pointer to \ref ARM_MPC_InterruptState : MPC interrupt State. + int32_t (*LockDown) (void); ///< Pointer to \ref ARM_MPC_LockDown : Lock down the MPC configuration. +} const ARM_DRIVER_MPC; + +#endif /* __DRIVER_MPC_H */ + diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_PPC.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_PPC.h new file mode 100644 index 00000000..e689b2eb --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_PPC.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_PPC_DRV_H__ +#define __CMSIS_PPC_DRV_H__ + +#include "Driver_Common.h" + +/* API version */ +#define ARM_PPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +/* Security attribute used to configure the peripheral */ +typedef enum _ARM_PPC_SecAttr { + ARM_PPC_SECURE_ONLY, ///< Secure access + ARM_PPC_NONSECURE_ONLY, ///< Non-secure access +} ARM_PPC_SecAttr; + +/* Privilege attribute used to configure the peripheral */ +typedef enum _ARM_PPC_PrivAttr { + ARM_PPC_PRIV_AND_NONPRIV, ///< Privilege and non-privilege access + ARM_PPC_PRIV_ONLY, ///< Privilege only access +} ARM_PPC_PrivAttr; + +/* Function documentation */ +/** + \fn ARM_DRIVER_VERSION ARM_PPC_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn int32_t ARM_PPC_Initialize (void) + \brief Initialize PPC Interface. + \return Returns ARM error code. + + \fn int32_t ARM_PPC_Uninitialize (void) + \brief De-initialize MPC Interface. + \return Returns ARM error code. + + \fn int32_t ARM_PPC_ConfigPeriph (uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) + \brief Configures a peripheral controlled by the given PPC. + \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers. + \param[in] sec_attr: Secure attribute value. + \param[in] priv_attr: Privilege attrivute value. + + Secure Privilege Control Block ( SPCTRL ) + Non-Secure Privilege Control Block ( NSPCTRL ) + + \return Returns ARM error code. + + \fn int32_t ARM_PPC_IsPeriphSecure (uint8_t periph) + \brief Check if the peripheral is configured to be secure. + \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers. + + Secure Privilege Control Block ( SPCTRL ) + Non-Secure Privilege Control Block ( NSPCTRL ) + + \return Returns 1 if the peripheral is configured as secure, + 0 for non-secure. + + \fn uint32_t ARM_PPC_IsPeriphPrivOnly (uint8_t periph) + \brief Check if the peripheral is configured to be privilege only. + \param[in] periph: Peripheral position in SPCTRL and NSPCTRL registers. + + Secure Privilege Control Block ( SPCTRL ) + Non-Secure Privilege Control Block ( NSPCTRL ) + + \return Returns 1 if the peripheral is configured as privilege access + only, 0 for privilege and unprivilege access mode. + + \fn int32_t ARM_PPC_EnableInterrupt (void) + \brief Enable PPC interrupt. + \return Returns ARM error code. + + \fn void ARM_PPC_DisableInterrupt (void) + \brief Disable PPC interrupt. + + \fn void ARM_PPC_ClearInterrupt (void) + \brief Clear PPC interrupt. + + \fn int32_t ARM_PPC_InterruptState (void) + \brief PPC interrupt state. + \return Returns 1 if the interrupt is active, 0 otherwise. +*/ + +/** + * \brief Access structure of the MPC Driver. + */ +typedef struct _ARM_DRIVER_PPC { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_PPC_GetVersion : Get driver version. + int32_t (*Initialize) (void); ///< Pointer to \ref ARM_PPC_Initialize : Initialize the PPC Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_PPC_Uninitialize : De-initialize the PPC Interface. + int32_t (*ConfigPeriph) (uint8_t periph, ARM_PPC_SecAttr sec_attr, ARM_PPC_PrivAttr priv_attr); ///< Pointer to \ref ARM_PPC_ConfigPeriph : Configure a peripheral controlled by the PPC. + uint32_t (*IsPeriphSecure) (uint8_t periph); ///< Pointer to \ref IsPeriphSecure : Check if the peripheral is configured to be secure. + uint32_t (*IsPeriphPrivOnly) (uint8_t periph); ///< Pointer to \ref IsPeriphPrivOnly : Check if the peripheral is configured to be privilege only. + int32_t (*EnableInterrupt) (void); ///< Pointer to \ref ARM_PPC_EnableInterrupt : Enable PPC interrupt. + void (*DisableInterrupt) (void); ///< Pointer to \ref ARM_PPC_DisableInterrupt : Disable PPC interrupt. + void (*ClearInterrupt) (void); ///< Pointer to \ref ARM_PPC_ClearInterrupt : Clear PPC interrupt. + uint32_t (*InterruptState) (void); ///< Pointer to \ref ARM_PPC_InterruptState : PPC interrupt State. +} const ARM_DRIVER_PPC; + +#endif /* __CMSIS_PPC_DRV_H__ */ + diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_USART.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_USART.h new file mode 100644 index 00000000..237496bc --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/Driver_USART.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile + * Version 2.2 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.1 + * Removed optional argument parameter from Signal Event + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_USART_H_ +#define DRIVER_USART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef volatile struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t reserved : 25; +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef volatile struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive + uint32_t reserved : 28; +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI + uint32_t reserved : 11; ///< Reserved (must be zero) +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_USART_H_ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_compiler.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_compiler.h new file mode 100644 index 00000000..adbf296f --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_gcc.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_gcc.h new file mode 100644 index 00000000..35890004 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; i<(pTable->wlen/sizeof(pTable->dest)); ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; i<(pTable->wlen/sizeof(pTable->dest)); ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE _vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_version.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_version.h new file mode 100644 index 00000000..f2e27466 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/core_cm33.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/core_cm33.h new file mode 100644 index 00000000..7fed59a8 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/mpu_armv8.h b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/mpu_armv8.h new file mode 100644 index 00000000..0041d4dc --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/CMSIS/include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/config/device_cfg.h b/Arm/MPS3_AN524/lib/AN524/src/device/config/device_cfg.h new file mode 100644 index 00000000..29e992e8 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/config/device_cfg.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the device configuration file with only used peripherals + * defined and configured via the secure and/or non-secure base address. + */ + +/* ARM Memory Protection Controller (MPC) */ +#define MPC_ISRAM0_S +#define MPC_ISRAM1_S +#define MPC_ISRAM2_S +#define MPC_ISRAM3_S +#define MPC_QSPI_S + +/* ARM Peripheral Protection Controllers (PPC) */ +#define AHB_PPCEXP0_S +#define APB_PPC0_S +#define APB_PPC1_S +#define APB_PPCEXP0_S +#define APB_PPCEXP1_S +#define APB_PPCEXP2_S + +/* ARM UART CMSDK */ +#define DEFAULT_UART_BAUDRATE 115200 +#define UART0_CMSDK_S +#define UART0_CMSDK_NS +#define UART1_CMSDK_S +#define UART1_CMSDK_NS + +/* CMSDK Timers */ +#define CMSDK_TIMER0_S +#define CMSDK_TIMER0_NS +#define CMSDK_TIMER1_S +#define CMSDK_TIMER1_NS + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/cmsis.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/cmsis.h new file mode 100644 index 00000000..44068a10 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/cmsis.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AN524_CMSIS_H__ +#define __AN524_CMSIS_H__ + +/* ================== Start of section using anonymous unions ============ */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*Setting shared by the two cores.*/ +#define __CM33_REV 0x02U /* Core revision r0p2 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for + * Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different + * SysTick Config is used */ + +#ifdef DUAL_CORE +/* Both cores are used */ +#if defined CORE0 +#define __FPU_PRESENT 0U /* no FPU present */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#elif defined CORE1 +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#else +#error "Either CORE0 or CORE1 must be defined for DUAL_CORE builds" +#endif /* CORE0/1 */ + +#else /* DUAL_CORE */ +/* Single core is used */ +#define __FPU_PRESENT 0U /* no FPU present */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#endif /* DUAL_CORE */ + +#include "system_core_init.h" +#include "platform_irq.h" +#include /*!< ARM Cortex-M33 processor and core peripherals */ + +/* ================== End of section using anonymous unions ============= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#endif /* __AN524_CMSIS_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/device_definition.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/device_definition.h new file mode 100644 index 00000000..a978ac99 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/device_definition.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file device_definition.h + * \brief The structure definitions in this file are exported based on the + * peripheral definitions from device_cfg.h. + * This file is meant to be used as a helper for baremetal + * applications and/or as an example of how to configure the generic + * driver structures. + */ + +#ifndef __DEVICE_DEFINITION_H__ +#define __DEVICE_DEFINITION_H__ + +#include "device_cfg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ======= Defines peripheral configuration structures ======= */ +/* UART CMSDK driver structures */ +#ifdef UART0_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART0_DEV_S; +#endif +#ifdef UART0_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART0_DEV_NS; +#endif + +#ifdef UART1_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART1_DEV_S; +#endif +#ifdef UART1_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART1_DEV_NS; +#endif + +#ifdef UART2_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART2_DEV_S; +#endif +#ifdef UART2_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART2_DEV_NS; +#endif + +#ifdef UART3_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART3_DEV_S; +#endif +#ifdef UART3_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART3_DEV_NS; +#endif + +#ifdef UART4_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART4_DEV_S; +#endif +#ifdef UART4_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART4_DEV_NS; +#endif + +#ifdef UART5_CMSDK_S +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART5_DEV_S; +#endif +#ifdef UART5_CMSDK_NS +#include "uart_cmsdk_drv.h" +extern struct uart_cmsdk_dev_t ARM_UART5_DEV_NS; +#endif + +/* ARM PPC driver structures */ +#ifdef AHB_PPC0_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S; +#endif + +#ifdef AHB_PPCEXP0_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S; +#endif + +#ifdef APB_PPC0_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t APB_PPC0_DEV_S; +#endif + +#ifdef APB_PPC1_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t APB_PPC1_DEV_S; +#endif + +#ifdef APB_PPCEXP0_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S; +#endif + +#ifdef APB_PPCEXP1_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S; +#endif + +#ifdef APB_PPCEXP2_S +#include "ppc_sse200_drv.h" +extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S; +#endif + +/* CMSDK Timer driver structures */ +#ifdef CMSDK_TIMER0_S +#include "timer_cmsdk_drv.h" +extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S; +#endif +#ifdef CMSDK_TIMER0_NS +#include "timer_cmsdk_drv.h" +extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS; +#endif + +#ifdef CMSDK_TIMER1_S +#include "timer_cmsdk_drv.h" +extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S; +#endif +#ifdef CMSDK_TIMER1_NS +#include "timer_cmsdk_drv.h" +extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS; +#endif + +/* ARM MPC SSE 200 driver structures */ +#ifdef MPC_ISRAM0_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S; +#endif + +#ifdef MPC_ISRAM1_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S; +#endif + +#ifdef MPC_ISRAM2_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S; +#endif + +#ifdef MPC_ISRAM3_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S; +#endif + +#ifdef MPC_BRAM_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_BRAM_DEV_S; +#endif + +#ifdef MPC_QSPI_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_QSPI_DEV_S; +#endif + +#ifdef MPC_DDR4_S +#include "mpc_sie200_drv.h" +extern struct mpc_sie200_dev_t MPC_DDR4_DEV_S; +#endif + +#ifdef MPS3_IO_S +#include "arm_mps3_io_drv.h" +extern struct arm_mps3_io_dev_t MPS3_IO_DEV_S; +#endif + +#ifdef MPS3_IO_NS +#include "arm_mps3_io_drv.h" +extern struct arm_mps3_io_dev_t MPS3_IO_DEV_NS; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DEVICE_DEFINITION_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_base_address.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_base_address.h new file mode 100644 index 00000000..52d4b36b --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_base_address.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2019-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file platform_base_address.h + * \brief This file defines all the peripheral base addresses for MPS3 SSE-200 + * AN524 platform. + */ + +#ifndef __PLATFORM_BASE_ADDRESS_H_ +#define __PLATFORM_BASE_ADDRESS_H_ + +/* ======= Defines peripherals memory map addresses ======= */ +/* Non-secure memory map addresses */ +#define CMSDK_TIMER0_BASE_NS 0x40000000 +#define CMSDK_TIMER1_BASE_NS 0x40001000 +#define CMSDK_DUALTIMER_BASE_NS 0x40002000 +#define CMSDK_SYSINFO_BASE_NS 0x40020000 +#define S32K_TIMER_BASE_NS 0x4002F000 +#define CMSDK_NSPCTRL_BASE_NS 0x40080000 +#define APB_WATCHDOG_BASE_NS 0x40081000 +#define GPIO0_BASE_NS 0x41100000 +#define GPIO1_BASE_NS 0x41101000 +#define GPIO2_BASE_NS 0x41102000 +#define GPIO3_BASE_NS 0x41103000 +#define I2C0_SBCON_BASE_NS 0x41200000 /* Touchscreen I2C Base Address */ +#define I2C1_SBCON_BASE_NS 0x41201000 /* Audio I2C Base Address */ +#define SSP0_BASE_NS 0x41202000 /* ADC SPI PL022 Base Address */ +#define SSP1_BASE_NS 0x41203000 /* Shield 0 SPI PL022 Base Address */ +#define SSP2_BASE_NS 0x41204000 /* Shield 1 SPI PL022 Base Address */ +#define I2C2_SBCON_BASE_NS 0x41205000 /* Shield 0 SBCon Base Address */ +#define I2C3_SBCON_BASE_NS 0x41206000 /* Shield 1 SBCon Base Address */ +#define I2C4_SBCON_BASE_NS 0x41208000 /* DDR4 EEPROM I2C Base Address */ +#define MPS3_IO_SCC_BASE_NS 0x41300000 +#define I2S_BASE_NS 0x41301000 /* Audio I2S Base Address */ +#define MPS3_IO_FPGAIO_BASE_NS 0x41302000 +#define UART0_BASE_NS 0x41303000 +#define UART1_BASE_NS 0x41304000 +#define UART2_BASE_NS 0x41305000 +#define UART3_BASE_NS 0x41306000 +#define UART4_BASE_NS 0x41307000 +#define UART5_BASE_NS 0x41308000 +#define CLCD_CONFIG_BASE_NS 0x4130A000 +#define RTC_BASE_NS 0x4130B000 +#define ETHERNET_BASE_NS 0x41400000 + +/* Secure memory map addresses */ +#define CMSDK_TIMER0_BASE_S 0x50000000 +#define CMSDK_TIMER1_BASE_S 0x50001000 +#define CMSDK_DUALTIMER_BASE_S 0x50002000 +#define CMSDK_SYSINFO_BASE_S 0x50020000 +#define CMSDK_SYSCTRL_BASE_S 0x50021000 +#define S32K_WATCHDOG_BASE_S 0x5002E000 +#define S32K_TIMER_BASE_S 0x5002F000 +#define CMSDK_SPCTRL_BASE_S 0x50080000 +#define APB_WATCHDOG_BASE_S 0x50081000 +#define GPIO0_BASE_S 0x51100000 +#define GPIO1_BASE_S 0x51101000 +#define GPIO2_BASE_S 0x51102000 +#define GPIO3_BASE_S 0x51103000 +#define I2C0_SBCON_BASE_S 0x51200000 +#define I2C1_SBCON_BASE_S 0x51201000 +#define SSP0_BASE_S 0x51202000 +#define SSP1_BASE_S 0x51203000 +#define SSP2_BASE_S 0x51204000 +#define I2C2_SBCON_BASE_S 0x51205000 +#define I2C3_SBCON_BASE_S 0x51206000 +#define I2C4_SBCON_BASE_S 0x51208000 +#define MPS3_IO_SCC_BASE_S 0x51300000 +#define I2S_BASE_S 0x51301000 +#define MPS3_IO_FPGAIO_BASE_S 0x51302000 +#define UART0_BASE_S 0x51303000 +#define UART1_BASE_S 0x51304000 +#define UART2_BASE_S 0x51305000 +#define UART3_BASE_S 0x51306000 +#define UART4_BASE_S 0x51307000 +#define UART5_BASE_S 0x51308000 +#define CLCD_CONFIG_BASE_S 0x5130A000 +#define RTC_BASE_S 0x5130B000 +#define ETHERNET_BASE_S 0x51400000 +#define MPC_ISRAM0_BASE_S 0x50083000 +#define MPC_ISRAM1_BASE_S 0x50084000 +#define MPC_ISRAM2_BASE_S 0x50085000 +#define MPC_ISRAM3_BASE_S 0x50086000 +#define MPC_BRAM_BASE_S 0x58007000 +#define MPC_QSPI_BASE_S 0x58008000 +#define MPC_DDR4_BASE_S 0x58009000 + +/* SRAM MPC ranges and limits */ +/* Internal memory */ +#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000 +#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF +#define MPC_ISRAM0_RANGE_BASE_S 0x30000000 +#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF + +#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000 +#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF +#define MPC_ISRAM1_RANGE_BASE_S 0x30008000 +#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF + +#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000 +#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF +#define MPC_ISRAM2_RANGE_BASE_S 0x30010000 +#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF + +#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000 +#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF +#define MPC_ISRAM3_RANGE_BASE_S 0x30018000 +#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF + +/* + * TF-M only supports booting up from QSPI flash. + * The following addresses for BRAM and QSPI are for QSPI boot. + */ +/* FPGA BRAM memory */ +#define MPC_BRAM_RANGE_BASE_NS 0x28000000 +#define MPC_BRAM_RANGE_LIMIT_NS 0x2807FFFF +#define MPC_BRAM_RANGE_BASE_S 0x38000000 +#define MPC_BRAM_RANGE_LIMIT_S 0x3807FFFF + +/* QSPI flash memory */ +#define MPC_QSPI_RANGE_BASE_NS 0x00000000 +#define MPC_QSPI_RANGE_LIMIT_NS 0x007FFFFF +#define MPC_QSPI_RANGE_BASE_S 0x10000000 +#define MPC_QSPI_RANGE_LIMIT_S 0x107FFFFF + +/* DDR4 memory */ +#define MPC_DDR4_RANGE0_BASE_NS 0x60000000 +#define MPC_DDR4_RANGE0_LIMIT_NS 0x6FFFFFFF +#define MPC_DDR4_RANGE0_BASE_S 0x70000000 +#define MPC_DDR4_RANGE0_LIMIT_S 0x7FFFFFFF + +#endif /* __PLATFORM_BASE_ADDRESS_H_ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_description.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_description.h new file mode 100644 index 00000000..85fc4405 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_description.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_AN524_DESCRIPTION_H__ +#define __ARM_LTD_AN524_DESCRIPTION_H__ + +#include "platform_base_address.h" +#include "platform_pins.h" +#include "platform_regs.h" +#include "cmsis.h" + +#endif /* __ARM_LTD_AN524_DESCRIPTION_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_irq.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_irq.h new file mode 100644 index 00000000..c84684c8 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_irq.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_AN524_IRQ_H__ +#define __ARM_LTD_AN524_IRQ_H__ + +typedef enum _IRQn_Type { + NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */ + HardFault_IRQn = -13, /* HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* Memory Management Interrupt */ + BusFault_IRQn = -11, /* Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* Usage Fault Interrupt */ + SecureFault_IRQn = -9, /* Secure Fault Interrupt */ + SVCall_IRQn = -5, /* SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* Pend SV Interrupt */ + SysTick_IRQn = -1, /* System Tick Interrupt */ + NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset + * Interrupt + */ + NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ + S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */ + TIMER0_IRQn = 3, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 4, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */ + MHU0_IRQn = 6, /* Message Handling Unit 0 */ + MHU1_IRQn = 7, /* Message Handling Unit 1 */ + MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */ + PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */ + MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */ + BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined + * (Secure) Interrupt + */ + INVALID_INSTR_CACHE_IRQn = 13, /* CPU Instruction Cache Invalidation + * Interrupt + */ + SYS_PPU_IRQn = 15, /* SYS PPU */ + CPU0_PPU_IRQn = 16, /* CPU0 PPU */ + CPU1_PPU_IRQn = 17, /* CPU1 PPU */ + CPU0_DBG_PPU_IRQn = 18, /* CPU0 DBG PPU */ + CPU1_DBG_PPU_IRQn = 19, /* CPU1 DBG PPU */ + /* Reserved = 20, Reserved */ + RAM0_PPU_IRQn = 22, /* RAM0 PPU */ + RAM1_PPU_IRQn = 23, /* RAM1 PPU */ + RAM2_PPU_IRQn = 24, /* RAM2 PPU */ + RAM3_PPU_IRQn = 25, /* RAM3 PPU */ + DEBUG_PPU_IRQn = 26, /* DEBUG PPU */ + CPUx_CTI_IRQ0 = 28, /* CPUx CTI 0 */ + CPUx_CTI_IRQ1 = 29, /* CPUx CTI 1 */ + /* Reserved = 30, Reserved */ + /* Reserved = 31, Reserved */ + UARTRX0_IRQn = 32, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 33, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 34, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 35, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 36, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 37, /* UART 2 TX Interrupt */ + UARTRX3_IRQn = 38, /* UART 3 RX Interrupt */ + UARTTX3_IRQn = 39, /* UART 3 TX Interrupt */ + UARTRX4_IRQn = 40, /* UART 4 RX Interrupt */ + UARTTX4_IRQn = 41, /* UART 4 TX Interrupt */ + UART0_IRQn = 42, /* UART 0 combined Interrupt */ + UART1_IRQn = 43, /* UART 1 combined Interrupt */ + UART2_IRQn = 44, /* UART 2 combined Interrupt */ + UART3_IRQn = 45, /* UART 3 combined Interrupt */ + UART4_IRQn = 46, /* UART 4 combined Interrupt */ + UARTOVF_IRQn = 47, /* UART 012345 Overflow Interrupt */ + ETHERNET_IRQn = 48, /* Ethernet Interrupt */ + I2S_IRQn = 49, /* I2S Interrupt */ + TSC_IRQn = 50, /* Touch Screen Interrupt */ + SPI0_IRQn = 52, /* SPI 0 Interrupt */ + SPI1_IRQn = 53, /* SPI 1 Interrupt */ + SPI2_IRQn = 54, /* SPI 2 Interrupt */ + GPIO0_IRQn = 68, /* GPIO 0 Combined Interrupt */ + GPIO1_IRQn = 69, /* GPIO 1 Combined Interrupt */ + GPIO2_IRQn = 70, /* GPIO 2 Combined Interrupt */ + GPIO3_IRQn = 71, /* GPIO 3 Combined Interrupt */ + GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */ + GPIO0_1_IRQn = 73, + GPIO0_2_IRQn = 74, + GPIO0_3_IRQn = 75, + GPIO0_4_IRQn = 76, + GPIO0_5_IRQn = 77, + GPIO0_6_IRQn = 78, + GPIO0_7_IRQn = 79, + GPIO0_8_IRQn = 80, + GPIO0_9_IRQn = 81, + GPIO0_10_IRQn = 82, + GPIO0_11_IRQn = 83, + GPIO0_12_IRQn = 84, + GPIO0_13_IRQn = 85, + GPIO0_14_IRQn = 86, + GPIO0_15_IRQn = 87, + GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */ + GPIO1_1_IRQn = 89, + GPIO1_2_IRQn = 90, + GPIO1_3_IRQn = 91, + GPIO1_4_IRQn = 92, + GPIO1_5_IRQn = 93, + GPIO1_6_IRQn = 94, + GPIO1_7_IRQn = 95, + GPIO1_8_IRQn = 96, + GPIO1_9_IRQn = 97, + GPIO1_10_IRQn = 98, + GPIO1_11_IRQn = 99, + GPIO1_12_IRQn = 100, + GPIO1_13_IRQn = 101, + GPIO1_14_IRQn = 102, + GPIO1_15_IRQn = 103, + GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */ + GPIO2_1_IRQn = 105, + GPIO2_2_IRQn = 106, + GPIO2_3_IRQn = 107, + GPIO2_4_IRQn = 108, + GPIO2_5_IRQn = 109, + GPIO2_6_IRQn = 110, + GPIO2_7_IRQn = 111, + GPIO2_8_IRQn = 112, + GPIO2_9_IRQn = 113, + GPIO2_10_IRQn = 114, + GPIO2_11_IRQn = 115, + GPIO2_12_IRQn = 116, + GPIO2_13_IRQn = 117, + GPIO2_14_IRQn = 118, + GPIO2_15_IRQn = 119, + GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */ + GPIO3_1_IRQn = 121, + GPIO3_2_IRQn = 122, + GPIO3_3_IRQn = 123, + UARTRX5_IRQn = 124, /* UART 5 RX Interrupt */ + UARTTX5_IRQn = 125, /* UART 5 TX Interrupt */ + UART5_IRQn = 126, /* UART 5 combined Interrupt */ + HDCLCD_IRQn = 127, /* HDCLCD Interrupt */ +} IRQn_Type; + +#endif /* __ARM_LTD_AN524_IRQ_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_pins.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_pins.h new file mode 100644 index 00000000..e5fcfcca --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_pins.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file platform_pins.h + * \brief This file defines all the pins for this platform. + */ + +#ifndef __ARM_LTD_AN524_PINS_H__ +#define __ARM_LTD_AN524_PINS_H__ + +/* AHB GPIO pin names */ +enum arm_gpio_pin_name_t { + AHB_GPIO0_0 = 0U, + AHB_GPIO0_1, + AHB_GPIO0_2, + AHB_GPIO0_3, + AHB_GPIO0_4, + AHB_GPIO0_5, + AHB_GPIO0_6, + AHB_GPIO0_7, + AHB_GPIO0_8, + AHB_GPIO0_9, + AHB_GPIO0_10, + AHB_GPIO0_11, + AHB_GPIO0_12, + AHB_GPIO0_13, + AHB_GPIO0_14, + AHB_GPIO0_15, + AHB_GPIO1_0 = 0U, + AHB_GPIO1_1, + AHB_GPIO1_2, + AHB_GPIO1_3, + AHB_GPIO1_4, + AHB_GPIO1_5, + AHB_GPIO1_6, + AHB_GPIO1_7, + AHB_GPIO1_8, + AHB_GPIO1_9, + AHB_GPIO1_10, + AHB_GPIO1_11, + AHB_GPIO1_12, + AHB_GPIO1_13, + AHB_GPIO1_14, + AHB_GPIO1_15, + AHB_GPIO2_0 = 0U, + AHB_GPIO2_1, + AHB_GPIO2_2, + AHB_GPIO2_3, + AHB_GPIO2_4, + AHB_GPIO2_5, + AHB_GPIO2_6, + AHB_GPIO2_7, + AHB_GPIO2_8, + AHB_GPIO2_9, + AHB_GPIO2_10, + AHB_GPIO2_11, + AHB_GPIO2_12, + AHB_GPIO2_13, + AHB_GPIO2_14, + AHB_GPIO2_15, + AHB_GPIO3_0 = 0U, + AHB_GPIO3_1, + AHB_GPIO3_2, + AHB_GPIO3_3, + AHB_GPIO3_4, + AHB_GPIO3_5, + AHB_GPIO3_6, + AHB_GPIO3_7, + AHB_GPIO3_8, + AHB_GPIO3_9, + AHB_GPIO3_10, + AHB_GPIO3_11, + AHB_GPIO3_12, + AHB_GPIO3_13, + AHB_GPIO3_14, + AHB_GPIO3_15, +}; + +/* + * Pin definitions for the MPS3 Arduino adapter shields. + * Reference: Application Note AN524 + */ + +/* GPIO shield 0 definition */ +#define SH0_UART_RX AHB_GPIO0_0 +#define SH0_UART_TX AHB_GPIO0_1 +#define SH0_SPI_SS AHB_GPIO0_10 +#define SH0_SPI_MOSI AHB_GPIO0_11 +#define SH0_SPI_MISO AHB_GPIO0_12 +#define SH0_SPI_SCK AHB_GPIO0_13 +#define SH0_I2C_SDA AHB_GPIO0_14 +#define SH0_I2C_SCL AHB_GPIO0_15 + +/* GPIO shield 1 definition */ +#define SH1_UART_RX AHB_GPIO1_0 +#define SH1_UART_TX AHB_GPIO1_1 + +#define SH1_SPI_SS AHB_GPIO1_10 +#define SH1_SPI_MOSI AHB_GPIO1_11 +#define SH1_SPI_MISO AHB_GPIO1_12 +#define SH1_SPI_SCK AHB_GPIO1_13 +#define SH1_I2C_SDA AHB_GPIO1_14 +#define SH1_I2C_SCL AHB_GPIO1_15 + +#endif /* __ARM_LTD_AN524_PINS_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_regs.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_regs.h new file mode 100644 index 00000000..1e5e92fa --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/platform_regs.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_AN524_REGS_H__ +#define __ARM_LTD_AN524_REGS_H__ + +#include + +/* System info memory mapped register access structure */ +struct sysinfo_t { + volatile uint32_t sys_version; /* (R/ ) System version */ + volatile uint32_t sys_config; /* (R/ ) System configuration */ + volatile uint32_t reserved0[1008]; + volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ + volatile uint32_t reserved1[3]; + volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ + volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ + volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ + volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ + volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ + volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ + volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ + volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ +}; + +/* System control memory mapped register access structure */ +struct sysctrl_t { + volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration + * Status Register + */ + volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration + * Set Register + */ + volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration + * Clear Register + */ + volatile uint32_t scsecctrl; /* (R/W) System Control Security + * Control Register + */ + volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider + * Configuration Register + */ + volatile uint32_t sysclk_div; /* (R/W) System Clock Divider + * Configuration Register + */ + volatile uint32_t clockforce; /* (R/W) Clock Forces */ + volatile uint32_t reserved0[57]; + volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */ + volatile uint32_t resetmask; /* (R/W) Reset MASK */ + volatile uint32_t swreset; /* ( /W) Software Reset */ + volatile uint32_t gretreg; /* (R/W) General Purpose Retention + * Register + */ + volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector + * Register For CPU 0 + */ + volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset + * Vector Register For CPU 1 + */ + volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control + * after reset + */ + volatile uint32_t nmi_enable; /* (R/W) NMI Enable Register */ + volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and + * Acknowledgment + */ + volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */ + volatile uint32_t reserved1[54]; + volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency + * Matrix PD_SYS + * Power Domain Sensitivity. + */ + volatile uint32_t reserved2[2]; /* Reserved */ + volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency + * Matrix PD_SRAM0 Power + * Domain Sensitivity. + */ + volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency + * Matrix PD_SRAM1 Power + * Domain Sensitivity. + */ + volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency + * Matrix PD_SRAM2 Power + * Domain Sensitivity. + */ + volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency + * Matrix PD_SRAM3 Power + * Domain Sensitivity. + */ + volatile uint32_t reserved3[877]; /* Reserved */ + volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ + volatile uint32_t reserved4[3]; + volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ + volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ + volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ + volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ + volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ + volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ + volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ + volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ +}; + +/* Secure Privilege Control */ +#define CMSDK_SPCTRL ((struct spctrl_def *)CMSDK_SPCTRL_BASE_S) + +/* SPCTRL memory mapped register access structure */ +struct spctrl_def { + volatile uint32_t spcsecctrl; + volatile uint32_t buswait; + volatile uint32_t reserved[2]; + volatile uint32_t secrespcfg; + volatile uint32_t nsccfg; + volatile uint32_t reserved2; + volatile uint32_t secmpcintstat; + volatile uint32_t secppcintstat; + volatile uint32_t secppcintclr; + volatile uint32_t secppcinten; + volatile uint32_t reserved3; + volatile uint32_t secmscintstat; + volatile uint32_t secmscintclr; + volatile uint32_t secmscinten; + volatile uint32_t reserved4; + volatile uint32_t brgintstat; + volatile uint32_t brgintclr; + volatile uint32_t brginten; + volatile uint32_t reserved5; + volatile uint32_t ahbnsppc0; + volatile uint32_t reserved6[3]; + volatile uint32_t ahbnsppcexp0; + volatile uint32_t ahbnsppcexp1; + volatile uint32_t ahbnsppcexp2; + volatile uint32_t ahbnsppcexp3; + volatile uint32_t apbnsppc0; + volatile uint32_t apbnsppc1; + volatile uint32_t reserved7[2]; + volatile uint32_t apbnsppcexp0; + volatile uint32_t apbnsppcexp1; + volatile uint32_t apbnsppcexp2; + volatile uint32_t apbnsppcexp3; + volatile uint32_t ahbspppc0; + volatile uint32_t reserved8[3]; + volatile uint32_t ahbspppcexp0; + volatile uint32_t ahbspppcexp1; + volatile uint32_t ahbspppcexp2; + volatile uint32_t ahbspppcexp3; + volatile uint32_t apbspppc0; + volatile uint32_t apbspppc1; + volatile uint32_t reserved9[2]; + volatile uint32_t apbspppcexp0; + volatile uint32_t apbspppcexp1; + volatile uint32_t apbspppcexp2; + volatile uint32_t apbspppcexp3; + volatile uint32_t nsmscexp; + volatile uint32_t reserved10[959]; + volatile uint32_t pid4; + volatile uint32_t pid5; + volatile uint32_t pid6; + volatile uint32_t pid7; + volatile uint32_t pid0; + volatile uint32_t pid1; + volatile uint32_t pid2; + volatile uint32_t pid3; + volatile uint32_t cid0; + volatile uint32_t cid1; + volatile uint32_t cid2; + volatile uint32_t cid3; +}; + +/* Throw out bus error when an access causes security violation */ +#define CMSDK_SECRESPCFG_BUS_ERR_MASK (1UL << 0) + +/* PPC interrupt position mask */ +#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0) +#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1) +#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4) +#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5) +#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6) +#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7) +#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20) +#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21) +#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22) +#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23) + +/* Non-Secure Privilege Control */ +#define CMSDK_NSPCTRL ((struct nspctrl_def *)CMSDK_NSPCTRL_BASE_NS) + +/* NSPCTRL memory mapped register access structure */ +struct nspctrl_def { + volatile uint32_t reserved[36]; + volatile uint32_t ahbnspppc0; + volatile uint32_t reserved3[3]; + volatile uint32_t ahbnspppcexp0; + volatile uint32_t ahbnspppcexp1; + volatile uint32_t ahbnspppcexp2; + volatile uint32_t ahbnspppcexp3; + volatile uint32_t apbnspppc0; + volatile uint32_t apbnspppc1; + volatile uint32_t reserved4[2]; + volatile uint32_t apbnspppcexp0; + volatile uint32_t apbnspppcexp1; + volatile uint32_t apbnspppcexp2; + volatile uint32_t apbnspppcexp3; + volatile uint32_t reserved5[960]; + volatile uint32_t pidr4; + volatile uint32_t reserved7; /* pidr5 */ + volatile uint32_t reserved8; /* pidr6 */ + volatile uint32_t reserved9; /* pidr7 */ + volatile uint32_t pidr0; + volatile uint32_t pidr1; + volatile uint32_t pidr2; + volatile uint32_t pidr3; + volatile uint32_t cidr0; + volatile uint32_t cidr1; + volatile uint32_t cidr2; + volatile uint32_t cidr3; +}; + +/* ARM APB PPC0 peripherals definition */ +#define CMSDK_TIMER0_APB_PPC_POS 0U +#define CMSDK_TIMER1_APB_PPC_POS 1U +#define CMSDK_DTIMER_APB_PPC_POS 2U +#define CMSDK_MHU0_APB_PPC_POS 3U +#define CMSDK_MHU1_APB_PPC_POS 4U +/* The bits 31:5 are reserved */ +/* End ARM APB PPC0 peripherals definition */ + +/* ARM APB PPC1 peripherals definition */ +#define CMSDK_S32K_TIMER_PPC_POS 0U +/* The bits 31:1 are reserved */ +/* End ARM APB PPC1 peripherals definition */ + +/* ARM APB PPCEXP0 peripherals definition */ +#define CMSDK_BRAM_MPC_APB_PPC_POS 0U +#define CMSDK_QSPI_MPC_APB_PPC_POS 1U +#define CMSDK_DDR4_MPC_APB_PPC_POS 2U +/* The bits 31:3 are reserved */ +/* End ARM APB PPCEXP0 peripherals definition */ + +/* ARM APB PPCEXP1 peripherals definition */ +#define CMSDK_I2C0_APB_PPC_POS 0U +#define CMSDK_I2C1_APB_PPC_POS 1U +#define CMSDK_SPI0_APB_PPC_POS 2U +#define CMSDK_SPI1_APB_PPC_POS 3U +#define CMSDK_SPI2_APB_PPC_POS 4U +#define CMSDK_I2C2_APB_PPC_POS 5U +#define CMSDK_I2C3_APB_PPC_POS 6U +#define CMSDK_I2C4_APB_PPC_POS 8U +/* The bits 7 and 31:9 are reserved */ +/* End ARM APB PPCEXP1 peripherals definition */ + +/* ARM APB PPCEXP2 peripherals definition */ +#define CMSDK_FPGA_SCC_PPC_POS 0U +#define CMSDK_FPGA_AUDIO_PPC_POS 1U +#define CMSDK_FPGA_IO_PPC_POS 2U +#define CMSDK_UART0_APB_PPC_POS 3U +#define CMSDK_UART1_APB_PPC_POS 4U +#define CMSDK_UART2_APB_PPC_POS 5U +#define CMSDK_UART3_APB_PPC_POS 6U +#define CMSDK_UART4_APB_PPC_POS 7U +#define CMSDK_UART5_APB_PPC_POS 8U +#define CMSDK_CLCD_APB_PPC_POS 10U +#define CMSDK_RTC_APB_PPC_POS 11U +/* The bits 9 and 31:12 are reserved */ +/* End ARM APB PPCEXP2 peripherals definition */ + +/* ARM APB PPCEXP3 peripherals definition */ +/* The bits 31:0 are reserved */ +/* End ARM APB PPCEXP3 peripherals definition */ + +/* ARM AHB PPC0 peripherals definition */ +/* The bits 31:0 are reserved */ +/* End of ARM AHB PPC0 peripherals definition */ + +/* ARM AHB PPCEXP0 peripherals definition */ +#define CMSDK_GPIO0_PPC_POS 0U +#define CMSDK_GPIO1_PPC_POS 1U +#define CMSDK_GPIO2_PPC_POS 2U +#define CMSDK_GPIO3_PPC_POS 3U +#define CMSDK_USB_ETHERNET_PPC_POS 4U +#define CMSDK_USER0_PPC_POS 5U +#define CMSDK_USER1_PPC_POS 6U +#define CMSDK_USER2_PPC_POS 7U +/* The bits 31:8 are reserved */ +/* End of ARM AHB PPCEXP0 peripherals definition */ + +/* ARM AHB PPCEXP1 peripherals definition */ +/* The bits 31:0 are reserved */ +/* End of ARM AHB PPCEXP1 peripherals definition */ + +/* ARM AHB PPCEXP2 peripherals definition */ +/* The bits 31:0 are reserved */ +/* End of ARM AHB PPCEXP2 peripherals definition */ + +/* ARM AHB PPCEXP3 peripherals definition */ +/* The bits 31:0 are reserved */ +/* End of ARM AHB PPCEXP3 peripherals definition */ + +#endif /* __ARM_LTD_AN524_REGS_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/include/system_core_init.h b/Arm/MPS3_AN524/lib/AN524/src/device/include/system_core_init.h new file mode 100644 index 00000000..ab59ce55 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/include/system_core_init.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_CORE_INIT_H__ +#define __SYSTEM_CORE_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ + +/** + * \brief Initializes the system + */ +extern void SystemInit(void); + +/** + * \brief Restores system core clock + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/source/device_definition.c b/Arm/MPS3_AN524/lib/AN524/src/device/source/device_definition.c new file mode 100644 index 00000000..ac1e0b41 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/source/device_definition.c @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2019-2021 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file device_definition.c + * \brief This file defines exports the structures based on the peripheral + * definitions from device_cfg.h. + * This file is meant to be used as a helper for baremetal + * applications and/or as an example of how to configure the generic + * driver structures. + */ + +#include "device_definition.h" +#include "platform_base_address.h" +// #include "tfm_plat_defs.h" + +/* UART CMSDK driver structures */ +#ifdef UART0_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = { + .base = UART0_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART0_DEV_S = { + &(UART0_CMSDK_DEV_CFG_S), + &(UART0_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART0_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = { + .base = UART0_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART0_DEV_NS = { + &(UART0_CMSDK_DEV_CFG_NS), + &(UART0_CMSDK_DEV_DATA_NS) +}; +#endif + +#ifdef UART1_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_S = { + .base = UART1_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART1_DEV_S = { + &(UART1_CMSDK_DEV_CFG_S), + &(UART1_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART1_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_NS = { + .base = UART1_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART1_DEV_NS = { + &(UART1_CMSDK_DEV_CFG_NS), + &(UART1_CMSDK_DEV_DATA_NS) +}; +#endif + +#ifdef UART2_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_S = { + .base = UART2_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART2_DEV_S = { + &(UART2_CMSDK_DEV_CFG_S), + &(UART2_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART2_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_NS = { + .base = UART2_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART2_DEV_NS = { + &(UART2_CMSDK_DEV_CFG_NS), + &(UART2_CMSDK_DEV_DATA_NS) +}; +#endif + +#ifdef UART3_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_S = { + .base = UART3_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART3_DEV_S = { + &(UART3_CMSDK_DEV_CFG_S), + &(UART3_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART3_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_NS = { + .base = UART3_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART3_DEV_NS = { + &(UART3_CMSDK_DEV_CFG_NS), + &(UART3_CMSDK_DEV_DATA_NS) +}; +#endif + +#ifdef UART4_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_S = { + .base = UART4_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART4_DEV_S = { + &(UART4_CMSDK_DEV_CFG_S), + &(UART4_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART4_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_NS = { + .base = UART4_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART4_DEV_NS = { + &(UART4_CMSDK_DEV_CFG_NS), + &(UART4_CMSDK_DEV_DATA_NS) +}; +#endif + +#ifdef UART5_CMSDK_S +static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_S = { + .base = UART5_BASE_S, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_S = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART5_DEV_S = { + &(UART5_CMSDK_DEV_CFG_S), + &(UART5_CMSDK_DEV_DATA_S) +}; +#endif +#ifdef UART5_CMSDK_NS +static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_NS = { + .base = UART5_BASE_NS, + .default_baudrate = DEFAULT_UART_BAUDRATE +}; +static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_NS = { + .state = 0, + .system_clk = 0, + .baudrate = 0 +}; +struct uart_cmsdk_dev_t ARM_UART5_DEV_NS = { + &(UART5_CMSDK_DEV_CFG_NS), + &(UART5_CMSDK_DEV_DATA_NS) +}; +#endif + +/* ARM PPC SIE 200 driver structures */ +#ifdef AHB_PPC0_S +static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t AHB_PPC0_DEV_S = { + &AHB_PPC0_DEV_CFG_S, + &AHB_PPC0_DEV_DATA_S +}; +#endif + +#ifdef AHB_PPCEXP0_S +static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = { + &AHB_PPCEXP0_DEV_CFG_S, + &AHB_PPCEXP0_DEV_DATA_S +}; +#endif + +#ifdef APB_PPC0_S +static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t APB_PPC0_DEV_S = { + &APB_PPC0_DEV_CFG_S, + &APB_PPC0_DEV_DATA_S +}; +#endif + +#ifdef APB_PPC1_S +static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t APB_PPC1_DEV_S = { + &APB_PPC1_DEV_CFG_S, + &APB_PPC1_DEV_DATA_S +}; +#endif + +#ifdef APB_PPCEXP0_S +static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = { + &APB_PPCEXP0_DEV_CFG_S, + &APB_PPCEXP0_DEV_DATA_S +}; +#endif + +#ifdef APB_PPCEXP1_S +static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = { + &APB_PPCEXP1_DEV_CFG, + &APB_PPCEXP1_DEV_DATA_S +}; +#endif + +#ifdef APB_PPCEXP2_S +static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = { + .spctrl_base = CMSDK_SPCTRL_BASE_S, + .nspctrl_base = CMSDK_NSPCTRL_BASE_NS +}; +static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = { + .p_ns_ppc = 0, + .p_sp_ppc = 0, + .p_nsp_ppc = 0, + .int_bit_mask = 0, + .state = 0 +}; +struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = { + &APB_PPCEXP2_DEV_CFG, + &APB_PPCEXP2_DEV_DATA_S +}; +#endif + +/* CMSDK Timer driver structures */ +#ifdef CMSDK_TIMER0_S +static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = { + // TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") = { + .base = CMSDK_TIMER0_BASE_S + }; +static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = { + // TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") = { + .is_initialized = 0 + }; +struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = { + // TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") = { + &(CMSDK_TIMER0_DEV_CFG_S), + &(CMSDK_TIMER0_DEV_DATA_S) + }; +#endif +#ifdef CMSDK_TIMER0_NS +static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = { + .base = CMSDK_TIMER0_BASE_NS +}; +static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = { + .is_initialized = 0 +}; +struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = { + &(CMSDK_TIMER0_DEV_CFG_NS), + &(CMSDK_TIMER0_DEV_DATA_NS) +}; +#endif + +#ifdef CMSDK_TIMER1_S +static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = { + .base = CMSDK_TIMER1_BASE_S +}; +static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = { + .is_initialized = 0 +}; +struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = { + &(CMSDK_TIMER1_DEV_CFG_S), + &(CMSDK_TIMER1_DEV_DATA_S) +}; +#endif +#ifdef CMSDK_TIMER1_NS +static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = { + .base = CMSDK_TIMER1_BASE_NS +}; +static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = { + .is_initialized = 0 +}; +struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = { + &(CMSDK_TIMER1_DEV_CFG_NS), + &(CMSDK_TIMER1_DEV_DATA_NS) +}; +#endif + +/* ARM MPC SSE 200 driver structures */ +#ifdef MPC_ISRAM0_S +static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { + .base = MPC_ISRAM0_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = { + &(MPC_ISRAM0_DEV_CFG_S), + &(MPC_ISRAM0_DEV_DATA_S) +}; +#endif + +#ifdef MPC_ISRAM1_S +static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { + .base = MPC_ISRAM1_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = { + &(MPC_ISRAM1_DEV_CFG_S), + &(MPC_ISRAM1_DEV_DATA_S) +}; +#endif + +#ifdef MPC_ISRAM2_S +static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = { + .base = MPC_ISRAM2_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = { + &(MPC_ISRAM2_DEV_CFG_S), + &(MPC_ISRAM2_DEV_DATA_S) +}; +#endif + +#ifdef MPC_ISRAM3_S +static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = { + .base = MPC_ISRAM3_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = { + &(MPC_ISRAM3_DEV_CFG_S), + &(MPC_ISRAM3_DEV_DATA_S) +}; +#endif + +#ifdef MPC_BRAM_S +static const struct mpc_sie200_dev_cfg_t MPC_BRAM_DEV_CFG_S = { + .base = MPC_BRAM_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_BRAM_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_BRAM_DEV_S = { + &(MPC_BRAM_DEV_CFG_S), + &(MPC_BRAM_DEV_DATA_S) +}; +#endif + +#ifdef MPC_QSPI_S +static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_S = { + .base = MPC_QSPI_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_QSPI_DEV_S = { + &(MPC_QSPI_DEV_CFG_S), + &(MPC_QSPI_DEV_DATA_S) +}; +#endif + +#ifdef MPC_DDR4_S +static const struct mpc_sie200_dev_cfg_t MPC_DDR4_DEV_CFG_S = { + .base = MPC_DDR4_BASE_S +}; +static struct mpc_sie200_dev_data_t MPC_DDR4_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0 +}; +struct mpc_sie200_dev_t MPC_DDR4_DEV_S = { + &(MPC_DDR4_DEV_CFG_S), + &(MPC_DDR4_DEV_DATA_S) +}; +#endif + +#ifdef MPS3_IO_S +static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_S = { + .base = MPS3_IO_FPGAIO_BASE_S +}; +struct arm_mps3_io_dev_t MPS3_IO_DEV_S = { + .cfg = &(MPS3_IO_DEV_CFG_S) +}; +#endif + +#ifdef MPS3_IO_NS +static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_NS = { + .base = MPS3_IO_FPGAIO_BASE_NS +}; +struct arm_mps3_io_dev_t MPS3_IO_DEV_NS = { + .cfg = &(MPS3_IO_DEV_CFG_NS) +}; +#endif diff --git a/Arm/MPS3_AN524/lib/AN524/src/device/source/system_core_init.c b/Arm/MPS3_AN524/lib/AN524/src/device/source/system_core_init.c new file mode 100644 index 00000000..11f73eee --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/device/source/system_core_init.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "system_core_init.h" +#include "platform_description.h" + + /* Define clocks */ +#define XTAL (32000000UL) +#define PERIPHERAL_XTAL (32000000UL) +#define SYSTEM_CLOCK (XTAL) +#define PERIPHERAL_CLOCK (PERIPHERAL_XTAL) + +/* System Core Clock Variable */ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/* System Core Clock update function */ +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/* System initialization function */ +void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t _vectors; + SCB->VTOR = (uint32_t) &_vectors; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.c b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.c new file mode 100644 index 00000000..b6dd8e99 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.c @@ -0,0 +1,655 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mpc_sie200_drv.h" + +#include + +#include "cmsis_compiler.h" + +#define MPC_SIE200_BLK_CFG_OFFSET 5U + +#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a + * bus error + */ +#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */ +#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */ + +/* ARM MPC interrupt */ +#define MPC_SIE200_INT_EN 1UL +#define MPC_SIE200_INT_STAT 1UL + +/* ARM MPC state definitions */ +#define MPC_SIE200_INITIALIZED (1 << 0) + +/* Error code returned by the internal driver functions */ +enum mpc_sie200_intern_error_t { + MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE, + MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE, + MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED, + MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE, + MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE = + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, + /* Calculated block index + * is higher than the maximum allowed by the MPC. It should never + * happen unless the controlled ranges of the MPC are misconfigured + * in the driver or if the IP has not enough LUTs to cover the + * range, due to wrong reported block size for example. + */ + MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1, + +}; + +/* ARM MPC memory mapped register access structure */ +struct mpc_sie200_reg_map_t { + volatile uint32_t ctrl; /* (R/W) MPC Control */ + volatile uint32_t reserved[3];/* Reserved */ + volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */ + volatile uint32_t blk_cfg; /* (R/ ) Block configuration */ + volatile uint32_t blk_idx; /* (R/W) Index value for accessing block + * based look up table + */ + volatile uint32_t blk_lutn; /* (R/W) Block based gating + * Look Up Table (LUT) + */ + volatile uint32_t int_stat; /* (R/ ) Interrupt state */ + volatile uint32_t int_clear; /* ( /W) Interrupt clear */ + volatile uint32_t int_en; /* (R/W) Interrupt enable */ + volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */ + volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */ + volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */ + volatile uint32_t reserved2[997]; /* Reserved */ + volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ + volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */ + volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */ + volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */ + volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ + volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ + volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ + volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ + volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ + volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ + volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ + volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ +}; + +/* + * Checks if the address is controlled by the MPC and returns + * the range index in which it is contained. + * + * \param[in] dev MPC device to initialize \ref mpc_sie200_dev_t + * \param[in] addr Address to check if it is controlled by MPC. + * \param[out] addr_range Range index in which it is contained. + * + * \return True if the base is controller by the range list, false otherwise. + */ +static uint32_t is_ctrl_by_range_list( + struct mpc_sie200_dev_t* dev, + uint32_t addr, + const struct mpc_sie200_memory_range_t** addr_range) +{ + uint32_t i; + const struct mpc_sie200_memory_range_t* range; + + for(i = 0; i < dev->data->nbr_of_ranges; i++) { + range = dev->data->range_list[i]; + if(addr >= range->base && addr <= range->limit) { + *addr_range = range; + return 1; + } + } + return 0; +} + +/* + * Gets the masks selecting the bits in the LUT of the MPC corresponding + * to the base address (included) up to the limit address (included) + * + * \param[in] mpc_dev The MPC device. + * \param[in] base Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[in] limit Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[out] range Memory range in which the base address and + * limit are. + * \param[out] first_word_idx Index of the first touched word in the LUT. + * \param[out] nr_words Number of words used in the LUT. If 1, only + * first_word_mask is valid and limit_word_mask + * must not be used. + * \param[out] first_word_mask First word mask in the LUT will be stored here. + * \param[out] limit_word_mask Limit word mask in the LUT will be stored here. + * + * \return Returns error code as specified in \ref mpc_sie200_intern_error_t + */ +static enum mpc_sie200_intern_error_t get_lut_masks( + struct mpc_sie200_dev_t* dev, + const uint32_t base, const uint32_t limit, + const struct mpc_sie200_memory_range_t** range, + uint32_t *first_word_idx, + uint32_t *nr_words, + uint32_t *first_word_mask, + uint32_t *limit_word_mask) +{ + const struct mpc_sie200_memory_range_t* base_range; + uint32_t block_size; + uint32_t base_block_idx; + uint32_t base_word_idx; + uint32_t blk_max; + const struct mpc_sie200_memory_range_t* limit_range; + uint32_t limit_block_idx; + uint32_t limit_word_idx; + uint32_t mask; + uint32_t norm_base; + uint32_t norm_limit; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + /* + * Check that the addresses are within the controlled regions + * of this MPC + */ + if(!is_ctrl_by_range_list(dev, base, &base_range) || + !is_ctrl_by_range_list(dev, limit, &limit_range)) { + return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE; + } + + /* Base and limit should be part of the same range */ + if(base_range != limit_range) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + *range = base_range; + + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + /* Base and limit+1 addresses must be aligned on the MPC block size */ + if(base % block_size || (limit+1) % block_size) { + return MPC_SIE200_INTERN_ERR_NOT_ALIGNED; + } + + /* + * Get a normalized address that is an offset from the beginning + * of the lowest range controlled by the MPC + */ + norm_base = (base - base_range->base) + base_range->range_offset; + norm_limit = (limit - base_range->base) + base_range->range_offset; + + /* + * Calculate block index and to which 32 bits word it belongs + */ + limit_block_idx = norm_limit/block_size; + limit_word_idx = limit_block_idx/32; + + base_block_idx = norm_base/block_size; + base_word_idx = base_block_idx/32; + + if(base_block_idx > limit_block_idx) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + + /* Transmit the information to the caller */ + *nr_words = limit_word_idx - base_word_idx + 1; + *first_word_idx = base_word_idx; + + /* Limit to the highest block that can be configured */ + blk_max = p_mpc->blk_max; + + if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) { + return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH; + } + + /* + * Create the mask for the first word to only select the limit N bits + */ + *first_word_mask = ~((1 << (base_block_idx % 32)) - 1); + + /* + * Create the mask for the limit word to select only the first M bits. + */ + *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1; + /* + * If limit_word_mask is 0, it means that the limit touched block index is + * the limit in its word, so the limit word mask has all its bits selected + */ + if(*limit_word_mask == 0) { + *limit_word_mask = 0xFFFFFFFF; + } + + /* + * If the blocks to configure are all packed in one word, only + * touch this word. + * Code using the computed masks should test if this mask + * is non-zero, and if so, only use this one instead of the limit_word_mask + * and first_word_mask. + * As the only bits that are the same in both masks are the 1 that we want + * to select, just use XOR to extract them. + */ + if(base_word_idx == limit_word_idx) { + mask = ~(*first_word_mask ^ *limit_word_mask); + *first_word_mask = mask; + *limit_word_mask = mask; + } + + return MPC_SIE200_INTERN_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges) +{ + if((range_list == NULL) || (nbr_of_ranges == 0)) { + return MPC_SIE200_INVALID_ARG; + } + + dev->data->range_list = range_list; + dev->data->nbr_of_ranges = nbr_of_ranges; + dev->data->state = MPC_SIE200_INITIALIZED; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(blk_size == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* Calculate the block size in byte according to the manual */ + *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr) +{ + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_mask; + uint32_t limit_word_idx; + uint32_t nr_words; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx + nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to a generic errpr */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* + * The memory range should allow accesses in with the wanted security + * attribute if it requires special attribute for successful accesses + */ + if(range->attr != attr) { + return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + } + + /* + * Starts changing actual configuration so issue DMB to ensure every + * transaction has completed by now + */ + __DMB(); + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; + } + + /* First word */ + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + /* Partially configure the first word */ + p_mpc->blk_lutn = word_value; + + /* Fully configure the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + p_mpc->blk_lutn = 0xFFFFFFFF; + } else { + p_mpc->blk_lutn = 0x00000000; + } + } + + /* Partially configure the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= limit_word_mask; + } else { + word_value &= ~limit_word_mask; + } + p_mpc->blk_idx = limit_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, uint32_t limit, + enum mpc_sie200_sec_attr_t* attr) +{ + enum mpc_sie200_sec_attr_t attr_prev; + uint32_t block_size; + uint32_t block_size_mask; + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_idx; + uint32_t limit_word_mask; + uint32_t nr_words; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(attr == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* + * Initialize the security attribute to mixed in case of early + * termination of this function. A caller that does not check the + * returned error will act as if it does not know anything about the + * region queried, which is the safest bet + */ + *attr = MPC_SIE200_SEC_ATTR_MIXED; + + /* + * If the base and limit are not aligned, align them and make sure + * that the resulting region fully includes the original region + */ + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + block_size_mask = block_size - 1; + base &= ~(block_size_mask); + limit &= ~(block_size_mask); + limit += block_size - 1; /* Round to the upper block address, + * and then remove one to get the preceding + * address. + */ + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx+nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to generic error */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + word_value &= first_word_mask; + if(word_value == 0) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + /* + * If there are differences between the mask and the word value, + * it means that the security attributes of blocks are mixed + */ + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + return MPC_SIE200_ERR_NONE; + } + + /* Get the partial configuration of the first word */ + word_value = p_mpc->blk_lutn & first_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + /* + * Bail out as the security attribute will be the same regardless + * of the configuration of other blocks + */ + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + /* + * Store the current found attribute, to check that all the blocks indeed + * have the same security attribute. + */ + attr_prev = *attr; + + /* Get the configuration of the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + word_value = p_mpc->blk_lutn; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value == 0xFFFFFFFF) { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } else { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + /* If the attribute is different than the one found before, bail out */ + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + attr_prev = *attr; + } + + /* Get the partial configuration of the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn & limit_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(ctrl_val == 0) { + return MPC_SIE200_INVALID_ARG; + } + + *ctrl_val = p_mpc->ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl = mpc_ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(sec_rep == 0) { + return MPC_SIE200_INVALID_ARG; + } + + if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) { + *sec_rep = MPC_SIE200_RESP_BUS_ERROR; + return MPC_SIE200_ERR_NONE; + } + + *sec_rep = MPC_SIE200_RESP_RAZ_WI; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->int_en |= MPC_SIE200_INT_EN; + + return MPC_SIE200_ERR_NONE; +} + +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_en &= ~MPC_SIE200_INT_EN; +} + +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_clear = MPC_SIE200_INT_EN; +} + +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + return (p_mpc->int_stat & MPC_SIE200_INT_STAT); +} + +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT + | MPC_SIE200_CTRL_SEC_LOCK_DOWN); + + return MPC_SIE200_ERR_NONE; +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.h b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.h new file mode 100644 index 00000000..998a5f10 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpc_sie200_drv.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file mpc_sie200_drv.h + * \brief Generic driver for ARM SIE 200 Memory Protection + * Controllers (MPC). + */ + +#ifndef __MPC_SIE_200_DRV_H__ +#define __MPC_SIE_200_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error code returned by the driver functions */ +enum mpc_sie200_error_t { + MPC_SIE200_ERR_NONE, /*!< No error */ + MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */ + MPC_SIE200_NOT_INIT, /*!< MPC not initialized */ + MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range + * controlled by the MPC */ + MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size + * of this MPC + */ + MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure + * is invalid. This could be because: + * - The base and limit swapped + * - The base and limit addresses + * are in different ranges + */ + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be + * accessed with the wanted + * security attributes + */ +}; + +/* Security attribute used in various place of the API */ +enum mpc_sie200_sec_attr_t { + MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */ + MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */ + /*!< Used when getting the configuration of a memory range and some blocks + * are secure whereas some other are non secure + */ + MPC_SIE200_SEC_ATTR_MIXED, +}; + +/* What can happen when trying to do an illegal memory access */ +enum mpc_sie200_sec_resp_t { + MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */ + MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */ +}; + +/* Description of a memory range controlled by the MPC */ +struct mpc_sie200_memory_range_t { + const uint32_t base; /*!< Base address (included in the range) */ + const uint32_t limit; /*!< Limit address (included in the range) */ + const uint32_t range_offset; /*!< Offset of current range area to the 0 + * point of the whole area (the sum of the + * sizes of the previous memory ranges + * covered by the same MPC) + */ + const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute + * needed to be matched when + * accessing this range. + * For example, the non-secure + * alias of a memory region can not + * be accessed using secure access, + * and configuring the MPC to + * secure using that range will not + * be permitted by the driver. + */ +}; + +/* ARM MPC SIE 200 device configuration structure */ +struct mpc_sie200_dev_cfg_t { + const uint32_t base; /*!< MPC base address */ +}; + +/* ARM MPC SIE 200 device data structure */ +struct mpc_sie200_dev_data_t { + /*!< Array of pointers to memory ranges controlled by the MPC */ + const struct mpc_sie200_memory_range_t** range_list; + uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */ + uint8_t state; /*!< Indicates if the MPC driver + * is initialized and enabled + */ + uint16_t reserved; /*!< 32 bits alignment */ +}; + +/* ARM MPC SIE 200 device structure */ +struct mpc_sie200_dev_t { + const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */ + struct mpc_sie200_dev_data_t* const data; /*!< MPC data */ +}; + +/** + * \brief Initializes a MPC device. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] range_list List of memory ranges controller by the MPC + * (\ref mpc_sie200_memory_range_t). This list can not + * freed after the initializations. + * \param[in] nbr_of_ranges Number of memory ranges + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges); + +/** + * \brief Gets MPC block size. All regions must be aligned on this block + * size (base address and limit+1 address). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] blk_size MPC block size + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size); + +/** + * \brief Configures a memory region (base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to poll. This bound is + * included. It does not need to be aligned in any way. + * + * \param[in] limit Limit address of the region to poll. This bound is + * included. (limit+1) does not need to be aligned + * in any way. + * \param[in] attr Security attribute of the region. If the region has mixed + * secure/non-secure, a special value is returned + * (\ref mpc_sie200_sec_attr_t). + * + * In case base and limit+1 addresses are not aligned on + * the block size, the enclosing region with base and + * limit+1 aligned on block size will be queried. + * In case of early termination of the function (error), the + * security attribute will be set to MPC_SIE200_ATTR_MIXED. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr); + +/** + * \brief Gets a memory region configuration(base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to get the configuration. + * \param[in] limit Limit address of the region to get the configuration. + * \param[out] attr Security attribute of the region + * \ref mpc_sie200_sec_attr_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, + uint32_t limit, + enum mpc_sie200_sec_attr_t* attr); + +/** + * \brief Gets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] ctrl_val Current MPC control value. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val); + +/** + * \brief Sets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] mpc_ctrl New MPC control value + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl); + +/** + * \brief Gets the configured secure response. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t). + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep); + +/** + * \brief Enables MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Disables MPC interrupt + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Clears MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev); + +/** + * \brief Returns the MPC interrupt state. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns 1 if the interrupt is active, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev); + +/** + * \brief Locks down the MPC configuration. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev); + +#ifdef __cplusplus +} +#endif +#endif /* __MPC_SIE_200_DRV_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.c b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.c new file mode 100644 index 00000000..ad9efab9 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2017-2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "mpu_armv8m_drv.h" +#include "cmsis.h" + +/* + * FixMe: + * This is a beta quality driver for MPU in v8M. To be finalized. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en) +{ + /*No error checking*/ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* + * FixMe: Set 3 pre-defined MAIR_ATTR for memory. The attributes come + * from default memory map, need to check if fine-tune is necessary. + * + * MAIR0_0: Peripheral, Device-nGnRE. + * MAIR0_1: Code, WT RA. Same attr for Outer and Inner. + * MAIR0_2: SRAM, WBWA RA. Same attr for Outer and Inner. + */ + mpu->MAIR0 = (MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL << MPU_MAIR0_Attr0_Pos) | + (MPU_ARMV8M_MAIR_ATTR_CODE_VAL << MPU_MAIR0_Attr1_Pos) | + (MPU_ARMV8M_MAIR_ATTR_DATA_VAL << MPU_MAIR0_Attr2_Pos); + + mpu->CTRL = + (privdef_en ? MPU_CTRL_PRIVDEFENA_Msk : 0) | + (hfnmi_en ? MPU_CTRL_HFNMIENA_Msk : 0); + + /*Ensure all configuration is written before enable*/ + + mpu->CTRL |= MPU_CTRL_ENABLE_Msk; + + /* Enable MPU before next instruction */ + __DSB(); + __ISB(); + return MPU_ARMV8M_OK; +} + +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* Reset all fields as enable does full setup */ + mpu->CTRL = 0; + + return MPU_ARMV8M_OK; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + uint32_t base_cfg; + uint32_t limit_cfg; + + /*FIXME : Add complete error checking*/ + if ((region_cfg->region_base & ~MPU_RBAR_BASE_Msk) != 0) { + return MPU_ARMV8M_ERROR; + } + /* region_limit doesn't need to be aligned but the scatter + * file needs to be setup to ensure that partitions do not overlap. + */ + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_cfg->region_nr & MPU_RNR_REGION_Msk; + + /* This 0s the lower bits of the base address */ + base_cfg = region_cfg->region_base & MPU_RBAR_BASE_Msk; + base_cfg |= (region_cfg->attr_sh << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk; + base_cfg |= (region_cfg->attr_access << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk; + base_cfg |= (region_cfg->attr_exec << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk; + + mpu->RBAR = base_cfg; + + /*This 0s the lower bits of base address but they are treated as 1 */ + limit_cfg = (region_cfg->region_limit-1) & MPU_RLAR_LIMIT_Msk; + + limit_cfg |= (region_cfg->region_attridx << MPU_RLAR_AttrIndx_Pos) & + MPU_RLAR_AttrIndx_Msk; + + limit_cfg |= MPU_RLAR_EN_Msk; + + mpu->RLAR = limit_cfg; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + /* Enable MPU before the next instruction */ + __DSB(); + __ISB(); + + return ret_val; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr) +{ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + + /*FIXME : Add complete error checking*/ + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_nr & MPU_RNR_REGION_Msk; + + mpu->RBAR = 0; + mpu->RLAR = 0; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + return ret_val; +} + +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + uint32_t i = (mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + while (i > 0) { + mpu_armv8m_region_disable(dev, i-1); + i--; + } + + return MPU_ARMV8M_OK; + +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.h b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.h new file mode 100644 index 00000000..d427604f --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/mpu_armv8m_drv.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017-2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MPU_ARMV8M_DRV_H__ +#define __MPU_ARMV8M_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define PRIVILEGED_DEFAULT_ENABLE 1 +#define HARDFAULT_NMI_ENABLE 1 + +/* MAIR_ATTR */ +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL 0x04 +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX 0 +#define MPU_ARMV8M_MAIR_ATTR_CODE_VAL 0xAA +#define MPU_ARMV8M_MAIR_ATTR_CODE_IDX 1 +#define MPU_ARMV8M_MAIR_ATTR_DATA_VAL 0xFF +#define MPU_ARMV8M_MAIR_ATTR_DATA_IDX 2 + +struct mpu_armv8m_dev_t { + const uint32_t base; +}; + +enum mpu_armv8m_error_t { + MPU_ARMV8M_OK, + MPU_ARMV8M_ERROR +}; + +enum mpu_armv8m_attr_exec_t { + MPU_ARMV8M_XN_EXEC_OK, + MPU_ARMV8M_XN_EXEC_NEVER +}; + +enum mpu_armv8m_attr_access_t { + MPU_ARMV8M_AP_RW_PRIV_ONLY, + MPU_ARMV8M_AP_RW_PRIV_UNPRIV, + MPU_ARMV8M_AP_RO_PRIV_ONLY, + MPU_ARMV8M_AP_RO_PRIV_UNPRIV +}; + +enum mpu_armv8m_attr_shared_t { + MPU_ARMV8M_SH_NONE, + MPU_ARMV8M_SH_UNUSED, + MPU_ARMV8M_SH_OUTER, + MPU_ARMV8M_SH_INNER +}; + +struct mpu_armv8m_region_cfg_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; + uint32_t region_attridx; + enum mpu_armv8m_attr_exec_t attr_exec; + enum mpu_armv8m_attr_access_t attr_access; + enum mpu_armv8m_attr_shared_t attr_sh; +}; + +struct mpu_armv8m_region_cfg_raw_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; +}; + + +/** + * \brief Enable MPU + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] privdef_en privilege default region 1:enable 0:disable + * \param[in] hfnmi_en mpu for hard fault & nmi 1:enable 0:disable + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en); + +/** + * \brief Disable MPU + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * + * \return Error code \ref arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Disable MPU and clean all regions + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * + * \return Error code \ref arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Enable MPU Region + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] region_cfg MPU region config \ref mpu_armv8m_region_cfg_t + * + * \return Error code \ref arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg); + +/** + * \brief Disable MPU Region + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] region_nr Region number + * + * \return Error code \ref arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPU_ARMV8M_DRV_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.c b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.c new file mode 100644 index 00000000..dda05506 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.c @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ppc_sse200_drv.h" + +/* SPCTRL PPCs control memory mapped registers access structure */ +struct arm_spctrl_ppc_sse200_t { + volatile uint32_t reserved[8]; + volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */ + volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */ + volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */ + volatile uint32_t reserved1[9]; + volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral + * Protection Control #0 + */ + volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access + * AHB Slave Peripheral Protection Control + */ + volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB + * slave Peripheral Protection Control + */ + volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB + * slave Peripheral Protection Control + */ + volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB + * slave Peripheral Protection Control + */ + volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB + * slave Peripheral Protection Control + */ + volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral + * Protection Control 0 + */ + volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral + * Protection Control 1 + */ + volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral + * Protection Control [3:1] + */ + volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB + * slave Peripheral Protection Control + */ + volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB + * slave Peripheral Protection Control + */ + volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB + * slave Peripheral Protection Control + */ + volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB + * slave Peripheral Protection Control + */ + volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave + * Peripheral Protection Control 0 + */ + volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged + * Access AHB slave Peripheral Protection + * Control + */ + volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access + * AHB slave Peripheral Protection Control + */ + volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access + * AHB slave Peripheral Protection Control + */ + volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access + * AHB slave Peripheral Protection Control + */ + volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access + * AHB slave Peripheral Protection Control + */ + volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave + * Peripheral 0 + */ + volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave + * Peripheral 1 + */ + volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged + * Access APB slave Peripheral Protection + * Control + */ + volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access + * APB slave Peripheral Protection + * Control + */ + volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access + * APB slave Peripheral Protection + * Control + */ + volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access + * APB slave Peripheral Protection + * Control + */ + volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access + * APB slave Peripheral Protection + * Control + */ +}; + +/* NSPCTRL PPCs memory mapped register access structure */ +struct arm_nspctrl_ppc_sse200_t { + volatile uint32_t reserved[36]; + volatile uint32_t ahbnspppc0; + volatile uint32_t reserved1[3]; + volatile uint32_t ahbnspppcexp0; + volatile uint32_t ahbnspppcexp1; + volatile uint32_t ahbnspppcexp2; + volatile uint32_t ahbnspppcexp3; + volatile uint32_t apbnspppc0; + volatile uint32_t apbnspppc1; + volatile uint32_t reserved2[2]; + volatile uint32_t apbnspppcexp0; + volatile uint32_t apbnspppcexp1; + volatile uint32_t apbnspppcexp2; + volatile uint32_t apbnspppcexp3; +}; + +/* PPC interrupt position mask */ +#define APB_PPC0_INT_POS_MASK (1UL << 0) +#define APB_PPC1_INT_POS_MASK (1UL << 1) +/* Reserved bits 2:3 */ +#define APB_PPCEXP0_INT_POS_MASK (1UL << 4) +#define APB_PPCEXP1_INT_POS_MASK (1UL << 5) +#define APB_PPCEXP2_INT_POS_MASK (1UL << 6) +#define APB_PPCEXP3_INT_POS_MASK (1UL << 7) +/* Reserved bits 8:15 */ +#define AHB_PPC0_INT_POS_MASK (1UL << 16) +/* Reserved bits 17:19 */ +#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20) +#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21) +#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22) +#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23) +/* Reserved bits 24:31 */ + +/* ARM PPC state definitions */ +#define PPC_SSE200_INITIALIZED (1 << 0) + +/* Default peripheral states */ +#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1 +#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1 + +void ppc_sse200_init(struct ppc_sse200_dev_t* dev, + enum ppc_sse200_name_t ppc_name) +{ + struct arm_spctrl_ppc_sse200_t* p_spctrl = + (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; + struct arm_nspctrl_ppc_sse200_t* p_nspctrl = + (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base; + + switch(ppc_name) { + case AHB_PPC0: + dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0; + dev->data->p_sp_ppc = &p_spctrl->ahbspppc0; + dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0; + dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; + break; + case AHB_PPC_EXP0: + dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0; + dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0; + dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0; + dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; + break; + case AHB_PPC_EXP1: + dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1; + dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1; + dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1; + dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; + break; + case AHB_PPC_EXP2: + dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2; + dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2; + dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2; + dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; + break; + case AHB_PPC_EXP3: + dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3; + dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3; + dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3; + dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; + break; + case APB_PPC0: + dev->data->p_ns_ppc = &p_spctrl->apbnsppc0; + dev->data->p_sp_ppc = &p_spctrl->apbspppc0; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0; + dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; + break; + case APB_PPC1: + dev->data->p_ns_ppc = &p_spctrl->apbnsppc1; + dev->data->p_sp_ppc = &p_spctrl->apbspppc1; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1; + dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; + break; + case APB_PPC_EXP0: + dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0; + dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0; + dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; + break; + case APB_PPC_EXP1: + dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1; + dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1; + dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; + break; + case APB_PPC_EXP2: + dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2; + dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2; + dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; + break; + case APB_PPC_EXP3: + dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3; + dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3; + dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3; + dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK; + break; + /* default: The default is not defined intentionally to force the + * compiler to check that all enumeration values are + * covered in the switch. + */ + } + + dev->data->state = PPC_SSE200_INITIALIZED; +} + +enum ppc_sse200_error_t ppc_sse200_config_peripheral( + struct ppc_sse200_dev_t* dev, + uint8_t periph, + enum ppc_sse200_sec_attr_t sec_attr, + enum ppc_sse200_priv_attr_t priv_attr) +{ + if(dev->data->state != PPC_SSE200_INITIALIZED) { + return PPC_SSE200_NOT_INIT; + } + + if(sec_attr == PPC_SSE200_SECURE_ONLY) { + /* Sets secure attribute */ + *(dev->data->p_ns_ppc) &= ~(1U << periph); + + /* Uses secure unprivileged access address (SPCTRL) to set privilege + * attribute + */ + if(priv_attr == PPC_SSE200_PRIV_ONLY) { + *(dev->data->p_sp_ppc) &= ~(1U << periph); + } else { + *(dev->data->p_sp_ppc) |= (1U << periph); + } + } else { + /* Sets secure attribute */ + *(dev->data->p_ns_ppc) |= (1U << periph); + + /* Uses non-secure unprivileged access address (NSPCTRL) to set + * privilege attribute + */ + if(priv_attr == PPC_SSE200_PRIV_ONLY) { + *(dev->data->p_nsp_ppc) &= ~(1U << periph); + } else { + *(dev->data->p_nsp_ppc) |= (1U << periph); + } + } + + return PPC_SSE200_ERR_NONE; +} + +uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev, + uint8_t periph) +{ + if(dev->data->state != PPC_SSE200_INITIALIZED) { + return SECURE_AS_DEFAULT_PERIPHERAL_STATE; + } + + return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0); +} + +uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev, + uint8_t periph) +{ + if(dev->data->state != PPC_SSE200_INITIALIZED) { + return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE; + } + + if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) { + /* Returns secure unprivileged access address (SPCTRL) */ + return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0); + } else { + /* Returns non-secure unprivileged access address (NSPCTRL) */ + return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0); + } +} + +enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev) +{ + struct arm_spctrl_ppc_sse200_t* p_spctrl = + (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; + + if(dev->data->state != PPC_SSE200_INITIALIZED) { + return PPC_SSE200_NOT_INIT; + } + + p_spctrl->secppcinten |= dev->data->int_bit_mask; + + return PPC_SSE200_ERR_NONE; +} + +void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev) +{ + struct arm_spctrl_ppc_sse200_t* p_spctrl = + (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; + + if(dev->data->state == PPC_SSE200_INITIALIZED) { + p_spctrl->secppcinten &= ~(dev->data->int_bit_mask); + } +} + +void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev) +{ + struct arm_spctrl_ppc_sse200_t* p_spctrl = + (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; + + if(dev->data->state == PPC_SSE200_INITIALIZED) { + p_spctrl->secppcintclr = dev->data->int_bit_mask; + } +} + +uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev) +{ + struct arm_spctrl_ppc_sse200_t* p_spctrl = + (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; + + if(dev->data->state != PPC_SSE200_INITIALIZED) { + return 0; + } + + return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0); +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.h b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.h new file mode 100644 index 00000000..7a08a8f9 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/ppc_sse200_drv.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file ppc_sse200_drv.h + * \brief Generic driver for ARM SEE 200 Peripheral Protection + * Controllers (PPC). + */ + +#ifndef __PPC_SSE_200_DRV_H__ +#define __PPC_SSE_200_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Secure Privilege Control Block aka SPCTRL */ +/* Non-Secure Privilege Control Block aka NSPCTRL */ + +/* ARM TrustZone PPC device configuration structure */ +struct ppc_sse200_dev_cfg_t { + uint32_t const spctrl_base; /*!< SPCTRL base address */ + uint32_t const nspctrl_base; /*!< NSPCTRL base address */ +}; + +/* ARM TrustZone PPC device data structure */ +struct ppc_sse200_dev_data_t { + volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */ + volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged + * register + */ + volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged + * register + */ + uint32_t int_bit_mask; /*!< Interrupt bit mask */ + uint8_t state; /*!< Indicates if the PPC driver + * is initialized + */ + uint8_t reserved[3]; /*!< 32 bits alignment */ +}; + +/* ARM PPC device structure */ +struct ppc_sse200_dev_t { + const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */ + struct ppc_sse200_dev_data_t* const data; /*!< PPC data */ +}; + +/* Security attribute used to configure the peripheral */ +enum ppc_sse200_sec_attr_t { + PPC_SSE200_SECURE_ONLY, /*! Secure access */ + PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */ +}; + +/* Privilege attribute used to configure the peripheral */ +enum ppc_sse200_priv_attr_t { + PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */ + PPC_SSE200_PRIV_ONLY, /*! Privilege only access */ +}; + +/* ARM PPC error codes */ +enum ppc_sse200_error_t { + PPC_SSE200_ERR_NONE = 0, /*!< No error */ + PPC_SSE200_NOT_INIT, /*!< PPC not initialized */ +}; + +/* ARM PPC names */ +enum ppc_sse200_name_t { + AHB_PPC0 = 0, /*!< AHB PPC0 */ + AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */ + AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */ + AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */ + AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */ + APB_PPC0, /*!< APB PPC0 */ + APB_PPC1, /*!< APB PPC1 */ + APB_PPC_EXP0, /*!< Expansion 0 APB PPC */ + APB_PPC_EXP1, /*!< Expansion 1 APB PPC */ + APB_PPC_EXP2, /*!< Expansion 2 APB PPC */ + APB_PPC_EXP3 /*!< Expansion 3 APB PPC */ +}; + +/** + * \brief Initialize the PPC device. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * \param[in] ppc_name PPC name \ref ppc_sse200_name_t + * + * \note This function doesn't check if dev is NULL. + */ +void ppc_sse200_init(struct ppc_sse200_dev_t* dev, + enum ppc_sse200_name_t ppc_name); + +/** + * \brief Configures the PPC device. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * \param[in] periph Peripheral position in the PPC. + * \param[in] sec_attr Secure attribute value. + * \param[in] priv_attr Privilege attribute value. + * + * \return Returns error code as specified in \ref ppc_sse200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum ppc_sse200_error_t ppc_sse200_config_peripheral( + struct ppc_sse200_dev_t* dev, + uint8_t periph, + enum ppc_sse200_sec_attr_t sec_attr, + enum ppc_sse200_priv_attr_t priv_attr); +/** + * \brief Checks if the peripheral is configured as secure or non-secure. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * \param[in] periph Peripheral position in the PPC. + * + * \return Returns 1 for secure and 0 for non-secure. + * If the driver is not initialized the return value is 1 (secure) as + * it is the default system configuration. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev, + uint8_t periph); + +/** + * \brief Checks if the peripheral is configured as Privilege only or + * Privilege and non-Privilege access mode. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * \param[in] periph Peripheral position in the PPC. + * + * \return Returns 1 for Privilege only configuration and 0 for Privilege and + * non-Privilege access. + * If the driver is not initialized the return of this function is + * 1 (Privilege only) as it is the default system configuration. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev, + uint8_t periph); +/** + * \brief Enables PPC interrupt. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * + * \return Returns error code as specified in \ref ppc_sse200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev); + +/** + * \brief Disables PPC interrupt. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev); + +/** + * \brief Clears PPC interrupt. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev); + +/** + * \brief Returns the PPC interrupt state. + * + * \param[in] dev PPC device \ref ppc_sse200_dev_t + * + * \return Returns 1 if the interrupt is active and otherwise 0. + * If the driver is not initialized the return of this function is + * 0 (not active) as it is the default system configuration. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev); + +#ifdef __cplusplus +} +#endif + +#endif /* __PPC_SSE_200_DRV_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.c b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.c new file mode 100644 index 00000000..b051909b --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file timer_cmsdk_drv.c + * \brief Generic driver for CMSDK APB Timers. + * The timer is a 32-bit down-counter with the following features: + * - optional programmable external clock source + * - programmable interrupt source, triggered if counter reaches 0 + * - automatic reload if counter reaches 0 + */ + +#include "timer_cmsdk_drv.h" + +/** Setter bit manipulation macro */ +#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) +/** Clearing bit manipulation macro */ +#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) +/** Getter bit manipulation macro */ +#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX)))) + +/** + * \brief Timer register map structure + * + */ +struct timer_cmsdk_reg_map_t { + volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ + volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */ + volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */ + union { + volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt + * status register + */ + volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt + * clear register + */ + }intreg; +}; + +/** + * \brief CTRL register bit definitions + * + */ +enum ctrl_reg_bits_t { + CTRL_REG_ENUM_ENABLE_INDEX = 0, + CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1, + CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2, + CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3 +}; + +/** + * \brief INTSTATUS/INTCLEAR register bit definitions + * + */ +enum interrupt_reg_bits_t { + INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0 +}; + +void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + + if (dev->data->is_initialized == 0) { + register_map->ctrl = 0; + register_map->reload = TIMER_CMSDK_DEFAULT_RELOAD; + dev->data->is_initialized = 1; + } +} + +bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev) +{ + return dev->data->is_initialized; +} + +void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); +} + +void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); +} + +bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return GET_BIT(register_map->ctrl, + CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); +} + +void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); +} + +void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); +} + +bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return GET_BIT(register_map->ctrl, + CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); +} + +void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); +} + +void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); +} + +bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); +} + +void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); +} + +void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); +} + +bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); +} + +bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return GET_BIT(register_map->intreg.intstatus, + INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX); +} + +void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + SET_BIT(register_map->intreg.intclear, + INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX); +} + +uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return register_map->value; +} + +void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev, + uint32_t reload) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + register_map->reload = reload; +} + +void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + register_map->value = register_map->reload; +} + +uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return register_map->reload; +} + +uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev) +{ + struct timer_cmsdk_reg_map_t* register_map = + (struct timer_cmsdk_reg_map_t*)dev->cfg->base; + return register_map->reload - register_map->value; +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.h b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.h new file mode 100644 index 00000000..a374e63b --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/timer_cmsdk_drv.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file timer_cmsdk_drv.h + * \brief Generic driver for CMSDK APB Timers. + * The timer is a 32-bit down-counter with the following features: + * - optional programmable external clock source + * - programmable interrupt source, triggered if counter reaches 0 + * - automatic reload if counter reaches 0 + */ + +#ifndef __TIMER_CMSDK_DRV_H__ +#define __TIMER_CMSDK_DRV_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Maximum reload value */ +#define TIMER_CMSDK_MAX_RELOAD UINT32_MAX /* max of 32-bit */ +#define TIMER_CMSDK_DEFAULT_RELOAD TIMER_CMSDK_MAX_RELOAD + +/** CMSDK timer device configuration structure */ +struct timer_cmsdk_dev_cfg_t { + const uintptr_t base; /*!< Timer base address */ +}; + +/** CMSDK timer device data structure */ +struct timer_cmsdk_dev_data_t { + bool is_initialized; /*!< Indicates if the timer is initialized */ +}; + +/* CMSDK timer device structure */ +struct timer_cmsdk_dev_t { + const struct timer_cmsdk_dev_cfg_t* const cfg; /*!< Timer configuration */ + struct timer_cmsdk_dev_data_t* const data; /*!< Timer data */ +}; + +/** + * \brief Initializes timer to a known default state, which is: + * - timer disabled + * - timer interrupt disabled + * - clock source set to internal + * - external input disabled + * - reload value maxed out + * Init should be called prior to any other process and + * it's the caller's responsibility to follow proper call order. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Checks if a timer is initialized. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return true if initialized, false otherwise + */ +bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Enables external input, which could be used as clock source + * by calling \ref timer_cmsdk_set_clock_to_external. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Disables external input. + * Make sure if the timer is explicitly wanted to be stopped or set + * the clock source to internal by \ref timer_cmsdk_set_clock_to_internal + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Checks if external input is enabled. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return true if enabled, false otherwise + */ +bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Sets the clock source to internal. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Sets the clock source to external. + * Make sure external input is enabled correspondingly + * by \ref timer_cmsdk_enable_external_input. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Checks if clock source is external input. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return true if external, false if internal + */ +bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Enables timer operation. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Disables the given hardware timer. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Checks if a timer is enabled. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return true if enabled, false otherwise + */ +bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Enables timer interrupt. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Disables timer interrupt. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Checks if a timer interrupt is enabled. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return true if enabled, false otherwise + */ +bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Gets timer interrupt status + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * * \return true if active, false otherwise + */ +bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Clears timer interrupt + * The interrupt request is held until it is cleared. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Reads timer current value. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return Timer value + */ +uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Sets the reload value of the selected timer. + * + * New reload value takes effect when: + * - timer is restarted + * - on timer underflow + * - when timer_cmsdk_reset is called + * + * \note In r1p0 technical reference manual it's incorrectly stated + * writing the reload value automatically sets the current value also. + * r1p1 technical reference manual includes the fix. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * \param[in] reload Timer reload value to set. + * This is the start value of the 32-bit down counter, + * which automatically reloaded if 0 is reached. + */ +void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev, + uint32_t reload); + +/** + * \brief Resets the timer counter to the reload value instantly + * (i.e. without waiting for underflow). + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + */ +void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Gets the reload value of the selected timer. + * This is the start value of the 32-bit down counter, + * which is automatically reloaded if 0 is reached by the counter. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return Reload value of the selected timer. + */ +uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev); + +/** + * \brief Reads the number of ticks elapsed in the current cycle. + * + * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t + * + * \return Get elapsed number of ticks since last reload was set. + * Elapsed = (Reload value - Current value) + */ +uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev); + +#ifdef __cplusplus +} +#endif +#endif /* __TIMER_CMSDK_DRV_H__ */ diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.c b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.c new file mode 100644 index 00000000..c3d12300 --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "uart_cmsdk_drv.h" + +#include + +/* UART register map structure */ +struct _uart_cmsdk_reg_map_t { + volatile uint32_t data; /* Offset: 0x000 (R/W) data register */ + volatile uint32_t state; /* Offset: 0x004 (R/W) status register */ + volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ + union { + volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status + * register + */ + volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear + * register + */ + }intr_reg; + volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider + * register + */ +}; + +/* CTRL Register */ +#define UART_CMSDK_TX_EN (1ul << 0) +#define UART_CMSDK_RX_EN (1ul << 1) +#define UART_CMSDK_TX_INTR_EN (1ul << 2) +#define UART_CMSDK_RX_INTR_EN (1ul << 3) + +/* STATE Register */ +#define UART_CMSDK_TX_BF (1ul << 0) +#define UART_CMSDK_RX_BF (1ul << 1) + +/* INTSTATUS Register */ +#define UART_CMSDK_TX_INTR (1ul << 0) +#define UART_CMSDK_RX_INTR (1ul << 1) + +/* UART state definitions */ +#define UART_CMSDK_INITIALIZED (1ul << 0) + +enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev, + uint32_t system_clk) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + if(system_clk == 0) { + return UART_CMSDK_ERR_INVALID_ARG; + } + + /* Sets baudrate and system clock */ + dev->data->system_clk = system_clk; + dev->data->baudrate = dev->cfg->default_baudrate; + + /* Sets baudrate */ + p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate); + + /* Enables receiver and transmitter */ + p_uart->ctrl = UART_CMSDK_RX_EN | UART_CMSDK_TX_EN; + + dev->data->state = UART_CMSDK_INITIALIZED; + + return UART_CMSDK_ERR_NONE; +} + +enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev, + uint32_t baudrate) +{ + uint32_t bauddiv; + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(baudrate == 0) { + return UART_CMSDK_ERR_INVALID_BAUD; + } + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return UART_CMSDK_ERR_NOT_INIT; + } + + /* Sets baudrate */ + bauddiv = (dev->data->system_clk / baudrate); + dev->data->baudrate = baudrate; + + /* Minimum bauddiv value */ + if(bauddiv < 16) { + return UART_CMSDK_ERR_INVALID_BAUD; + } + + p_uart->bauddiv = bauddiv; + + return UART_CMSDK_ERR_NONE; +} + +uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev) +{ + return dev->data->baudrate; +} + +enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev, + uint32_t system_clk) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(system_clk == 0) { + return UART_CMSDK_ERR_INVALID_ARG; + } + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return UART_CMSDK_ERR_NOT_INIT; + } + + /* Sets system clock */ + dev->data->system_clk = system_clk; + + /* Updates baudrate divider */ + p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate); + + /* Enables receiver and transmitter */ + return UART_CMSDK_ERR_NONE; +} + +enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev, + uint8_t* byte) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(!(p_uart->state & UART_CMSDK_RX_BF)) { + return UART_CMSDK_ERR_NOT_READY; + } + + /* Reads data */ + *byte = (uint8_t)p_uart->data; + + return UART_CMSDK_ERR_NONE; +} + +enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev, + uint8_t byte) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(p_uart->state & UART_CMSDK_TX_BF) { + return UART_CMSDK_ERR_NOT_READY; + } + + /* Sends data */ + p_uart->data = byte; + + return UART_CMSDK_ERR_NONE; +} + +enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return UART_CMSDK_ERR_NOT_INIT; + } + + p_uart->ctrl |= UART_CMSDK_TX_INTR_EN; + + return UART_CMSDK_ERR_NONE; +} + +void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(dev->data->state & UART_CMSDK_INITIALIZED ) { + p_uart->ctrl &= ~UART_CMSDK_TX_INTR_EN; + } +} + +uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return 0; + } + + return !(p_uart->state & UART_CMSDK_TX_BF); +} + +enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return UART_CMSDK_ERR_NOT_INIT; + } + + p_uart->ctrl |= UART_CMSDK_RX_INTR_EN; + + return UART_CMSDK_ERR_NONE; +} + +void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(dev->data->state & UART_CMSDK_INITIALIZED) { + p_uart->ctrl &= ~UART_CMSDK_RX_INTR_EN; + } +} + +uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { + return 0; + } + + return (p_uart->state & UART_CMSDK_RX_BF); +} + +void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev, + enum uart_cmsdk_irq_t irq) +{ + struct _uart_cmsdk_reg_map_t* p_uart = + (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; + + if(dev->data->state & UART_CMSDK_INITIALIZED) { + /* Clears pending interrupts */ + switch(irq) { + case UART_CMSDK_IRQ_RX: + p_uart->intr_reg.intrclear = UART_CMSDK_RX_INTR; + break; + case UART_CMSDK_IRQ_TX: + p_uart->intr_reg.intrclear = UART_CMSDK_TX_INTR; + break; + case UART_CMSDK_IRQ_COMBINED: + p_uart->intr_reg.intrclear = + (UART_CMSDK_RX_INTR | UART_CMSDK_TX_INTR); + break; + /* default: not defined to force all cases to be handled */ + } + } +} diff --git a/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.h b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.h new file mode 100644 index 00000000..2d3278ef --- /dev/null +++ b/Arm/MPS3_AN524/lib/AN524/src/native_drivers/uart_cmsdk_drv.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file uart_cmsdk_drv.h + * \brief Generic driver for ARM UART. + */ + +#ifndef __UART_CMSDK_DRV_H__ +#define __UART_CMSDK_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ARM UART device configuration structure */ +struct uart_cmsdk_dev_cfg_t { + const uint32_t base; /*!< UART base address */ + const uint32_t default_baudrate; /*!< Default baudrate */ +}; + +/* ARM UART device data structure */ +struct uart_cmsdk_dev_data_t { + uint32_t state; /*!< Indicates if the uart driver + * is initialized and enabled + */ + uint32_t system_clk; /*!< System clock */ + uint32_t baudrate; /*!< Baudrate */ +}; + +/* ARM UART device structure */ +struct uart_cmsdk_dev_t { + const struct uart_cmsdk_dev_cfg_t* const cfg; /*!< UART configuration */ + struct uart_cmsdk_dev_data_t* const data; /*!< UART data */ +}; + +/* ARM UART enumeration types */ +enum uart_cmsdk_error_t { + UART_CMSDK_ERR_NONE = 0, /*!< No error */ + UART_CMSDK_ERR_INVALID_ARG, /*!< Error invalid input argument */ + UART_CMSDK_ERR_INVALID_BAUD, /*!< Invalid baudrate */ + UART_CMSDK_ERR_NOT_INIT, /*!< Error UART not initialized */ + UART_CMSDK_ERR_NOT_READY, /*!< Error UART not ready */ +}; + +enum uart_cmsdk_irq_t { + UART_CMSDK_IRQ_RX, /*!< RX interrupt source */ + UART_CMSDK_IRQ_TX, /*!< TX interrupt source */ + UART_CMSDK_IRQ_COMBINED /*!< RX-TX combined interrupt source */ +}; + +/** + * \brief Initializes UART. It uses the default baudrate to configure + * the peripheral at this point. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] system_clk System clock used by the device. + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev, + uint32_t system_clk); + +/** + * \brief Sets the UART baudrate. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] baudrate New baudrate. + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev, + uint32_t baudrate); + +/** + * \brief Gets the UART baudrate. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \return Returns the UART baudrate. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Sets system clock. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] system_clk System clock used by the device. + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev, + uint32_t system_clk); +/** + * \brief Reads one byte from UART dev. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] byte Pointer to byte. + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note For better performance, this function doesn't check if dev and byte + * pointer are NULL, and if the driver is initialized. + */ +enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev, + uint8_t* byte); + +/** + * \brief Writes a byte to UART dev. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] byte Byte to write. + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note For better performance, this function doesn't check if dev is NULL and + * if the driver is initialized to have better performance. + */ +enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev, + uint8_t byte); + +/** + * \brief Enables TX interrupt. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Disables TX interrupt. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Verifies if Tx is ready to send more data. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \return 1 if TX is ready, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Enables RX interrupt. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \return Returns error code as specified in \ref uart_cmsdk_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Disables RX interrupt + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Verifies if Rx has data. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * + * \return 1 if RX has data, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev); + +/** + * \brief Clears UART interrupt. + * + * \param[in] dev UART device struct \ref uart_cmsdk_dev_t + * \param[in] irq IRQ source to clean \ref uart_cmsdk_irq_t + * + * \note This function doesn't check if dev is NULL. + */ +void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev, + enum uart_cmsdk_irq_t irq); + +#ifdef __cplusplus +} +#endif +#endif /* __UART_CMSDK_DRV_H__ */ diff --git a/Arm/MPS3_AN524/lib/CMakeLists.txt b/Arm/MPS3_AN524/lib/CMakeLists.txt new file mode 100644 index 00000000..715f2ac4 --- /dev/null +++ b/Arm/MPS3_AN524/lib/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT License. + +# Define the CPU architecture for Threadx +set(THREADX_ARCH "cortex_m33") +set(THREADX_TOOLCHAIN "gnu") + +# Define ThreadX user configuration +set(TX_USER_FILE "${CMAKE_CURRENT_LIST_DIR}/threadx/tx_user.h" CACHE STRING "Enable TX user configuration") + +# Core libraries +add_subdirectory(${CORE_LIB_DIR}/threadx threadx) +#add_subdirectory(${CORE_LIB_DIR}/netxduo netxduo) +#add_subdirectory(${CORE_LIB_DIR}/jsmn jsmn) + +add_subdirectory(AN524) +add_subdirectory(tf-m) +add_subdirectory(threadx threadx-cmsis) diff --git a/Arm/MPS3_AN524/lib/tf-m/CMakeLists.txt b/Arm/MPS3_AN524/lib/tf-m/CMakeLists.txt new file mode 100644 index 00000000..321175cd --- /dev/null +++ b/Arm/MPS3_AN524/lib/tf-m/CMakeLists.txt @@ -0,0 +1,326 @@ +# Copyright (c) 2021 Linaro +# +# SPDX-License-Identifier: Apache-2.0 + +# List of all partitions supported by TF-M +# Name must match name in 'trusted-firmware-m/config/config_default.cmake' +set(TFM_VALID_PARTITIONS + TFM_PARTITION_PROTECTED_STORAGE + TFM_PARTITION_INTERNAL_TRUSTED_STORAGE + TFM_PARTITION_CRYPTO + TFM_PARTITION_INITIAL_ATTESTATION + TFM_PARTITION_PLATFORM + TFM_PARTITION_AUDIT_LOG + ) + +# Adds trusted-firmware-m as an external project. +# Also creates a target called 'tfm_api' +# which can be linked into the app. +# +# When called from a ThreadX module, the following input values can be provided +# to configure the TF-M build: +# +# BINARY_DIR: The location where the build outputs will be written +# BOARD: The string identifying the board target for TF-M (AN521, etc.) +# CMAKE_BUILD_TYPE: The TF-M build type to use, (Debug, Release, etc.) +# IPC: Build TFM IPC library. This library allows a non-secure application to +# interface to secure domain using IPC. +# ISOLATION_LEVEL: The TF-M isolation level to use +# REGRESSION: Boolean if TF-M build includes building the TF-M regression tests +# BL2: Boolean if the TF-M build uses MCUboot. Default: True +# ENABLED_PARTITIONS: List of TFM partitions to enable. +# +# Example usage: +# +# trusted_firmware_build(BINARY_DIR ${CMAKE_BINARY_DIR}/tfm +# BOARD ${TFM_TARGET_PLATFORM} +# CMAKE_BUILD_TYPE Release +# IPC +# ISOLATION_LEVEL 2 +# REGRESSION +# BL2 +# BUILD_PROFILE profile_small +# ENABLED_PARTITIONS TFM_PARTITION_PLATFORM TFM_PARTITION_CRYPTO) +function(trusted_firmware_build) + set(options IPC REGRESSION BL2) + set(oneValueArgs BINARY_DIR BOARD ISOLATION_LEVEL CMAKE_BUILD_TYPE BUILD_PROFILE + MCUBOOT_IMAGE_NUMBER KEY_FILE_S KEY_FILE_NS PSA_TEST_SUITE) + set(multiValueArgs ENABLED_PARTITIONS) + cmake_parse_arguments(TFM "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + foreach(partition ${TFM_VALID_PARTITIONS}) + list(FIND TFM_ENABLED_PARTITIONS ${partition} idx) + if (idx EQUAL -1) + set(val "OFF") + else() + set(val "ON") + endif() + list(APPEND TFM_PARTITIONS_ARGS -D${partition}=${val}) + endforeach() + + if(TFM_IPC) + set(TFM_IPC_ARG -DTFM_PSA_API=ON) + # PSA API awareness for the Non-Secure application + target_compile_definitions(mps3_524 PRIVATE "TFM_PSA_API") + endif() + + if(DEFINED TFM_ISOLATION_LEVEL) + set(TFM_ISOLATION_LEVEL_ARG -DTFM_ISOLATION_LEVEL=${TFM_ISOLATION_LEVEL}) + endif() + + if(TFM_REGRESSION) + set(TFM_REGRESSION_ARG -DTEST_NS=ON) + endif() + + if(DEFINED TFM_CMAKE_BUILD_TYPE) + set(TFM_CMAKE_BUILD_TYPE_ARG -DCMAKE_BUILD_TYPE=${TFM_CMAKE_BUILD_TYPE}) + else() + set(TFM_CMAKE_BUILD_TYPE_ARG -DCMAKE_BUILD_TYPE=RelWithDebInfo) + endif() + + if(DEFINED TFM_BUILD_PROFILE) + set(TFM_PROFILE_ARG -DTFM_PROFILE=${TFM_BUILD_PROFILE}) + endif() + + if(DEFINED TFM_MCUBOOT_IMAGE_NUMBER) + set(MCUBOOT_IMAGE_NUM_ARG -DMCUBOOT_IMAGE_NUMBER=${TFM_MCUBOOT_IMAGE_NUMBER}) + endif() + + if(TFM_PSA_TEST_SUITE) + set(PSA_TEST_ARG -DTEST_PSA_API=${TFM_PSA_TEST_SUITE}) + endif() + + set(TFM_GENERATED_INCLUDES ${TFM_BINARY_DIR}/generated/interface/include) + + if(TFM_BL2) + set(BL2_BIN_FILE ${TFM_BINARY_DIR}/bin/bl2.bin) + set(BL2_HEX_FILE ${TFM_BINARY_DIR}/bin/bl2.hex) + endif() + set(TFM_S_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s.bin) + set(TFM_S_HEX_FILE ${TFM_BINARY_DIR}/bin/tfm_s.hex) + set(TFM_NS_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_ns.bin) + set(TFM_NS_HEX_FILE ${TFM_BINARY_DIR}/bin/tfm_ns.hex) + set(TFM_S_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s_signed.bin) + set(TFM_NS_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_ns_signed.bin) + set(TFM_S_NS_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s_ns_signed.bin) + + if (TFM_PSA_TEST_SUITE) + set(PSA_TEST_VAL_FILE ${TFM_BINARY_DIR}/app/psa_api_tests/val/val_nspe.a) + set(PSA_TEST_PAL_FILE ${TFM_BINARY_DIR}/app/psa_api_tests/platform/pal_nspe.a) + set(COMBINE_DIR_STORAGE storage) + set(COMBINE_DIR_PROTECTED_STORAGE storage) + set(COMBINE_DIR_INTERNAL_TRUSTED_STORAGE storage) + set(COMBINE_DIR_CRYPTO crypto) + set(COMBINE_DIR_INITIAL_ATTESTATION initial_attestation) + set(PSA_TEST_COMBINE_FILE ${TFM_BINARY_DIR}/app/psa_api_tests/dev_apis/${COMBINE_DIR_${TFM_PSA_TEST_SUITE}}/test_combine.a) + endif() + + set(VENEERS_FILE ${TFM_BINARY_DIR}/install/interface/lib/s_veneers.o) + set(PSA_API_NS_PATH ${TFM_BINARY_DIR}/app/libtfm_api_ns.a) + + if (TFM_REGRESSION) + set(PSA_QCBOR_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/qcbor/libtfm_test_suite_qcbor_ns.a) + set(PSA_NS_CORE_TEST_PATH ${TFM_BINARY_DIR}/test/suites/core/libtfm_test_suite_core_ns.a) + set(PSA_NS_IPC_TEST_PATH ${TFM_BINARY_DIR}/test/suites/ipc/libtfm_test_suite_ipc_ns.a) + set(PSA_ATTESTATION_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/attestation/libtfm_test_suite_attestation_ns.a) + set(PSA_CRYPTO_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/crypto/libtfm_test_suite_crypto_ns.a) + set(PSA_PLATFORM_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/platform/libtfm_test_suite_platform_ns.a) + set(PSA_PS_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/ps/libtfm_test_suite_ps_ns.a) + set(PSA_ITS_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/its/libtfm_test_suite_its_ns.a) + set(PSA_T_COSE_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/test/suites/t_cose/libtfm_test_suite_t_cose_ns.a) + set(PSA_NS_REGRESSION_TEST_PATH ${TFM_BINARY_DIR}/app/libtfm_ns_integration_test.a) + set(PSA_QCBOR_TEST_PATH ${TFM_BINARY_DIR}/lib/ext/qcbor/libtfm_qcbor_test.a) + set(PSA_T_COSE_TEST_PATH ${TFM_BINARY_DIR}/lib/ext/t_cose/libtfm_t_cose_test.a) + set(PSA_QCBOR_PATH ${TFM_BINARY_DIR}/lib/ext/qcbor/libtfm_qcbor.a) + set(PSA_T_COSE_PATH ${TFM_BINARY_DIR}/lib/ext/t_cose/libtfm_t_cose.a) + endif() + + if(TFM_REGRESSION OR TFM_PSA_TEST_SUITE) + set(PSA_PLATFORM_NS_PATH ${TFM_BINARY_DIR}/platform/libplatform_ns.a) + endif() + + set(BUILD_BYPRODUCTS + ${VENEERS_FILE} + ${PSA_API_NS_PATH} + ${PSA_QCBOR_NS_REGRESSION_TEST_PATH} + ${PSA_NS_CORE_TEST_PATH} + ${PSA_NS_IPC_TEST_PATH} + ${PSA_ATTESTATION_NS_REGRESSION_TEST_PATH} + ${PSA_CRYPTO_NS_REGRESSION_TEST_PATH} + ${PSA_PLATFORM_NS_REGRESSION_TEST_PATH} + ${PSA_PS_NS_REGRESSION_TEST_PATH} + ${PSA_ITS_NS_REGRESSION_TEST_PATH} + ${PSA_T_COSE_NS_REGRESSION_TEST_PATH} + ${PSA_NS_REGRESSION_TEST_PATH} + ${PSA_QCBOR_TEST_PATH} + ${PSA_T_COSE_TEST_PATH} + ${PSA_PLATFORM_NS_PATH} + ${PSA_QCBOR_PATH} + ${PSA_T_COSE_PATH} + ${TFM_GENERATED_INCLUDES}/psa_manifest/sid.h + ${PSA_TEST_VAL_FILE} + ${PSA_TEST_PAL_FILE} + ${PSA_TEST_COMBINE_FILE} + ${BL2_BIN_FILE} + ${BL2_HEX_FILE} + ${TFM_S_BIN_FILE} + ${TFM_S_HEX_FILE} + ${TFM_NS_BIN_FILE} + ${TFM_NS_HEX_FILE} + ${TFM_S_SIGNED_BIN_FILE} + ${TFM_NS_SIGNED_BIN_FILE} + ${TFM_S_NS_SIGNED_BIN_FILE} + ) + + set(TFM_TOOLCHAIN_FILE "trusted-firmware-m/toolchain_GNUARM.cmake") + set(TFM_TOOLCHAIN_PREFIX "arm-none-eabi") + set(TFM_TOOLCHAIN_PATH ${ARM_TOOLCHAIN_PATH}) + + include(ExternalProject) + + set(TX_TFM_BASE_DIR ${GSG_BASE_DIR}/core/lib/tfm) + set(TX_TFM_TESTS_DIR ${GSG_BASE_DIR}/core/lib/tf-m-tests) + + ExternalProject_Add( + tfm + SOURCE_DIR ${TX_TFM_BASE_DIR} + BINARY_DIR ${TFM_BINARY_DIR} + CMAKE_ARGS -DTFM_TOOLCHAIN_FILE=${TX_TFM_BASE_DIR}/toolchain_GNUARM.cmake + -DTFM_PLATFORM=${TFM_BOARD} + -DCROSS_COMPILE=${TFM_TOOLCHAIN_PATH}/${TFM_TOOLCHAIN_PREFIX} + ${TFM_CMAKE_BUILD_TYPE_ARG} + -DBL2=${TFM_BL2} + ${TFM_IPC_ARG} + ${TFM_ISOLATION_LEVEL_ARG} + ${TFM_REGRESSION_ARG} + ${TFM_PROFILE_ARG} + ${MCUBOOT_IMAGE_NUM_ARG} + ${PSA_TEST_ARG} + -DTFM_TEST_REPO_PATH=${TX_TFM_TESTS_DIR} + ${TFM_PARTITIONS_ARGS} + BUILD_ALWAYS True + USES_TERMINAL_BUILD True + BUILD_BYPRODUCTS ${BUILD_BYPRODUCTS} + ) + + # Set BL2 (MCUboot) executable file paths as target properties on 'tfm' + # These files are produced by the TFM build system. + if(TFM_BL2) + set_target_properties(tfm PROPERTIES + BL2_BIN_FILE ${BL2_BIN_FILE} + BL2_HEX_FILE ${BL2_HEX_FILE} + ) + endif() + + # Set TFM S/NS executable file paths as target properties on 'tfm' + # These files are produced by the TFM build system. + # Note that the Nonsecure FW is replaced by the ThreadX app in regular ThreadX + # builds. + set_target_properties(tfm PROPERTIES + TFM_S_BIN_FILE ${TFM_S_BIN_FILE} # TFM Secure FW (unsigned) + TFM_S_HEX_FILE ${TFM_S_HEX_FILE} # TFM Secure FW (unsigned) + TFM_NS_BIN_FILE ${TFM_NS_BIN_FILE} # TFM Nonsecure FW (unsigned) + TFM_NS_HEX_FILE ${TFM_NS_HEX_FILE} # TFM Nonsecure FW (unsigned) + TFM_S_SIGNED_BIN_FILE ${TFM_S_SIGNED_BIN_FILE} # TFM Secure FW (signed) + TFM_NS_SIGNED_BIN_FILE ${TFM_NS_SIGNED_BIN_FILE} # TFM Nonsecure FW (signed) + TFM_S_NS_SIGNED_BIN_FILE ${TFM_S_NS_SIGNED_BIN_FILE} # Merged TFM Secure/Nonsecure FW (signed) + ) + + add_library(tfm_api INTERFACE + # ${TX_TFM_TESTS_DIR}/app/os_wrapper_cmsis_rtos_v2.c + ) + + target_include_directories(tfm_api + # PRIVATE + # ${TX_TFM_TESTS_DIR}/CMSIS/RTOS2/Include + INTERFACE + ${TX_TFM_BASE_DIR}/interface/include + ${TX_TFM_BASE_DIR}/../tf-m-tests/test/framework + # INTERFACE + ${TFM_GENERATED_INCLUDES} + ) + + target_link_libraries(tfm_api + INTERFACE + ${PSA_NS_CORE_TEST_PATH} + ${PSA_ATTESTATION_NS_REGRESSION_TEST_PATH} + ${PSA_CRYPTO_NS_REGRESSION_TEST_PATH} + ${PSA_NS_IPC_TEST_PATH} + ${PSA_ITS_NS_REGRESSION_TEST_PATH} + ${PSA_PLATFORM_NS_REGRESSION_TEST_PATH} + ${PSA_PS_NS_REGRESSION_TEST_PATH} + ${PSA_QCBOR_NS_REGRESSION_TEST_PATH} + ${PSA_T_COSE_NS_REGRESSION_TEST_PATH} + ${PSA_QCBOR_TEST_PATH} + ${PSA_T_COSE_TEST_PATH} + ${PSA_NS_REGRESSION_TEST_PATH} + ${PSA_QCBOR_PATH} + ${PSA_T_COSE_PATH} + ${PSA_TEST_VAL_FILE} + ${PSA_TEST_PAL_FILE} + ${PSA_TEST_COMBINE_FILE} + ${PSA_PLATFORM_NS_PATH} + ${PSA_API_NS_PATH} + ${VENEERS_FILE} + # $ + ) + + add_dependencies(tfm_api tfm) + + set(PREPROCESSED_FILE_S "${TFM_BINARY_DIR}/bl2/ext/mcuboot/CMakeFiles/signing_layout_s.dir/signing_layout_s_ns.o") + set(PREPROCESSED_FILE_NS ${PREPROCESSED_FILE_S}) + set(TFM_IMAGE_VERSION_S "1.3.0") + set(TFM_IMAGE_VERSION_NS "0.0.1") + set(HEADER_SIZE "0x400") + set(TFM_PUBLIC_KEY_FORMAT "full") + + function(tfm_combine OUT_ARG INPUT_S_FILE INPUT_NS_FILE OUTPUT_FILE) + set (${OUT_ARG} + ${PYTHON_EXECUTABLE} ${TX_TFM_BASE_DIR}/bl2/ext/mcuboot/scripts/assemble.py + --layout ${PREPROCESSED_FILE_S} + -s ${INPUT_S_FILE} + -n ${INPUT_NS_FILE} + -o ${OUTPUT_FILE} + PARENT_SCOPE + ) + endfunction() + + function(tfm_sign OUT_ARG PAD INPUT_FILE OUTPUT_FILE) + if(PAD) + set(pad_args --pad --pad-header) + else() + set(pad_args --pad-header) + endif() + set (${OUT_ARG} + ${PYTHON_EXECUTABLE} ${TX_TFM_BASE_DIR}/bl2/ext/mcuboot/scripts/wrapper/wrapper.py + --layout ${PREPROCESSED_FILE_S} + -k ${TFM_KEY_FILE_S} + --public-key-format ${TFM_PUBLIC_KEY_FORMAT} + --align 1 + -v ${TFM_IMAGE_VERSION_S} + ${pad_args} + -s auto + -H ${HEADER_SIZE} + ${INPUT_FILE} + ${OUTPUT_FILE} + PARENT_SCOPE) + endfunction() + + set(S_NS_SIGNED_FILE ${CMAKE_BINARY_DIR}/tfm_s_ns_signed.bin) + set(S_NS_FILE ${CMAKE_BINARY_DIR}/tfm_s_ns.bin) + + tfm_combine(combine_cmd $ ${CMAKE_BINARY_DIR}/app/mps3_524.bin ${S_NS_FILE}) + + tfm_sign(sign_cmd TRUE ${S_NS_FILE} ${S_NS_SIGNED_FILE}) + + if (TFM_BL2) + add_custom_command( + TARGET mps3_524 + POST_BUILD + COMMAND ${TFM_TOOLCHAIN_PATH}/${TFM_TOOLCHAIN_PREFIX}-objcopy -O binary ${CMAKE_BINARY_DIR}/app/mps3_524.elf ${CMAKE_BINARY_DIR}/app/mps3_524.bin + COMMAND ${combine_cmd} + COMMAND ${sign_cmd} + ) + endif() + +endfunction() diff --git a/Arm/MPS3_AN524/lib/threadx/CMakeLists.txt b/Arm/MPS3_AN524/lib/threadx/CMakeLists.txt new file mode 100644 index 00000000..9e597ca9 --- /dev/null +++ b/Arm/MPS3_AN524/lib/threadx/CMakeLists.txt @@ -0,0 +1,46 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT License. + +set(SOURCES + cmsis_rtos_v2.c +) + +set(TARGET threadx-cmsis) + +set(TX_CMSIS_OS2_NUM_SEMAPHORES + "1" + CACHE STRING + "The CMSIS OS2 port relies on static allocations of semaphores. This configures + the size of that static allocation in number of semaphores." +) + +set(TX_CMSIS_OS2_NUM_THREADS + "2" + CACHE STRING + "The CMSIS OS2 port relies on static allocations of threads. This configures + the size of that static allocation in number of threads." +) + +set(TX_CMSIS_OS2_THREAD_STACK_SIZE + "768" + CACHE STRING + "The CMSIS OS2 port relies on static allocations of thread stacks. This + configures the size of each thread's stack in bytes." +) + +add_compile_definitions(TX_CMSIS_OS2_NUM_SEMAPHORES=${TX_CMSIS_OS2_NUM_SEMAPHORES}) +add_compile_definitions(TX_CMSIS_OS2_NUM_THREADS=${TX_CMSIS_OS2_NUM_THREADS}) +add_compile_definitions(TX_CMSIS_OS2_THREAD_STACK_SIZE=${TX_CMSIS_OS2_THREAD_STACK_SIZE}) + +add_library(${TARGET} OBJECT + ${SOURCES} +) + +target_include_directories(${TARGET} + INTERFACE + inc +) + +target_link_libraries(${TARGET} + threadx +) diff --git a/Arm/MPS3_AN524/lib/threadx/cmsis_rtos_v2.c b/Arm/MPS3_AN524/lib/threadx/cmsis_rtos_v2.c new file mode 100644 index 00000000..162d8865 --- /dev/null +++ b/Arm/MPS3_AN524/lib/threadx/cmsis_rtos_v2.c @@ -0,0 +1,223 @@ +#include +#include +#include +#include "inc/tx_cmsis_os2.h" +#include "../../../../core/lib/tf-m-tests/CMSIS/RTOS2/Include/cmsis_os2.h" + +#ifndef TX_CMSIS_OS2_NUM_SEMAPHORES +#define TX_CMSIS_OS2_NUM_SEMAPHORES (1) +#endif +TX_BLOCK_POOL semaphore_pool = {0}; +uint8_t semaphore_blocks[ + TX_CMSIS_OS2_NUM_SEMAPHORES * (sizeof(TX_SEMAPHORE) + sizeof(void *)) +] = {0}; + +#ifndef TX_CMSIS_OS2_NUM_THREADS +#define TX_CMSIS_OS2_NUM_THREADS (2) +#endif +#ifndef TX_CMSIS_OS2_THREAD_STACK_SIZE +#define TX_CMSIS_OS2_THREAD_STACK_SIZE (512 + 256) +#endif +TX_BLOCK_POOL thread_pool = {0}; +uint8_t thread_blocks[ + TX_CMSIS_OS2_NUM_THREADS * (sizeof(TX_THREAD) + sizeof(void *)) +] = {0}; + +TX_BYTE_POOL thread_stack_pool = {0}; +uint8_t thread_stack_blocks[ + TX_CMSIS_OS2_NUM_THREADS * + (TX_CMSIS_OS2_THREAD_STACK_SIZE + sizeof(void *)) +] = {0}; + +void init_cmsis_os2(void) { + tx_block_pool_create( + &semaphore_pool, /* pool ptr */ + "CMSIS OS2 Semaphore Pool", /* name */ + sizeof(TX_SEMAPHORE), /* block size */ + &semaphore_blocks[0], /* pool start */ + sizeof(semaphore_blocks) /* pool size */ + ); + tx_block_pool_create( + &thread_pool, /* pool ptr */ + "CMSIS OS2 Thread Pool", /* name */ + sizeof(TX_THREAD), /* block size */ + &thread_blocks[0], /* pool start */ + sizeof(thread_blocks) /* pool size */ + ); + tx_byte_pool_create( + &thread_stack_pool, /* pool ptr */ + "CMSIS OS2 Thread Stack Pool", /* name */ + &thread_stack_blocks[0], /* pool start */ + sizeof(thread_stack_blocks) /* pool size */ + ); +} + +osMutexId_t osMutexNew(const osMutexAttr_t *attr) { + return NULL; +} + +osSemaphoreId_t osSemaphoreNew ( + uint32_t max_count, + uint32_t initial_count, + const osSemaphoreAttr_t *attr +) { + TX_SEMAPHORE *new_semaphore = (TX_SEMAPHORE*) attr->cb_mem; + if (new_semaphore == NULL) { + tx_block_allocate( + &semaphore_pool, + (VOID **) &new_semaphore, + TX_WAIT_FOREVER + ); + } + tx_semaphore_create(new_semaphore, (CHAR *) attr->name, initial_count); + return (osSemaphoreId_t) new_semaphore; +} + +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) { + CHAR* name = NULL; + tx_semaphore_info_get( + (TX_SEMAPHORE *) semaphore_id, + &name, /* name */ + NULL, /* current_value */ + NULL, /* first_suspended */ + NULL, /* suspend_count */ + NULL /* next_semaphore */ + ); + return name; +} + +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + ULONG current_count = 0; + tx_semaphore_info_get( + (TX_SEMAPHORE *) semaphore_id, + NULL, /* name */ + ¤t_count, /* current_value */ + NULL, /* first_suspended */ + NULL, /* suspend_count */ + NULL /* next_semaphore */ + ); + return current_count; +} + +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + return tx_semaphore_get((TX_SEMAPHORE *) semaphore_id, (ULONG) timeout); +} + +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + return tx_semaphore_put((TX_SEMAPHORE *) semaphore_id); +} + +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + tx_semaphore_delete((TX_SEMAPHORE *) semaphore_id); + return tx_block_release((TX_SEMAPHORE *) semaphore_id); +} + +osThreadId_t osThreadGetId (void) { + return (osThreadId_t) tx_thread_identify(); +} + +void entry_exit_notify(TX_THREAD * thread, UINT entry_exit) { + if (entry_exit == TX_THREAD_EXIT) { + tx_thread_delete(thread); + tx_byte_release(thread->tx_thread_stack_start); + tx_block_release(thread); + } +} + +osThreadId_t osThreadNew ( + osThreadFunc_t func, + void *argument, + const osThreadAttr_t *attr +) { + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wcast-function-type" + VOID (*localfunc)(ULONG) = (VOID (*)(ULONG)) func; + #pragma GCC diagnostic pop + TX_THREAD *new_thread = (TX_THREAD*) attr->cb_mem; + if (new_thread == NULL) { + tx_block_allocate( + &thread_pool, + (VOID **) &new_thread, + TX_WAIT_FOREVER + ); + } + VOID *stack_mem = (VOID *) attr->stack_mem; + if (stack_mem == NULL) { + tx_byte_allocate( + &thread_stack_pool, + (VOID **) &stack_mem, + attr->stack_size, + TX_WAIT_FOREVER + ); + } + tx_thread_create( + new_thread, /* thread ptr */ + (CHAR *) attr->name, /* name */ + localfunc, /* entry function */ + (ULONG) argument, /* entry intput */ + stack_mem, /* stack start */ + (ULONG) attr->stack_size, /* stack size */ + (UINT) attr->priority, /* priority */ + 0, /* preempt threshold */ + TX_NO_TIME_SLICE, /* time slice */ + TX_DONT_START /* auto start */ + ); + tx_thread_entry_exit_notify(new_thread, &entry_exit_notify); + tx_thread_resume(new_thread); + return (osThreadId_t) new_thread; +} + +const char *osThreadGetName (osThreadId_t thread_id) { + char* name = NULL; + tx_thread_info_get( + (TX_THREAD*)thread_id, + &name, /* name */ + NULL, /* state */ + NULL, /* run_count */ + NULL, /* priority */ + NULL, /* preempt_threshold */ + NULL, /* time_slice */ + NULL, /* next_thread */ + NULL /* next_suspended_thread */ + ); + return (const char *) name; +} + +osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + UINT priority = 0; + tx_thread_info_get( + (TX_THREAD*)thread_id, + NULL, /* name */ + NULL, /* state */ + NULL, /* run_count */ + &priority, /* priority */ + NULL, /* preempt_threshold */ + NULL, /* time_slice */ + NULL, /* next_thread */ + NULL /* next_suspended_thread */ + ); + return priority; +} + +osThreadState_t osThreadGetState (osThreadId_t thread_id) { + UINT state = 0; + tx_thread_info_get( + (TX_THREAD*)thread_id, + NULL, /* name */ + &state, /* state */ + NULL, /* run_count */ + NULL, /* priority */ + NULL, /* preempt_threshold */ + NULL, /* time_slice */ + NULL, /* next_thread */ + NULL /* next_suspended_thread */ + ); + return (osThreadState_t) state; +} + +__NO_RETURN void osThreadExit (void) { + TX_THREAD *thread_id = tx_thread_identify(); + tx_thread_terminate(thread_id); + /* Ideally, this is never hit */ + while (true) ; +} diff --git a/Arm/MPS3_AN524/lib/threadx/inc/tx_cmsis_os2.h b/Arm/MPS3_AN524/lib/threadx/inc/tx_cmsis_os2.h new file mode 100644 index 00000000..7c419c5f --- /dev/null +++ b/Arm/MPS3_AN524/lib/threadx/inc/tx_cmsis_os2.h @@ -0,0 +1,6 @@ +#ifndef __TX_CMSIS_OS2_H_ +#define __TX_CMSIS_OS2_H_ + +void init_cmsis_os2(void); + +#endif // __TX_CMSIS_OS2_H_ diff --git a/Arm/MPS3_AN524/lib/threadx/tx_user.h b/Arm/MPS3_AN524/lib/threadx/tx_user.h new file mode 100644 index 00000000..db924875 --- /dev/null +++ b/Arm/MPS3_AN524/lib/threadx/tx_user.h @@ -0,0 +1,258 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ +/* 6.0 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* */ +/**************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_ENABLE_FPU_SUPPORT + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +/* +#define TX_REACTIVATE_INLINE +*/ + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +/* +#define TX_DISABLE_REDUNDANT_CLEARING +*/ + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_NOTIFY_CALLBACKS +*/ + + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif + diff --git a/Arm/MPS3_AN524/pyocd_user.py b/Arm/MPS3_AN524/pyocd_user.py new file mode 100644 index 00000000..fb86689f --- /dev/null +++ b/Arm/MPS3_AN524/pyocd_user.py @@ -0,0 +1,8 @@ +RESET_MASK = 0x50021104 +RESET_MASK_SYSRSTREQ0_EN = 1 << 4 + +def will_reset(core, reset_type): + LOG.info("Enabling SYSRSTREQ0_EN") + reset_mask = core.read32(RESET_MASK) + reset_mask |= RESET_MASK_SYSRSTREQ0_EN + core.write32(RESET_MASK, reset_mask) diff --git a/Arm/MPS3_AN524/readme.md b/Arm/MPS3_AN524/readme.md new file mode 100644 index 00000000..97075d09 --- /dev/null +++ b/Arm/MPS3_AN524/readme.md @@ -0,0 +1,204 @@ +--- +page_type: sample +description: Using the Arm MPS3 AN524 with Azure RTOS +languages: +- c +products: +- azure-rtos +--- + +# Getting started with the Arm MPS3 FGPA board and the AN524 + +**Total completion time**: 30 minutes + +In this tutorial you use Azure RTOS on the AN524, which is an Arm Cortex-M33 +image that can be run on the MPS3 FPGA prototyping board or in QEMU. + +## Prerequisites + +* [Git](https://git-scm.com/downloads) for cloning the repository +* Hardware or [QEMU](#using-qemu) + + > * The [Arm MPS3 FPGA Prototyping Board](https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3) (MPS3) + > * The [AN524 SSE-200 FPGA image for MPS3](https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/download-fpga-images) +* To use QEMU, `srec_cat` must be installed to merge TF-M and Azure RTOS + example application. You can install it via `$ sudo apt-get install srecord` + on Ubuntu or `$ brew install srecord` on OS X. +* We've automated the process of [updating application image onto the Arm MPS3 + FPGA Prototyping Board](#updating-application-image). If you wish to use this + , then `pyserial` python module should be installed: + > * pip3 install pyserial + +## System Setup + +### FTDI VCP Drivers + +Your OS may not properly enumerate the four serial ports provided by an FTDI +USB serial chip on the MPS3 board. If they don't appear, you must install the +latest VCP driver and restart your system: +https://ftdichip.com/drivers/vcp-drivers/ + +You should see five distinct serial ports (one for the LPC1768 debug MCU, and +four from the FTDI chip), where the first two ports from the FTDI chip are of +relevance to this demo: + +- `tty.usbserial-xxxxxxxxA` = The MPS3 bootloader +- `tty.usbserial-xxxxxxxxB` = Azure (etc.) serial output + +### AN524 PyOCD Support + +If you wish to debug, MPS3 AN524 support is available in pyocd via a CMSIS +pack, which can be installed as follows: + +```bash +$ pyocd pack -u +$ pyocd pack -i SSE-200-MPS3 +$ pyocd list --targets | grep MPS3 +``` + +You can then start a GDB debug session via: + +```bash +$ pyocd gdbserver --target=sse-200-mps3 +``` + +Then in another terminal: + +```bash +$ arm-none-eabi-gdb-py -s build/app/mps3_524.elf \ + -ex "target remote tcp:localhost:3333" +(gdb) monitor reset halt +(gdb) break main +(gdb) continue +``` + +> Please note that there is a known issue with resetting the AN524 with the + debugger (https://github.com/pyocd/pyOCD/issues/1078). The `pyocd_user.py` + script in this folder (`Arm/MPS3_AN524`) provides a workaround for this + issue, and pyocd should be run from the folder where this script is located. + +## Building the Sample + +The sample requires both a GCC cross compiler for armv7m, usually called `arm-none-eabi-gcc`, +and the `srec_cat` utility, which is commonly part of the `srecord` packace on linux +distributions. Build the sample with the provided `rebuild.sh` tool. + +```bash +$ cd Arm/MPS3_AN524 +$ tools/rebuild.sh +``` + +### Configuring the sample + +There are a few configuration options available to, for example, change the +secure partitions used by TF-M. These options are defined and documented in +`Arm/MPS3_AN524/app/config.cmake`. You may pass your own overriding options to +cmake by defining the `APP_CONFIG` variable to a path to a file that sets these +options. + +The ThreadX CMSIS RTOS2 interface statically allocates threads, thread stacks +and semaphores. The size of these allocations may also be configured. +Configuration options for these are defined and documented in +`Arm/MPS3_AN524/lib/threadx/CMmakeLists.txt`. + +### Running TF-M NS regression tests +TF-M NS regression tests config option `TFM_REGRESSION` is documented in +`Arm/MPS3_AN524/app/config.cmake` and is disabled by default. To run TF-M NS +regression tests, set the config option to `ON` and rebuild the application. +Then run it either on [QEMU](#using-qemu) or [hardware](#updating-application-image) + +### Running PSA Arch tests +PSA arch tests config option `TFM_PSA_TEST` is documented in +`Arm/MPS3_AN524/app/config.cmake` and is disabled by default. To run PSA arch +tests, set the config option to any of `CRYPTO`|`PROTECTED_STORAGE`| +`INTERNAL_TRUSTED_STORAGE`|`STORAGE`|`INITIAL_ATTESTATION`. +Then run it either on [QEMU](#using-qemu) or [hardware](#updating-application-image) + +*Note* +The TF-M version 1.3 and PSA architecture crypto test suite version 1.1 causes +resets on QEMU. However, the crypto test suite completes without any issues on +Arm MPS3 FPGA board. Other test suites can be run either on QEMU or Arm MPS3 +FPGA board. + +Following summary will be printed at the end of crypto tests: + +```bash +************ Crypto Suite Report ********** +TOTAL TESTS : 63 +TOTAL PASSED : 39 +TOTAL SIM ERROR : 0 +TOTAL FAILED : 17 +TOTAL SKIPPED : 7 +****************************************** +``` + +## Updating application image +> This has only been tested on OS X, some modifications might be needed to make + `Arm/MPS3_AN524/tools/flash.py` to work in Windows/Linux environments. + +The python script `Arm/MPS3_AN524/tools/flash.py` automates steps needed to +update an application image onto the Arm MPS3 FPGA Prototyping Board. if you +wish to use this, then add `-f` command line option while invoking `rebuild.sh`. +If `-f` option is used then FPGA MCC serial port must be provided using `-p` +option. + +```bash +$ cd Arm/MPS3_AN524 +$ tools/rebuild.sh -f -p /dev/tty.usbserial-14543100 +``` + +## Using QEMU +QEMU can be used to emulate MPS3 FPGA board with AN524 and run Azure RTOS +example application. However, AN524 memory remap feature is required +successfully run the application. This feature was added to QEMU after current +6.0.0 release. Therefore we need to [build QEMU from source](#building-qemu). + +After build is successful and path to QEMU executable `qemu-system-arm` is +added to `PATH` environment variable, QEMU can be started from build script by +using `-q` option. + +```bash +$ cd Arm/MPS3_AN524 +$ tools/rebuild.sh -q +``` + +### Building QEMU +Follow the steps below to build QEMU from source: + +```bash +cd /path/for/qemu/source +git clone https://github.com/qemu/qemu.git + +mkdir build && cd build + +../configure --disable-docs --disable-sdl --disable-debug-info --disable-cap-ng \ + --disable-libnfs --disable-libusb --disable-libiscsi --disable-usb-redir \ + --disable-linux-aio --disable-guest-agent --disable-libssh --disable-vnc-png \ + --disable-seccomp --disable-tpm --disable-numa --disable-glusterfs \ + --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses \ + --disable-iconv --target-list="aarch64-softmmu arm-softmmu" + +make +``` + +Once build completes successfully, run the following command to check supported machines. + +```bash +./qemu-system-arm -M help +``` +It should contain the following machines: +```bash +mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3 +mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4 +mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7 +mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33 +mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3 +mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33 +mps3-an524 ARM MPS3 with AN524 FPGA image for dual Cortex-M33 +mps3-an547 ARM MPS3 with AN547 FPGA image for Cortex-M55 +musca-a ARM Musca-A board (dual Cortex-M33) +musca-b1 ARM Musca-B1 board (dual Cortex-M33) +``` + +Make sure that path to QEMU executable `qemu-system-arm` is added to `PATH` +environment variable. diff --git a/Arm/MPS3_AN524/tools/flash.py b/Arm/MPS3_AN524/tools/flash.py new file mode 100644 index 00000000..fc61b33a --- /dev/null +++ b/Arm/MPS3_AN524/tools/flash.py @@ -0,0 +1,60 @@ +# Copyright (c) 2021 Linaro Limited. + +import pathlib +import serial +import shutil +import sys +import time + +# Serial baudrate +SERIAL_BAUDRATE = 115200 + +# Path to image files +BL_FILE = pathlib.Path(__file__).parent.absolute().parent / "build" / "tfm" / "bin" / "bl2.bin" +S_NS_IMAGE = pathlib.Path(__file__).parent.absolute().parent / "build" / "tfm_s_ns_signed.bin" +# Path where image file should be copied +BIN_DEST_PATH = pathlib.Path("/Volumes/V2M-MPS3/SOFTWARE") + +def initiate_reboot(port): + try: + serial_port = serial.Serial(port, SERIAL_BAUDRATE, exclusive=False) + except serial.SerialException: + print("ERROR: Unable to update application image onto FPGA board") + print(f"ERROR: Unable to open serial port {port}") + sys.exit(1) + else: + # Send reboot command to mcc terminal + # Wring the string `reboot\n` is causing data loss. Therefore send + # individual characters and introduce 100ms delay between each + # character. + serial_port.write(b'r') + time.sleep(0.1) + serial_port.write(b'e') + time.sleep(0.1) + serial_port.write(b'b') + time.sleep(0.1) + serial_port.write(b'o') + time.sleep(0.1) + serial_port.write(b'o') + time.sleep(0.1) + serial_port.write(b't') + time.sleep(0.1) + serial_port.write(b'\n') + +def copy_application_image(): + try: + shutil.copy2(BL_FILE, BIN_DEST_PATH, follow_symlinks=False) + time.sleep(0.1) + + shutil.copy2(S_NS_IMAGE, BIN_DEST_PATH / "tfm_fpga.bin", follow_symlinks=False) + time.sleep(1) + except OSError as e: + print("ERROR: Unable to update application image onto FPGA board") + print(f"ERROR: {e.strerror} : {e.filename}") + sys.exit(1) + +if __name__ == '__main__': + # Copy application image onto USB drive + copy_application_image() + # Initiate reboot + initiate_reboot(sys.argv[1]) diff --git a/Arm/MPS3_AN524/tools/rebuild.sh b/Arm/MPS3_AN524/tools/rebuild.sh new file mode 100755 index 00000000..af7001df --- /dev/null +++ b/Arm/MPS3_AN524/tools/rebuild.sh @@ -0,0 +1,97 @@ +# Copyright (c) 2021 Linaro Limited. +# Licensed under the MIT License. + +#!/bin/bash + +# Check if user wishes to auto update application image onto connected board +# after successful build. +HELP_STR=" +Usage: rebuild.sh [-h] [-q] [-f] [-p=serial port] \n \ + Build Azure RTOS application image \n \ + Optional: \n \ + \t-h : Show this message \n \ + \t-c : Clean the build directory before building \n \ + \t-q : Use QEMU for running application \n \ + \t-f : Update generated image onto connected board \n \ + \t-p=serial port : MCC Serial port name, mandatory with -f option +" + +flash_option=false +while getopts "hcqfp:" option; do + case ${option} in + f ) + flash_option=true + ;; + p ) + if [ "$flash_option" = false ]; then + echo "ERROR: -p option can only be used with -f option" + exit 1 + fi + serial_port=$OPTARG + ;; + q ) + use_qemu=true + ;; + c ) + clean_first=true + ;; + h ) + echo $HELP_STR + exit 1 + ;; + \? ) + echo $HELP_STR + exit 1 + esac +done +# shift $((OPTIND -1)) +if [ "$flash_option" = true ] && [ "$serial_port" = "" ]; then + echo "ERROR: -p option is mandatory when -f option is used" + exit 1 +fi + +# Use paths relative to this script's location +SCRIPT=$(realpath "$0") +SCRIPTDIR=$(dirname "$SCRIPT") +BASEDIR=$(dirname "$SCRIPTDIR") +BUILDTYPE=Debug + +# echo $BASEDIR + +# If you want to build into a different directory, change this variable +BUILDDIR="$BASEDIR/build" + +# Ensure the bulid directory exists +mkdir -p $BUILDDIR +# When a clean build is specified, wipe away all chance at state +if [ "$clean_first" = true ]; then + rm -rf $BUILDDIR/* +fi + +# Generate the build system using Ninja +cmake -B"$BUILDDIR" -GNinja -DCMAKE_BUILD_TYPE=$BUILDTYPE $BASEDIR + +# And then do the build +cmake --build $BUILDDIR + +# Check if build succeeded and running on QEMU is requested +if [ $? -eq 0 ] && [ "$use_qemu" = true ]; then + # Check if srec_cat is installed + if ! command -v srec_cat &> /dev/null; then + echo "srec_cat is required to merge TF-M and Azure RTOS example. Install it via \n \ +$ sudo apt-get install srecord on Ubuntu or \n \ +$ brew install srecord on OS X." + + exit 1 + fi + # Before we launch QEMU, we need to merge TF-M and Azure RTOS example + # application images + srec_cat $BUILDDIR/tfm/bin/bl2.bin -Binary -offset 0x10000000 $BUILDDIR/tfm_s_ns_signed.bin -Binary -offset 0x10040000 -o $BUILDDIR/tfm_full.hex -Intel + echo "Starting QEMU" + qemu-system-arm -M mps3-an524 -M remap=QSPI -device loader,file=$BUILDDIR/tfm_full.hex -serial stdio +fi + +# Check if build succeeded +if [ $? -eq 0 ] && [ "$flash_option" = true ]; then + python3 $SCRIPTDIR/flash.py $serial_port +fi diff --git a/cmake/arm-gcc-cortex-m33.cmake b/cmake/arm-gcc-cortex-m33.cmake new file mode 100644 index 00000000..2f805fe7 --- /dev/null +++ b/cmake/arm-gcc-cortex-m33.cmake @@ -0,0 +1,13 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT License. +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR cortex-m33) + +set(THREADX_ARCH "cortex_m33") +set(THREADX_TOOLCHAIN "gnu") + +set(MCPU_FLAGS "-mthumb -mcpu=cortex-m33+nodsp+nofp") +set(VFP_FLAGS "-mfloat-abi=softfp") +set(SPEC_FLAGS "--specs=nosys.specs") + +include(${CMAKE_CURRENT_LIST_DIR}/arm-gcc-cortex-toolchain.cmake) diff --git a/core/lib/tf-m-tests b/core/lib/tf-m-tests new file mode 160000 index 00000000..b0c06b46 --- /dev/null +++ b/core/lib/tf-m-tests @@ -0,0 +1 @@ +Subproject commit b0c06b46b8a32d73794637e2a034a9cfbb4e883b diff --git a/core/lib/tfm b/core/lib/tfm new file mode 160000 index 00000000..442bc936 --- /dev/null +++ b/core/lib/tfm @@ -0,0 +1 @@ +Subproject commit 442bc9361462cd8472aadff1f4c74621ef134af9 diff --git a/core/lib/threadx b/core/lib/threadx index a891c3f9..c5474e6b 160000 --- a/core/lib/threadx +++ b/core/lib/threadx @@ -1 +1 @@ -Subproject commit a891c3f9033b80bad838ab3e96e83e049981e175 +Subproject commit c5474e6b1f5d8b15e61c2dfa251aab813d9a9d3a