From c1a63ed8f08c3964112e3c415812bf91da88636a Mon Sep 17 00:00:00 2001 From: James Newling Date: Mon, 9 Dec 2024 01:01:10 -0800 Subject: [PATCH] Bump aie-rt (#970) This PR moves aie-rt forward about 5 months. Our on-the-fly string matching fix in iree_aie_rt is dropped because https://github.com/Xilinx/aie-rt/issues/4 is fixed. The other changes appear minor. --- cmake/iree_aie_rt.cmake | 196 ------------------ .../aie_runtime/iree_aie_runtime.cc | 6 +- .../aie_runtime/iree_aie_runtime.h | 7 +- third_party/aie-rt | 2 +- 4 files changed, 11 insertions(+), 200 deletions(-) diff --git a/cmake/iree_aie_rt.cmake b/cmake/iree_aie_rt.cmake index 161bd03b5..7762c6508 100644 --- a/cmake/iree_aie_rt.cmake +++ b/cmake/iree_aie_rt.cmake @@ -46,202 +46,6 @@ include(${_aie_rt_source_dir}/fal/cmake/collect.cmake) set(XAIENGINE_BUILD_SHARED OFF CACHE BOOL "" FORCE) add_subdirectory(${_aie_rt_source_dir}/driver/src iree_aie_runtime) -# https://github.com/Xilinx/aie-rt/issues/4 -set(_incorrect_port_map " -static const XAie_StrmSwPortMap AieMlMemTileStrmSwSlavePortMap[] = -{ - { - /* PhyPort 0 */ - .PortType = DMA, - .PortNum = 0, - }, - { - /* PhyPort 1 */ - .PortType = DMA, - .PortNum = 1, - }, - { - /* PhyPort 2 */ - .PortType = DMA, - .PortNum = 2, - }, - { - /* PhyPort 3 */ - .PortType = DMA, - .PortNum = 3, - }, - { - /* PhyPort 4 */ - .PortType = DMA, - .PortNum = 4, - }, - { - /* PhyPort 5 */ - .PortType = DMA, - .PortNum = 5, - }, - { - /* PhyPort 6 */ - .PortType = CTRL, - .PortNum = 0, - }, - { - /* PhyPort 7 */ - .PortType = SOUTH, - .PortNum = 0, - }, - { - /* PhyPort 8 */ - .PortType = SOUTH, - .PortNum = 1, - }, - { - /* PhyPort 9 */ - .PortType = SOUTH, - .PortNum = 2, - }, - { - /* PhyPort 10 */ - .PortType = SOUTH, - .PortNum = 3, - }, - { - /* PhyPort 11 */ - .PortType = NORTH, - .PortNum = 0, - }, - { - /* PhyPort 12 */ - .PortType = NORTH, - .PortNum = 1, - }, - { - /* PhyPort 13 */ - .PortType = NORTH, - .PortNum = 2, - }, - { - /* PhyPort 14 */ - .PortType = NORTH, - .PortNum = 3, - }, - { - /* PhyPort 15 */ - .PortType = NORTH, - .PortNum = 4, - }, - { - /* PhyPort 16 */ - .PortType = NORTH, - .PortNum = 5, - }, - { - /* PhyPort 17 */ - .PortType = TRACE, - .PortNum = 0, - }, -}; -") - -set(_correct_port_map " -static const XAie_StrmSwPortMap AieMlMemTileStrmSwSlavePortMap[] = { - { - /* PhyPort 0 */ - .PortType = DMA, - .PortNum = 0, - }, - { - /* PhyPort 1 */ - .PortType = DMA, - .PortNum = 1, - }, - { - /* PhyPort 2 */ - .PortType = DMA, - .PortNum = 2, - }, - { - /* PhyPort 3 */ - .PortType = DMA, - .PortNum = 3, - }, - { - /* PhyPort 4 */ - .PortType = DMA, - .PortNum = 4, - }, - { - /* PhyPort 5 */ - .PortType = DMA, - .PortNum = 5, - }, - { - /* PhyPort 6 */ - .PortType = CTRL, - .PortNum = 0, - }, - { - /* PhyPort 7 */ - .PortType = SOUTH, - .PortNum = 0, - }, - { - /* PhyPort 8 */ - .PortType = SOUTH, - .PortNum = 1, - }, - { - /* PhyPort 9 */ - .PortType = SOUTH, - .PortNum = 2, - }, - { - /* PhyPort 10 */ - .PortType = SOUTH, - .PortNum = 3, - }, - { - /* PhyPort 11 */ - .PortType = SOUTH, - .PortNum = 4, - }, - { - /* PhyPort 12 */ - .PortType = SOUTH, - .PortNum = 5, - }, - { - /* PhyPort 13 */ - .PortType = NORTH, - .PortNum = 0, - }, - { - /* PhyPort 14 */ - .PortType = NORTH, - .PortNum = 1, - }, - { - /* PhyPort 15 */ - .PortType = NORTH, - .PortNum = 2, - }, - { - /* PhyPort 16 */ - .PortType = NORTH, - .PortNum = 3, - }, - { - /* PhyPort 17 */ - .PortType = TRACE, - .PortNum = 0, - }, -}; -") - -replace_string_in_file( - ${_aie_rt_source_dir}/driver/src/global/xaie2ipugbl_reginit.c - "${_incorrect_port_map}" "${_correct_port_map}") - get_target_property(_aie_runtime_compile_options xaiengine COMPILE_OPTIONS) list(REMOVE_ITEM _aie_runtime_compile_options -D__AIEBAREMETAL__) diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc index a29fe0898..58d068743 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc +++ b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc @@ -881,9 +881,13 @@ std::string to_string(const XAie_TxnOpcode &value) { STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_BLOCKSET) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKWRITE) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKPOLL) + STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_NOOP) + STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_PREEMPT) + STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKPOLL_BUSY) + STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_LOADPDI) + STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_LOAD_PM_START) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_CONFIG_SHIMDMA_BD) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_CONFIG_SHIMDMA_DMABUF_BD) - // STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_BEGIN) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_TCT) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_DDR_PATCH) STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_READ_REGS) diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h index 0a9ddf4b5..278a208bc 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h +++ b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h @@ -8,8 +8,6 @@ #define IREE_AIE_RUNTIME_H #include -#include -#include #include #include @@ -166,6 +164,11 @@ enum class XAie_TxnOpcode : uint8_t { XAIE_IO_BLOCKSET, XAIE_IO_MASKWRITE, XAIE_IO_MASKPOLL, + XAIE_IO_NOOP, + XAIE_IO_PREEMPT, + XAIE_IO_MASKPOLL_BUSY, + XAIE_IO_LOADPDI, + XAIE_IO_LOAD_PM_START, XAIE_CONFIG_SHIMDMA_BD, XAIE_CONFIG_SHIMDMA_DMABUF_BD, XAIE_IO_CUSTOM_OP_BEGIN = ::XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_BEGIN, diff --git a/third_party/aie-rt b/third_party/aie-rt index e2aca220d..1470f6c1d 160000 --- a/third_party/aie-rt +++ b/third_party/aie-rt @@ -1 +1 @@ -Subproject commit e2aca220d75965e16912fa1d6b593bb2c22200cb +Subproject commit 1470f6c1d0e765a73c741ad51bc761515d74457e