diff --git a/Cargo.toml b/Cargo.toml
index 1111039..b66cb9d 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -29,7 +29,7 @@ max-cpu-frequency = []
 
 [profile.release]
 codegen-units = 1
-debug = false
+debug = true
 debug-assertions = false
 incremental = false
 lto = "fat"
diff --git a/ld/esp32p4.x b/ld/esp32p4.x
index 04762eb..f077f87 100644
--- a/ld/esp32p4.x
+++ b/ld/esp32p4.x
@@ -1,7 +1,7 @@
 
 MEMORY {
-    /* Start 64k into the RAM region */
-    IRAM : ORIGIN = 0x4FF10000, LENGTH = 0x10000
+    /* Start 256k into the uncached RAM region */
+    IRAM : ORIGIN = 0x8FF50000, LENGTH = 0x10000
 }
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
diff --git a/src/main.rs b/src/main.rs
index adcc39c..03e44ce 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -33,7 +33,7 @@ const _: [u8; 43776] = [0; core::mem::size_of::<Decompressor>()];
 // ESP32-C6  | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000    | 0x4086_0000
 // ESP32-C61 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! ROM data use starts at 0x4083EA70, so let's use H2's memory layout
 // ESP32-H2  | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! has smaller RAM, only reserve 32K for data
-// ESP32-P4  | 0x4FF1_0000 | 0x4FF1_0000 | 0x4FF6_0000 | 0x4FF7_0000    | 0x4FFC_0000
+// ESP32-P4  | 0x8FF4_0020 | 0x8FF4_0020 | 0x8FF6_0000 | 0x8FF7_0000    | 0x8FFC_0000 !! Uncached region
 
 // "State" base address
 #[cfg(feature = "esp32")]
@@ -55,7 +55,7 @@ const STATE_ADDR: usize = 0x4082_0000;
 #[cfg(feature = "esp32h2")]
 const STATE_ADDR: usize = 0x4082_0000;
 #[cfg(feature = "esp32p4")]
-const STATE_ADDR: usize = 0x4FF6_0000;
+const STATE_ADDR: usize = 0x8FF6_0000;
 
 // End of target memory configuration