From 45a139a711d9a0456d1df191055f9bb013d91cf6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 11:39:12 +0100 Subject: [PATCH 01/13] Move Cpu to a new module --- esp-hal-embassy/src/executor/interrupt.rs | 2 +- esp-hal-embassy/src/executor/thread.rs | 2 +- esp-hal/src/analog/adc/riscv.rs | 4 +- esp-hal/src/assist_debug.rs | 2 +- esp-hal/src/cpu.rs | 92 ++++++++++++++++++ esp-hal/src/dma/mod.rs | 6 +- esp-hal/src/ecc.rs | 2 +- esp-hal/src/gpio/mod.rs | 4 +- esp-hal/src/i2c/master/mod.rs | 4 +- esp-hal/src/i2s/master.rs | 4 +- esp-hal/src/interrupt/riscv.rs | 6 +- esp-hal/src/interrupt/software.rs | 2 +- esp-hal/src/interrupt/xtensa.rs | 2 +- esp-hal/src/lcd_cam/mod.rs | 4 +- esp-hal/src/lib.rs | 94 +------------------ esp-hal/src/otg_fs.rs | 2 +- esp-hal/src/parl_io.rs | 10 +- esp-hal/src/pcnt/mod.rs | 2 +- esp-hal/src/reset.rs | 2 +- esp-hal/src/rmt.rs | 2 +- esp-hal/src/rsa/mod.rs | 4 +- esp-hal/src/rtc_cntl/mod.rs | 4 +- esp-hal/src/rtc_cntl/sleep/mod.rs | 10 +- esp-hal/src/sha.rs | 2 +- esp-hal/src/soc/esp32/cpu_control.rs | 2 +- esp-hal/src/soc/esp32/gpio.rs | 2 +- esp-hal/src/soc/esp32s3/cpu_control.rs | 2 +- esp-hal/src/spi/master.rs | 4 +- esp-hal/src/sync.rs | 2 +- esp-hal/src/timer/mod.rs | 2 +- esp-hal/src/timer/systimer.rs | 4 +- esp-hal/src/timer/timg.rs | 2 +- esp-hal/src/twai/mod.rs | 5 +- esp-hal/src/uart.rs | 4 +- esp-hal/src/usb_serial_jtag.rs | 4 +- esp-wifi/src/ble/os_adapter_esp32s3.rs | 2 +- esp-wifi/src/preempt/timer/riscv.rs | 2 +- esp-wifi/src/radio/radio_esp32.rs | 11 ++- esp-wifi/src/radio/radio_esp32c2.rs | 4 +- esp-wifi/src/radio/radio_esp32c3.rs | 6 +- esp-wifi/src/radio/radio_esp32c6.rs | 4 +- esp-wifi/src/radio/radio_esp32h2.rs | 4 +- esp-wifi/src/radio/radio_esp32s3.rs | 4 +- examples/src/bin/embassy_multicore.rs | 2 +- .../src/bin/embassy_multicore_interrupt.rs | 2 +- qa-test/src/bin/sleep_timer.rs | 2 +- qa-test/src/bin/sleep_timer_ext0.rs | 2 +- qa-test/src/bin/sleep_timer_ext1.rs | 2 +- qa-test/src/bin/sleep_timer_lpio.rs | 2 +- qa-test/src/bin/sleep_timer_rtcio.rs | 2 +- 50 files changed, 180 insertions(+), 172 deletions(-) create mode 100644 esp-hal/src/cpu.rs diff --git a/esp-hal-embassy/src/executor/interrupt.rs b/esp-hal-embassy/src/executor/interrupt.rs index f4ae92ba94d..c32bf5fa69d 100644 --- a/esp-hal-embassy/src/executor/interrupt.rs +++ b/esp-hal-embassy/src/executor/interrupt.rs @@ -4,8 +4,8 @@ use core::{cell::UnsafeCell, mem::MaybeUninit}; use embassy_executor::SendSpawner; use esp_hal::{ + cpu::Cpu, interrupt::{self, software::SoftwareInterrupt, InterruptHandler}, - Cpu, }; use portable_atomic::{AtomicUsize, Ordering}; diff --git a/esp-hal-embassy/src/executor/thread.rs b/esp-hal-embassy/src/executor/thread.rs index e2deb251e69..14b60d5c1be 100644 --- a/esp-hal-embassy/src/executor/thread.rs +++ b/esp-hal-embassy/src/executor/thread.rs @@ -5,7 +5,7 @@ use core::marker::PhantomData; use embassy_executor::Spawner; #[cfg(all(low_power_wait, multi_core))] use esp_hal::interrupt::software::SoftwareInterrupt; -use esp_hal::{interrupt::Priority, Cpu}; +use esp_hal::{cpu::Cpu, interrupt::Priority}; #[cfg(low_power_wait)] use portable_atomic::{AtomicBool, Ordering}; diff --git a/esp-hal/src/analog/adc/riscv.rs b/esp-hal/src/analog/adc/riscv.rs index 77d5085b5a3..34ad588f71d 100644 --- a/esp-hal/src/analog/adc/riscv.rs +++ b/esp-hal/src/analog/adc/riscv.rs @@ -534,7 +534,7 @@ impl crate::private::Sealed for Adc<'_, ADCI, Blocking> {} impl InterruptConfigurable for Adc<'_, ADCI, Blocking> { fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, InterruptSource); } unsafe { crate::interrupt::bind_interrupt(InterruptSource, handler.handler()) }; @@ -643,7 +643,7 @@ where pub fn into_blocking(self) -> Adc<'d, ADCI, Blocking> { if asynch::release_async_adc() { // Disable ADC interrupt on all cores if the last async ADC instance is disabled - for cpu in crate::Cpu::all() { + for cpu in crate::cpu::Cpu::all() { crate::interrupt::disable(cpu, InterruptSource); } } diff --git a/esp-hal/src/assist_debug.rs b/esp-hal/src/assist_debug.rs index 41e3fbd3685..586635ac714 100644 --- a/esp-hal/src/assist_debug.rs +++ b/esp-hal/src/assist_debug.rs @@ -52,7 +52,7 @@ impl<'d> DebugAssist<'d> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::ASSIST_DEBUG); } unsafe { crate::interrupt::bind_interrupt(Interrupt::ASSIST_DEBUG, handler.handler()) }; diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs new file mode 100644 index 00000000000..8243964b19f --- /dev/null +++ b/esp-hal/src/cpu.rs @@ -0,0 +1,92 @@ +//! CPU related functionality + +/// Available CPU cores +/// +/// The actual number of available cores depends on the target. +#[derive(Debug, Copy, Clone, PartialEq, Eq, strum::FromRepr)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(C)] +pub enum Cpu { + /// The first core + ProCpu = 0, + /// The second core + #[cfg(multi_core)] + AppCpu = 1, +} + +impl Cpu { + /// The number of available cores. + pub const COUNT: usize = 1 + cfg!(multi_core) as usize; + + /// Returns the core the application is currently executing on + #[inline(always)] + pub fn current() -> Self { + // This works for both RISCV and Xtensa because both + // get_raw_core functions return zero, _or_ something + // greater than zero; 1 in the case of RISCV and 0x2000 + // in the case of Xtensa. + match raw_core() { + 0 => Cpu::ProCpu, + #[cfg(all(multi_core, riscv))] + 1 => Cpu::AppCpu, + #[cfg(all(multi_core, xtensa))] + 0x2000 => Cpu::AppCpu, + _ => unreachable!(), + } + } + + /// Returns an iterator over the "other" cores. + #[inline(always)] + pub(crate) fn other() -> impl Iterator { + cfg_if::cfg_if! { + if #[cfg(multi_core)] { + match Self::current() { + Cpu::ProCpu => [Cpu::AppCpu].into_iter(), + Cpu::AppCpu => [Cpu::ProCpu].into_iter(), + } + } else { + [].into_iter() + } + } + } + + /// Returns an iterator over all cores. + #[inline(always)] + pub(crate) fn all() -> impl Iterator { + cfg_if::cfg_if! { + if #[cfg(multi_core)] { + [Cpu::ProCpu, Cpu::AppCpu].into_iter() + } else { + [Cpu::ProCpu].into_iter() + } + } + } +} + +/// Returns the raw value of the mhartid register. +/// +/// Safety: This method should never return UNUSED_THREAD_ID_VALUE +#[cfg(riscv)] +#[inline(always)] +pub(crate) fn raw_core() -> usize { + #[cfg(multi_core)] + { + riscv::register::mhartid::read() + } + + #[cfg(not(multi_core))] + 0 +} + +/// Returns the result of reading the PRID register logically ANDed with 0x2000, +/// the 13th bit in the register. Espressif Xtensa chips use this bit to +/// determine the core id. +/// +/// Returns either 0 or 0x2000 +/// +/// Safety: This method should never return UNUSED_THREAD_ID_VALUE +#[cfg(xtensa)] +#[inline(always)] +pub(crate) fn raw_core() -> usize { + (xtensa_lx::get_processor_id() & 0x2000) as usize +} diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs index 49731d6b139..0deb80f723d 100644 --- a/esp-hal/src/dma/mod.rs +++ b/esp-hal/src/dma/mod.rs @@ -61,6 +61,7 @@ pub use self::m2m::*; #[cfg(pdma)] pub use self::pdma::*; use crate::{ + cpu::Cpu, interrupt::InterruptHandler, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, @@ -68,7 +69,6 @@ use crate::{ system, Async, Blocking, - Cpu, DriverMode, }; @@ -1873,7 +1873,7 @@ where self.clear_in(EnumSet::all()); if let Some(interrupt) = self.rx_impl.peripheral_interrupt() { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; @@ -2168,7 +2168,7 @@ where self.clear_out(EnumSet::all()); if let Some(interrupt) = self.tx_impl.peripheral_interrupt() { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/ecc.rs b/esp-hal/src/ecc.rs index 451620264c1..71dbb6bbabd 100644 --- a/esp-hal/src/ecc.rs +++ b/esp-hal/src/ecc.rs @@ -992,7 +992,7 @@ impl Ecc<'_, Dm> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::ECC); } unsafe { crate::interrupt::bind_interrupt(Interrupt::ECC, handler.handler()) }; diff --git a/esp-hal/src/gpio/mod.rs b/esp-hal/src/gpio/mod.rs index 3e0773cee53..a421bedfe77 100644 --- a/esp-hal/src/gpio/mod.rs +++ b/esp-hal/src/gpio/mod.rs @@ -717,7 +717,7 @@ pub(crate) fn bind_default_interrupt_handler() { } // The vector table doesn't contain a custom entry.Still, the // peripheral interrupt may already be bound to something else. - if interrupt::bound_cpu_interrupt_for(crate::Cpu::current(), Interrupt::GPIO).is_some() { + if interrupt::bound_cpu_interrupt_for(crate::cpu::Cpu::current(), Interrupt::GPIO).is_some() { info!("Not using default GPIO interrupt handler: peripheral interrupt already in use"); return; } @@ -773,7 +773,7 @@ impl Io { /// `None`) #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::GPIO); } self.set_interrupt_priority(handler.priority()); diff --git a/esp-hal/src/i2c/master/mod.rs b/esp-hal/src/i2c/master/mod.rs index 306526e73a1..9d78647c465 100644 --- a/esp-hal/src/i2c/master/mod.rs +++ b/esp-hal/src/i2c/master/mod.rs @@ -1332,7 +1332,7 @@ impl Info { } fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, self.interrupt); } self.enable_listen(EnumSet::all(), false); @@ -1342,7 +1342,7 @@ impl Info { } fn disable_interrupts(&self) { - crate::interrupt::disable(crate::Cpu::current(), self.interrupt); + crate::interrupt::disable(crate::cpu::Cpu::current(), self.interrupt); } } diff --git a/esp-hal/src/i2s/master.rs b/esp-hal/src/i2s/master.rs index 8d8d21976ca..6de8a067e81 100644 --- a/esp-hal/src/i2s/master.rs +++ b/esp-hal/src/i2s/master.rs @@ -1518,7 +1518,7 @@ mod private { impl RegisterAccessPrivate for I2S0 { fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::I2S0); } unsafe { crate::peripherals::I2S0::steal() }.bind_i2s0_interrupt(handler.handler()); @@ -1627,7 +1627,7 @@ mod private { #[cfg(i2s1)] impl RegisterAccessPrivate for I2S1 { fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::I2S1); } unsafe { crate::peripherals::I2S1::steal() }.bind_i2s1_interrupt(handler.handler()); diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 47bbe6e03d4..430f5e1fd7c 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -23,9 +23,9 @@ pub use self::plic::*; pub use self::vectored::*; use super::InterruptStatus; use crate::{ + cpu::Cpu, pac, peripherals::{Interrupt, INTERRUPT_CORE0}, - Cpu, }; /// Interrupt Error @@ -560,7 +560,7 @@ mod vectored { #[cfg(not(plic))] mod classic { use super::{CpuInterrupt, InterruptKind, Priority}; - use crate::{peripherals::INTERRUPT_CORE0, Cpu}; + use crate::{cpu::Cpu, peripherals::INTERRUPT_CORE0}; #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")] pub(super) static DISABLED_CPU_INTERRUPT: u32 = 0; @@ -710,7 +710,7 @@ mod classic { #[cfg(plic)] mod plic { use super::{CpuInterrupt, InterruptKind, Priority}; - use crate::{peripherals::PLIC_MX, Cpu}; + use crate::{cpu::Cpu, peripherals::PLIC_MX}; #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")] pub(super) static DISABLED_CPU_INTERRUPT: u32 = 31; diff --git a/esp-hal/src/interrupt/software.rs b/esp-hal/src/interrupt/software.rs index 65dcc728e7d..e6abc55604d 100644 --- a/esp-hal/src/interrupt/software.rs +++ b/esp-hal/src/interrupt/software.rs @@ -66,7 +66,7 @@ impl SoftwareInterrupt { _ => unreachable!(), }; - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/interrupt/xtensa.rs b/esp-hal/src/interrupt/xtensa.rs index 9fe6b067c57..fac161bbd1b 100644 --- a/esp-hal/src/interrupt/xtensa.rs +++ b/esp-hal/src/interrupt/xtensa.rs @@ -6,7 +6,7 @@ use xtensa_lx_rt::exception::Context; pub use self::vectored::*; use super::InterruptStatus; -use crate::{pac, peripherals::Interrupt, Cpu}; +use crate::{cpu::Cpu, pac, peripherals::Interrupt}; /// Interrupt Error #[derive(Copy, Clone, Debug, PartialEq, Eq)] diff --git a/esp-hal/src/lcd_cam/mod.rs b/esp-hal/src/lcd_cam/mod.rs index fd5418787d0..b93b2c7f689 100644 --- a/esp-hal/src/lcd_cam/mod.rs +++ b/esp-hal/src/lcd_cam/mod.rs @@ -12,6 +12,7 @@ use core::marker::PhantomData; use crate::{ asynch::AtomicWaker, + cpu::Cpu, handler, interrupt::InterruptHandler, lcd_cam::{cam::Cam, lcd::Lcd}, @@ -20,7 +21,6 @@ use crate::{ system::GenericPeripheralGuard, Async, Blocking, - Cpu, }; /// Represents a combined LCD and Camera interface. @@ -71,7 +71,7 @@ impl<'d> LcdCam<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::LCD_CAM); } unsafe { crate::interrupt::bind_interrupt(Interrupt::LCD_CAM, handler.handler()) }; diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index 82b75b8552d..127f56f81dd 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -177,6 +177,7 @@ pub use self::soc::ulp_core; #[cfg(any(dport, hp_sys, pcr, system))] pub mod clock; +pub mod cpu; #[cfg(gpio)] pub mod gpio; #[cfg(any(i2c0, i2c1))] @@ -294,6 +295,8 @@ unstable_module! { } /// State of the CPU saved when entering exception or interrupt +#[instability::unstable] +#[allow(unused_imports)] pub mod trapframe { #[cfg(riscv)] pub use esp_riscv_rt::TrapFrame; @@ -404,97 +407,6 @@ pub mod __macro_implementation { pub use xtensa_lx_rt::entry as __entry; } -/// Available CPU cores -/// -/// The actual number of available cores depends on the target. -#[derive(Debug, Copy, Clone, PartialEq, Eq, strum::FromRepr)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[repr(C)] -pub enum Cpu { - /// The first core - ProCpu = 0, - /// The second core - #[cfg(multi_core)] - AppCpu = 1, -} - -impl Cpu { - /// The number of available cores. - pub const COUNT: usize = 1 + cfg!(multi_core) as usize; - - /// Returns the core the application is currently executing on - #[inline(always)] - pub fn current() -> Self { - // This works for both RISCV and Xtensa because both - // get_raw_core functions return zero, _or_ something - // greater than zero; 1 in the case of RISCV and 0x2000 - // in the case of Xtensa. - match raw_core() { - 0 => Cpu::ProCpu, - #[cfg(all(multi_core, riscv))] - 1 => Cpu::AppCpu, - #[cfg(all(multi_core, xtensa))] - 0x2000 => Cpu::AppCpu, - _ => unreachable!(), - } - } - - /// Returns an iterator over the "other" cores. - #[inline(always)] - pub(crate) fn other() -> impl Iterator { - cfg_if::cfg_if! { - if #[cfg(multi_core)] { - match Self::current() { - Cpu::ProCpu => [Cpu::AppCpu].into_iter(), - Cpu::AppCpu => [Cpu::ProCpu].into_iter(), - } - } else { - [].into_iter() - } - } - } - - /// Returns an iterator over all cores. - #[inline(always)] - pub(crate) fn all() -> impl Iterator { - cfg_if::cfg_if! { - if #[cfg(multi_core)] { - [Cpu::ProCpu, Cpu::AppCpu].into_iter() - } else { - [Cpu::ProCpu].into_iter() - } - } - } -} - -/// Returns the raw value of the mhartid register. -/// -/// Safety: This method should never return UNUSED_THREAD_ID_VALUE -#[cfg(riscv)] -#[inline(always)] -fn raw_core() -> usize { - #[cfg(multi_core)] - { - riscv::register::mhartid::read() - } - - #[cfg(not(multi_core))] - 0 -} - -/// Returns the result of reading the PRID register logically ANDed with 0x2000, -/// the 13th bit in the register. Espressif Xtensa chips use this bit to -/// determine the core id. -/// -/// Returns either 0 or 0x2000 -/// -/// Safety: This method should never return UNUSED_THREAD_ID_VALUE -#[cfg(xtensa)] -#[inline(always)] -fn raw_core() -> usize { - (xtensa_lx::get_processor_id() & 0x2000) as usize -} - #[cfg(riscv)] #[export_name = "hal_main"] fn hal_main(a0: usize, a1: usize, a2: usize) -> ! { diff --git a/esp-hal/src/otg_fs.rs b/esp-hal/src/otg_fs.rs index 21e7c8853c4..603d7620ac3 100644 --- a/esp-hal/src/otg_fs.rs +++ b/esp-hal/src/otg_fs.rs @@ -147,7 +147,7 @@ pub mod asynch { use procmacros::handler; use super::*; - use crate::Cpu; + use crate::cpu::Cpu; // From ESP32-S3 TRM: // Six additional endpoints (endpoint numbers 1 to 6), configurable as IN or OUT diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs index c234f38fe52..e030ea538c3 100644 --- a/esp-hal/src/parl_io.rs +++ b/esp-hal/src/parl_io.rs @@ -985,7 +985,7 @@ fn internal_set_interrupt_handler(handler: InterruptHandler) { let mut peri = unsafe { PARL_IO::steal() }; #[cfg(esp32c6)] { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::PARL_IO); } internal_listen(EnumSet::all(), false); @@ -999,7 +999,7 @@ fn internal_set_interrupt_handler(handler: InterruptHandler) { } #[cfg(esp32h2)] { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::PARL_IO_RX); crate::interrupt::disable(core, Interrupt::PARL_IO_TX); } @@ -1107,7 +1107,7 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> { /// Convert to an async version. pub fn into_async(self) -> ParlIoFullDuplex<'d, Async> { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); @@ -1244,7 +1244,7 @@ impl<'d> ParlIoTxOnly<'d, Blocking> { /// Converts to Async mode. pub fn into_async(self) -> ParlIoTxOnly<'d, Async> { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); @@ -1372,7 +1372,7 @@ impl<'d> ParlIoRxOnly<'d, Blocking> { /// Converts to Async mode. pub fn into_async(self) -> ParlIoRxOnly<'d, Async> { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); diff --git a/esp-hal/src/pcnt/mod.rs b/esp-hal/src/pcnt/mod.rs index bde96969b8f..dd3b56de5ac 100644 --- a/esp-hal/src/pcnt/mod.rs +++ b/esp-hal/src/pcnt/mod.rs @@ -188,7 +188,7 @@ impl<'d> Pcnt<'d> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::PCNT); } unsafe { interrupt::bind_interrupt(Interrupt::PCNT, handler.handler()) }; diff --git a/esp-hal/src/reset.rs b/esp-hal/src/reset.rs index eeed2b09296..900a45c31c0 100644 --- a/esp-hal/src/reset.rs +++ b/esp-hal/src/reset.rs @@ -103,7 +103,7 @@ pub fn software_reset_cpu() { /// Retrieves the reason for the last reset as a SocResetReason enum value. /// Returns `None` if the reset reason cannot be determined. pub fn reset_reason() -> Option { - crate::rtc_cntl::reset_reason(crate::Cpu::current()) + crate::rtc_cntl::reset_reason(crate::cpu::Cpu::current()) } /// Retrieves the cause of the last wakeup event as a SleepSource enum value. diff --git a/esp-hal/src/rmt.rs b/esp-hal/src/rmt.rs index 02ce1a21368..12ec096c5ee 100644 --- a/esp-hal/src/rmt.rs +++ b/esp-hal/src/rmt.rs @@ -449,7 +449,7 @@ impl<'d> Rmt<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::RMT); } unsafe { crate::interrupt::bind_interrupt(Interrupt::RMT, handler.handler()) }; diff --git a/esp-hal/src/rsa/mod.rs b/esp-hal/src/rsa/mod.rs index d230c8e6b62..697e7b0f005 100644 --- a/esp-hal/src/rsa/mod.rs +++ b/esp-hal/src/rsa/mod.rs @@ -24,6 +24,7 @@ use core::{marker::PhantomData, ptr::copy_nonoverlapping}; use crate::{ + cpu::Cpu, interrupt::InterruptHandler, pac, peripheral::{Peripheral, PeripheralRef}, @@ -31,7 +32,6 @@ use crate::{ system::{GenericPeripheralGuard, Peripheral as PeripheralEnable}, Async, Blocking, - Cpu, }; #[cfg_attr(esp32s2, path = "esp32sX.rs")] @@ -75,7 +75,7 @@ impl<'d> Rsa<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::RSA); } unsafe { crate::interrupt::bind_interrupt(Interrupt::RSA, handler.handler()) }; diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index da221e82177..e52c30f0180 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -123,12 +123,12 @@ use crate::efuse::Efuse; use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers}; use crate::{ clock::Clock, + cpu::Cpu, interrupt::{self, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, reset::{SleepSource, WakeupReason}, time::Duration, - Cpu, }; #[cfg(not(any(esp32c6, esp32h2)))] use crate::{ @@ -474,7 +474,7 @@ impl<'d> Rtc<'d> { let interrupt = Interrupt::RTC_CORE; } } - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/rtc_cntl/sleep/mod.rs b/esp-hal/src/rtc_cntl/sleep/mod.rs index 8d9744de175..6207c194d22 100644 --- a/esp-hal/src/rtc_cntl/sleep/mod.rs +++ b/esp-hal/src/rtc_cntl/sleep/mod.rs @@ -56,7 +56,7 @@ pub enum WakeupLevel { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::TimerWakeupSource, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::Cpu; +/// # use esp_hal::cpu::Cpu; /// /// let delay = Delay::new(); /// let mut rtc = Rtc::new(peripherals.LPWR); @@ -104,7 +104,7 @@ pub enum Error { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext0WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::Cpu; +/// # use esp_hal::cpu::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull}; /// /// let delay = Delay::new(); @@ -157,7 +157,7 @@ impl<'a, P: RtcIoWakeupPinType> Ext0WakeupSource<'a, P> { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext1WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::Cpu; +/// # use esp_hal::cpu::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull, RtcPin}; /// # use esp_hal::peripheral::Peripheral; /// @@ -214,7 +214,7 @@ impl<'a, 'b> Ext1WakeupSource<'a, 'b> { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext1WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::Cpu; +/// # use esp_hal::cpu::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull, RtcPinWithResistors}; /// # use esp_hal::peripheral::Peripheral; /// @@ -276,7 +276,7 @@ impl<'a, 'b> Ext1WakeupSource<'a, 'b> { /// # use esp_hal::delay::Delay; /// # use esp_hal::gpio::{self, Input, InputConfig, Pull}; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{RtcioWakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::Cpu; +/// # use esp_hal::cpu::Cpu; /// # use esp_hal::peripheral::Peripheral; /// /// let mut rtc = Rtc::new(peripherals.LPWR); diff --git a/esp-hal/src/sha.rs b/esp-hal/src/sha.rs index 38f9286dd00..3f3158c76a0 100644 --- a/esp-hal/src/sha.rs +++ b/esp-hal/src/sha.rs @@ -111,7 +111,7 @@ impl crate::private::Sealed for Sha<'_> {} #[instability::unstable] impl crate::interrupt::InterruptConfigurable for Sha<'_> { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::SHA); } unsafe { crate::interrupt::bind_interrupt(Interrupt::SHA, handler.handler()) }; diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index a303e6f112d..cd5c40463d4 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -58,9 +58,9 @@ use core::{ }; use crate::{ + cpu::Cpu, peripheral::{Peripheral, PeripheralRef}, peripherals::{CPU_CTRL, DPORT, LPWR, SPI0}, - Cpu, }; /// Data type for a properly aligned stack of N bytes diff --git a/esp-hal/src/soc/esp32/gpio.rs b/esp-hal/src/soc/esp32/gpio.rs index d9697eef014..38bb0d1dff5 100644 --- a/esp-hal/src/soc/esp32/gpio.rs +++ b/esp-hal/src/soc/esp32/gpio.rs @@ -43,10 +43,10 @@ use core::mem::transmute; use crate::{ + cpu::Cpu, gpio::{AlternateFunction, GpioPin}, pac::io_mux, peripherals::{GPIO, IO_MUX}, - Cpu, }; /// The total number of GPIO pins available. diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index b7dbee78b4b..d3f85a4e95c 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -59,9 +59,9 @@ use core::{ }; use crate::{ + cpu::Cpu, peripheral::{Peripheral, PeripheralRef}, peripherals::CPU_CTRL, - Cpu, }; /// Data type for a properly aligned stack of N bytes diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index 0aaf40a54e6..492f34afc65 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -46,6 +46,7 @@ use super::{BitOrder, DataMode, DmaError, Error, Mode}; use crate::{ asynch::AtomicWaker, clock::Clocks, + cpu::Cpu, dma::{DmaChannelFor, DmaEligible, DmaRxBuffer, DmaTxBuffer, Rx, Tx}, gpio::{ interconnect::{OutputConnection, PeripheralInput, PeripheralOutput}, @@ -63,7 +64,6 @@ use crate::{ time::Rate, Async, Blocking, - Cpu, DriverMode, }; @@ -1345,7 +1345,7 @@ mod dma { /// Interrupts are not enabled at the peripheral level here. fn set_interrupt_handler(&mut self, handler: InterruptHandler) { let interrupt = self.driver().info.interrupt; - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/sync.rs b/esp-hal/src/sync.rs index 2393129b733..edbf7f6bc4a 100644 --- a/esp-hal/src/sync.rs +++ b/esp-hal/src/sync.rs @@ -128,7 +128,7 @@ mod multicore { const UNUSED_THREAD_ID_VALUE: usize = 0x100; pub fn thread_id() -> usize { - crate::raw_core() + crate::cpu::raw_core() } pub(super) struct AtomicLock { diff --git a/esp-hal/src/timer/mod.rs b/esp-hal/src/timer/mod.rs index c7b8cebb0c8..16738f0f668 100644 --- a/esp-hal/src/timer/mod.rs +++ b/esp-hal/src/timer/mod.rs @@ -49,13 +49,13 @@ use core::{ use crate::{ asynch::AtomicWaker, + cpu::Cpu, interrupt::{InterruptConfigurable, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, time::{Duration, Instant}, Async, Blocking, - Cpu, DriverMode, }; diff --git a/esp-hal/src/timer/systimer.rs b/esp-hal/src/timer/systimer.rs index 8c74637519c..845974b7fc7 100644 --- a/esp-hal/src/timer/systimer.rs +++ b/esp-hal/src/timer/systimer.rs @@ -22,13 +22,13 @@ use core::fmt::Debug; use super::{Error, Timer as _}; use crate::{ asynch::AtomicWaker, + cpu::Cpu, interrupt::{self, InterruptHandler}, peripheral::Peripheral, peripherals::{Interrupt, SYSTIMER}, sync::{lock, RawMutex}, system::{Peripheral as PeripheralEnable, PeripheralClockControl}, time::{Duration, Instant}, - Cpu, }; /// The configuration of a unit. @@ -397,7 +397,7 @@ impl Alarm { _ => unreachable!(), }; - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs index 0b546876b58..2b7d034b9cc 100644 --- a/esp-hal/src/timer/timg.rs +++ b/esp-hal/src/timer/timg.rs @@ -391,7 +391,7 @@ impl Timer { _ => unreachable!(), }; - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/twai/mod.rs b/esp-hal/src/twai/mod.rs index 9fcca985938..e4564882476 100644 --- a/esp-hal/src/twai/mod.rs +++ b/esp-hal/src/twai/mod.rs @@ -122,6 +122,7 @@ use core::marker::PhantomData; use self::filter::{Filter, FilterType}; use crate::{ + cpu::Cpu, gpio::{ interconnect::{PeripheralInput, PeripheralOutput}, InputSignal, @@ -745,7 +746,7 @@ where } fn internal_set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in Cpu::other() { crate::interrupt::disable(core, self.twai.interrupt()); } unsafe { crate::interrupt::bind_interrupt(self.twai.interrupt(), handler.handler()) }; @@ -986,7 +987,7 @@ impl<'d> TwaiConfiguration<'d, Blocking> { impl<'d> TwaiConfiguration<'d, Async> { /// Convert the configuration into a blocking configuration. pub fn into_blocking(self) -> TwaiConfiguration<'d, Blocking> { - use crate::{interrupt, Cpu}; + use crate::{cpu::Cpu, interrupt}; interrupt::disable(Cpu::current(), self.twai.interrupt()); diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index bb98b09293d..61baa5ed6aa 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2234,7 +2234,7 @@ impl Info { } fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, self.interrupt); } self.enable_listen(EnumSet::all(), false); @@ -2244,7 +2244,7 @@ impl Info { } fn disable_interrupts(&self) { - crate::interrupt::disable(crate::Cpu::current(), self.interrupt); + crate::interrupt::disable(crate::cpu::Cpu::current(), self.interrupt); } fn apply_config(&self, config: &Config) -> Result<(), ConfigError> { diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs index f37ea70cc8d..22f72a7faa8 100644 --- a/esp-hal/src/usb_serial_jtag.rs +++ b/esp-hal/src/usb_serial_jtag.rs @@ -129,13 +129,13 @@ use procmacros::handler; use crate::{ asynch::AtomicWaker, + cpu::Cpu, pac::usb_device::RegisterBlock, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, USB_DEVICE}, system::PeripheralClockControl, Async, Blocking, - Cpu, DriverMode, }; @@ -447,7 +447,7 @@ where /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::Cpu::other() { + for core in crate::cpu::Cpu::other() { crate::interrupt::disable(core, Interrupt::USB_DEVICE); } unsafe { crate::interrupt::bind_interrupt(Interrupt::USB_DEVICE, handler.handler()) }; diff --git a/esp-wifi/src/ble/os_adapter_esp32s3.rs b/esp-wifi/src/ble/os_adapter_esp32s3.rs index 87cb9fb77ef..498f054eefe 100644 --- a/esp-wifi/src/ble/os_adapter_esp32s3.rs +++ b/esp-wifi/src/ble/os_adapter_esp32s3.rs @@ -306,7 +306,7 @@ pub(crate) unsafe extern "C" fn interrupt_on(intr_num: i32) -> i32 { pub(crate) unsafe extern "C" fn interrupt_off(intr_num: i32) -> i32 { trace!("interrupt_off {}", intr_num); interrupt::disable( - crate::hal::Cpu::ProCpu, + crate::hal::cpu::Cpu::ProCpu, Interrupt::try_from(intr_num as u16).unwrap(), ); diff --git a/esp-wifi/src/preempt/timer/riscv.rs b/esp-wifi/src/preempt/timer/riscv.rs index e7a41c0d1c8..33a303cfaf6 100644 --- a/esp-wifi/src/preempt/timer/riscv.rs +++ b/esp-wifi/src/preempt/timer/riscv.rs @@ -53,7 +53,7 @@ pub(crate) fn setup_multitasking() { } pub(crate) fn disable_multitasking() { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::FROM_CPU_INTR3); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::FROM_CPU_INTR3); } extern "C" fn handler(trap_frame: &mut TrapFrame) { diff --git a/esp-wifi/src/radio/radio_esp32.rs b/esp-wifi/src/radio/radio_esp32.rs index ab635015388..38e815f7903 100644 --- a/esp-wifi/src/radio/radio_esp32.rs +++ b/esp-wifi/src/radio/radio_esp32.rs @@ -7,16 +7,19 @@ pub(crate) fn setup_radio_isr() { { // It's a mystery why these interrupts are enabled now since it worked without // this before Now at least without disabling these nothing will work - interrupt::disable(crate::hal::Cpu::ProCpu, peripherals::Interrupt::ETH_MAC); - interrupt::disable(crate::hal::Cpu::ProCpu, peripherals::Interrupt::UART0); + interrupt::disable( + crate::hal::cpu::Cpu::ProCpu, + peripherals::Interrupt::ETH_MAC, + ); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::UART0); } } pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, peripherals::Interrupt::RWBT); - interrupt::disable(crate::hal::Cpu::ProCpu, peripherals::Interrupt::BT_BB); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::RWBT); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::BT_BB); } } diff --git a/esp-wifi/src/radio/radio_esp32c2.rs b/esp-wifi/src/radio/radio_esp32c2.rs index a9c821f522a..8e74d6656bd 100644 --- a/esp-wifi/src/radio/radio_esp32c2.rs +++ b/esp-wifi/src/radio/radio_esp32c2.rs @@ -12,8 +12,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::LP_TIMER); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_TIMER); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32c3.rs b/esp-wifi/src/radio/radio_esp32c3.rs index 6aa99482163..8250f3d7318 100644 --- a/esp-wifi/src/radio/radio_esp32c3.rs +++ b/esp-wifi/src/radio/radio_esp32c3.rs @@ -12,9 +12,9 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::RWBT); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::RWBLE); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::BT_BB); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBT); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBLE); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_BB); } } diff --git a/esp-wifi/src/radio/radio_esp32c6.rs b/esp-wifi/src/radio/radio_esp32c6.rs index 34a4002f30f..93f9f254a8c 100644 --- a/esp-wifi/src/radio/radio_esp32c6.rs +++ b/esp-wifi/src/radio/radio_esp32c6.rs @@ -23,8 +23,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::LP_TIMER); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_TIMER); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32h2.rs b/esp-wifi/src/radio/radio_esp32h2.rs index d0f80f366a7..29d8695de2f 100644 --- a/esp-wifi/src/radio/radio_esp32h2.rs +++ b/esp-wifi/src/radio/radio_esp32h2.rs @@ -11,8 +11,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::LP_BLE_TIMER); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_BLE_TIMER); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32s3.rs b/esp-wifi/src/radio/radio_esp32s3.rs index 8e521339f8e..1baf898ed6b 100644 --- a/esp-wifi/src/radio/radio_esp32s3.rs +++ b/esp-wifi/src/radio/radio_esp32s3.rs @@ -9,8 +9,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::BT_BB); - interrupt::disable(crate::hal::Cpu::ProCpu, Interrupt::RWBLE); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_BB); + interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBLE); } } diff --git a/examples/src/bin/embassy_multicore.rs b/examples/src/bin/embassy_multicore.rs index da5b9ee2433..ec5f9971de9 100644 --- a/examples/src/bin/embassy_multicore.rs +++ b/examples/src/bin/embassy_multicore.rs @@ -22,7 +22,7 @@ use esp_hal::{ cpu_control::{CpuControl, Stack}, gpio::{Level, Output, OutputConfig}, timer::{timg::TimerGroup, AnyTimer}, - Cpu, + cpu::Cpu, }; use esp_hal_embassy::Executor; use esp_println::println; diff --git a/examples/src/bin/embassy_multicore_interrupt.rs b/examples/src/bin/embassy_multicore_interrupt.rs index ca160d3fe54..65cdcedad2e 100644 --- a/examples/src/bin/embassy_multicore_interrupt.rs +++ b/examples/src/bin/embassy_multicore_interrupt.rs @@ -23,7 +23,7 @@ use esp_hal::{ interrupt::{software::SoftwareInterruptControl, Priority}, main, timer::{timg::TimerGroup, AnyTimer}, - Cpu, + cpu::Cpu, }; use esp_hal_embassy::InterruptExecutor; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer.rs b/qa-test/src/bin/sleep_timer.rs index ced10b1820e..1137534a983 100644 --- a/qa-test/src/bin/sleep_timer.rs +++ b/qa-test/src/bin/sleep_timer.rs @@ -9,10 +9,10 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ + cpu::Cpu, delay::Delay, main, rtc_cntl::{reset_reason, sleep::TimerWakeupSource, wakeup_cause, Rtc, SocResetReason}, - Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_ext0.rs b/qa-test/src/bin/sleep_timer_ext0.rs index ca0f59cba80..f396c2da18a 100644 --- a/qa-test/src/bin/sleep_timer_ext0.rs +++ b/qa-test/src/bin/sleep_timer_ext0.rs @@ -12,6 +12,7 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ + cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull}, main, @@ -22,7 +23,6 @@ use esp_hal::{ Rtc, SocResetReason, }, - Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_ext1.rs b/qa-test/src/bin/sleep_timer_ext1.rs index bd059b0db15..87bece606ad 100644 --- a/qa-test/src/bin/sleep_timer_ext1.rs +++ b/qa-test/src/bin/sleep_timer_ext1.rs @@ -12,6 +12,7 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ + cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull, RtcPin}, main, @@ -22,7 +23,6 @@ use esp_hal::{ Rtc, SocResetReason, }, - Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_lpio.rs b/qa-test/src/bin/sleep_timer_lpio.rs index 126109ddc52..5341db7c6f0 100644 --- a/qa-test/src/bin/sleep_timer_lpio.rs +++ b/qa-test/src/bin/sleep_timer_lpio.rs @@ -13,6 +13,7 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ + cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull, RtcPinWithResistors}, main, @@ -23,7 +24,6 @@ use esp_hal::{ Rtc, SocResetReason, }, - Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_rtcio.rs b/qa-test/src/bin/sleep_timer_rtcio.rs index 982119017c3..80a2f6e58e1 100644 --- a/qa-test/src/bin/sleep_timer_rtcio.rs +++ b/qa-test/src/bin/sleep_timer_rtcio.rs @@ -16,6 +16,7 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ + cpu::Cpu, delay::Delay, gpio, gpio::{Input, InputConfig, Pull}, @@ -27,7 +28,6 @@ use esp_hal::{ Rtc, SocResetReason, }, - Cpu, }; use esp_println::println; From d510ece49777f8dbef67740a887ad062a7f2c971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 11:40:38 +0100 Subject: [PATCH 02/13] Move cpu_control's contents into cpu --- esp-hal/src/cpu.rs | 3 +++ esp-hal/src/lib.rs | 2 -- esp-hal/src/soc/esp32/cpu_control.rs | 2 +- esp-hal/src/soc/esp32s3/cpu_control.rs | 2 +- examples/src/bin/embassy_multicore.rs | 3 +-- examples/src/bin/embassy_multicore_interrupt.rs | 3 +-- hil-test/tests/embassy_interrupt_executor.rs | 2 +- hil-test/tests/embassy_interrupt_spi_dma.rs | 2 +- hil-test/tests/esp_wifi_floats.rs | 5 ++--- 9 files changed, 11 insertions(+), 13 deletions(-) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index 8243964b19f..ebd34eb2bb6 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -1,5 +1,8 @@ //! CPU related functionality +#[cfg(any(esp32, esp32s3))] +pub use crate::soc::cpu_control::*; + /// Available CPU cores /// /// The actual number of available cores depends on the target. diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index 127f56f81dd..78e47b20db1 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -155,8 +155,6 @@ pub use esp_riscv_rt::{self, riscv}; pub use xtensa_lx_rt::{self, xtensa_lx}; // TODO what should we reexport stably? -#[cfg(any(esp32, esp32s3))] -pub use self::soc::cpu_control; #[cfg(efuse)] #[instability::unstable] #[cfg_attr(not(feature = "unstable"), allow(unused))] diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index cd5c40463d4..75303264861 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -9,7 +9,7 @@ //! ```rust, no_run #![doc = crate::before_snippet!()] //! # use esp_hal::delay::Delay; -//! # use esp_hal::cpu_control::{CpuControl, Stack}; +//! # use esp_hal::cpu::{CpuControl, Stack}; //! # use core::{cell::RefCell, ptr::addr_of_mut}; //! # use critical_section::Mutex; //! static mut APP_CORE_STACK: Stack<8192> = Stack::new(); diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index d3f85a4e95c..8f65c3c045a 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -10,7 +10,7 @@ //! ```rust, no_run #![doc = crate::before_snippet!()] //! # use esp_hal::delay::Delay; -//! # use esp_hal::cpu_control::{CpuControl, Stack}; +//! # use esp_hal::cpu::{CpuControl, Stack}; //! # use core::{cell::RefCell, ptr::addr_of_mut}; //! # use critical_section::Mutex; //! # let delay = Delay::new(); diff --git a/examples/src/bin/embassy_multicore.rs b/examples/src/bin/embassy_multicore.rs index ec5f9971de9..aa5b6fde1a3 100644 --- a/examples/src/bin/embassy_multicore.rs +++ b/examples/src/bin/embassy_multicore.rs @@ -19,10 +19,9 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal} use embassy_time::{Duration, Ticker}; use esp_backtrace as _; use esp_hal::{ - cpu_control::{CpuControl, Stack}, + cpu::{Cpu, CpuControl, Stack}, gpio::{Level, Output, OutputConfig}, timer::{timg::TimerGroup, AnyTimer}, - cpu::Cpu, }; use esp_hal_embassy::Executor; use esp_println::println; diff --git a/examples/src/bin/embassy_multicore_interrupt.rs b/examples/src/bin/embassy_multicore_interrupt.rs index 65cdcedad2e..a193d116e98 100644 --- a/examples/src/bin/embassy_multicore_interrupt.rs +++ b/examples/src/bin/embassy_multicore_interrupt.rs @@ -18,12 +18,11 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal} use embassy_time::{Duration, Ticker}; use esp_backtrace as _; use esp_hal::{ - cpu_control::{CpuControl, Stack}, + cpu::{Cpu, CpuControl, Stack}, gpio::{Level, Output, OutputConfig}, interrupt::{software::SoftwareInterruptControl, Priority}, main, timer::{timg::TimerGroup, AnyTimer}, - cpu::Cpu, }; use esp_hal_embassy::InterruptExecutor; use esp_println::println; diff --git a/hil-test/tests/embassy_interrupt_executor.rs b/hil-test/tests/embassy_interrupt_executor.rs index b44e30992dc..7346ddecb25 100644 --- a/hil-test/tests/embassy_interrupt_executor.rs +++ b/hil-test/tests/embassy_interrupt_executor.rs @@ -15,7 +15,7 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal}; #[cfg(multi_core)] -use esp_hal::cpu_control::{CpuControl, Stack}; +use esp_hal::cpu::{CpuControl, Stack}; use esp_hal::{ interrupt::{ software::{SoftwareInterrupt, SoftwareInterruptControl}, diff --git a/hil-test/tests/embassy_interrupt_spi_dma.rs b/hil-test/tests/embassy_interrupt_spi_dma.rs index fdb3a578ac9..1449dcfc483 100644 --- a/hil-test/tests/embassy_interrupt_spi_dma.rs +++ b/hil-test/tests/embassy_interrupt_spi_dma.rs @@ -308,7 +308,7 @@ mod test { } }; - use esp_hal::cpu_control::{CpuControl, Stack}; + use esp_hal::cpu::{CpuControl, Stack}; const DISPLAY_STACK_SIZE: usize = 8192; let app_core_stack = mk_static!(Stack, Stack::new()); let cpu_control = CpuControl::new(peripherals.CPU_CTRL); diff --git a/hil-test/tests/esp_wifi_floats.rs b/hil-test/tests/esp_wifi_floats.rs index af874c1b0ba..e12202d38e0 100644 --- a/hil-test/tests/esp_wifi_floats.rs +++ b/hil-test/tests/esp_wifi_floats.rs @@ -42,11 +42,10 @@ cfg_if::cfg_if! { if #[cfg(multi_core)] { use core::sync::atomic::{AtomicBool, Ordering}; - use esp_hal::cpu_control::CpuControl; + use esp_hal::cpu::{CpuControl, Stack}; static DONE: AtomicBool = AtomicBool::new(false); - static mut APP_CORE_STACK: esp_hal::cpu_control::Stack<8192> = - esp_hal::cpu_control::Stack::new(); + static mut APP_CORE_STACK: Stack<8192> = Stack::new(); } } From dbdc21313592847a0340d1f480c97dc7051071d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 12:16:53 +0100 Subject: [PATCH 03/13] Merge raw_core functions --- esp-hal/src/cpu.rs | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index ebd34eb2bb6..b5810a4d96f 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -68,28 +68,21 @@ impl Cpu { /// Returns the raw value of the mhartid register. /// -/// Safety: This method should never return UNUSED_THREAD_ID_VALUE -#[cfg(riscv)] -#[inline(always)] -pub(crate) fn raw_core() -> usize { - #[cfg(multi_core)] - { - riscv::register::mhartid::read() - } - - #[cfg(not(multi_core))] - 0 -} - -/// Returns the result of reading the PRID register logically ANDed with 0x2000, -/// the 13th bit in the register. Espressif Xtensa chips use this bit to -/// determine the core id. -/// -/// Returns either 0 or 0x2000 +/// On RISC-V, this is the hardware thread ID. /// -/// Safety: This method should never return UNUSED_THREAD_ID_VALUE -#[cfg(xtensa)] +/// On Xtensa, this returns the result of reading the PRID register logically +/// ANDed with 0x2000, the 13th bit in the register. Espressif Xtensa chips use +/// this bit to determine the core id. #[inline(always)] pub(crate) fn raw_core() -> usize { - (xtensa_lx::get_processor_id() & 0x2000) as usize + // This method must never return UNUSED_THREAD_ID_VALUE + cfg_if::cfg_if! { + if #[cfg(all(multi_core, riscv))] { + riscv::register::mhartid::read() + } else if #[cfg(all(multi_core, xtensa))] { + (xtensa_lx::get_processor_id() & 0x2000) as usize + } else { + 0 + } + } } From 8c432dd931f1191f2638324ddf9a753427a0848c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 12:38:42 +0100 Subject: [PATCH 04/13] Hide cpu control APIs --- esp-hal/src/soc/esp32/cpu_control.rs | 153 +++++++++++------------ esp-hal/src/soc/esp32s3/cpu_control.rs | 164 ++++++++++++------------- 2 files changed, 150 insertions(+), 167 deletions(-) diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index 75303264861..fb13cbaef60 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -4,53 +4,6 @@ //! This module provides essential functionality for controlling //! and managing the APP (second) CPU core on the `ESP32` chip. It is used to //! start and stop program execution on the APP core. -//! -//! ## Examples -//! ```rust, no_run -#![doc = crate::before_snippet!()] -//! # use esp_hal::delay::Delay; -//! # use esp_hal::cpu::{CpuControl, Stack}; -//! # use core::{cell::RefCell, ptr::addr_of_mut}; -//! # use critical_section::Mutex; -//! static mut APP_CORE_STACK: Stack<8192> = Stack::new(); -//! -//! # let delay = Delay::new(); -//! -//! let counter = Mutex::new(RefCell::new(0)); -//! -//! let mut cpu_control = CpuControl::new(peripherals.CPU_CTRL); -//! let cpu1_fnctn = || { -//! cpu1_task(&delay, &counter); -//! }; -//! let _guard = cpu_control -//! .start_app_core( -//! unsafe { &mut *addr_of_mut!(APP_CORE_STACK) }, -//! cpu1_fnctn -//! )?; -//! -//! loop { -//! delay.delay(Duration::from_secs(1)); -//! let count = critical_section::with(|cs| *counter.borrow_ref(cs)); -//! } -//! # } -//! -//! // Where `cpu1_task()` may be defined as: -//! # use esp_hal::delay::Delay; -//! # use core::cell::RefCell; -//! fn cpu1_task( -//! delay: &Delay, -//! counter: &critical_section::Mutex>, -//! ) -> ! { -//! loop { -//! delay.delay(Duration::from_millis(500)); -//! -//! critical_section::with(|cs| { -//! let mut val = counter.borrow_ref_mut(cs); -//! *val = val.wrapping_add(1); -//! }); -//! } -//! } -//! ``` use core::{ marker::PhantomData, @@ -77,6 +30,7 @@ use crate::{ // Stack frame alignment depends on the SIZE as well as the placement of the // array. #[repr(C, align(16))] +#[instability::unstable] pub struct Stack { /// Memory to be used for the stack pub mem: MaybeUninit<[u8; SIZE]>, @@ -91,6 +45,7 @@ impl Default for Stack { #[allow(clippy::len_without_is_empty)] impl Stack { /// Construct a stack of length SIZE, uninitialized + #[instability::unstable] pub const fn new() -> Stack { ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. @@ -99,17 +54,20 @@ impl Stack { } } - /// Returns the size of the stack. + /// Returns the length of the stack in bytes. + #[instability::unstable] pub const fn len(&self) -> usize { SIZE } - /// Provides a mutable pointer to the bottom of the stack. + /// Returns a mutable pointer to the bottom of the stack. + #[instability::unstable] pub fn bottom(&mut self) -> *mut u32 { self.mem.as_mut_ptr() as *mut u32 } - /// Provides a mutable pointer to the top of the stack. + /// Returns a mutable pointer to the top of the stack. + #[instability::unstable] pub fn top(&mut self) -> *mut u32 { unsafe { self.bottom().add(SIZE / 4) } } @@ -118,53 +76,102 @@ impl Stack { // Pointer to the closure that will be executed on the second core. The closure // is copied to the core's stack. static mut START_CORE1_FUNCTION: Option<*mut ()> = None; - static mut APP_CORE_STACK_TOP: Option<*mut u32> = None; /// Will park the APP (second) core when dropped -#[must_use] +#[must_use = "Dropping this guard will park the APP core"] +#[instability::unstable] pub struct AppCoreGuard<'a> { phantom: PhantomData<&'a ()>, } impl Drop for AppCoreGuard<'_> { fn drop(&mut self) { - unsafe { - internal_park_core(Cpu::AppCpu); - } + unsafe { internal_park_core(Cpu::AppCpu, true) }; } } /// Represents errors that can occur while working with the core. #[derive(Debug, Clone, Copy, PartialEq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[instability::unstable] pub enum Error { /// The core is already running. CoreAlreadyRunning, } /// Control CPU Cores +/// +/// ## Examples +/// ```rust, no_run +#[doc = crate::before_snippet!()] +/// # use esp_hal::delay::Delay; +/// # use esp_hal::cpu_control::{CpuControl, Stack}; +/// # use core::{cell::RefCell, ptr::addr_of_mut}; +/// # use critical_section::Mutex; +/// # let delay = Delay::new(); +/// static mut APP_CORE_STACK: Stack<8192> = Stack::new(); +/// +/// let counter = Mutex::new(RefCell::new(0)); +/// +/// let mut cpu_control = CpuControl::new(peripherals.CPU_CTRL); +/// let cpu1_fnctn = || { +/// cpu1_task(&delay, &counter); +/// }; +/// let _guard = cpu_control +/// .start_app_core( +/// unsafe { &mut *addr_of_mut!(APP_CORE_STACK) }, +/// cpu1_fnctn +/// )?; +/// +/// loop { +/// delay.delay(Duration::from_secs(1)); +/// let count = critical_section::with(|cs| *counter.borrow_ref(cs)); +/// } +/// # } +/// +/// // Where `cpu1_task()` may be defined as: +/// # use esp_hal::delay::Delay; +/// # use core::cell::RefCell; +/// +/// fn cpu1_task( +/// delay: &Delay, +/// counter: &critical_section::Mutex>, +/// ) -> ! { +/// loop { +/// delay.delay(Duration::from_millis(500)); +/// +/// critical_section::with(|cs| { +/// let mut val = counter.borrow_ref_mut(cs); +/// *val = val.wrapping_add(1); +/// }); +/// } +/// } +/// ``` +#[instability::unstable] pub struct CpuControl<'d> { _cpu_control: PeripheralRef<'d, CPU_CTRL>, } -unsafe fn internal_park_core(core: Cpu) { +unsafe fn internal_park_core(core: Cpu, park: bool) { + let c1_value = if park { 0x21 } else { 0 }; + let c0_value = if park { 0x02 } else { 0 }; match core { Cpu::ProCpu => { LPWR::regs() .sw_cpu_stall() - .modify(|_, w| w.sw_stall_procpu_c1().bits(0x21)); + .modify(|_, w| w.sw_stall_procpu_c1().bits(c1_value)); LPWR::regs() .options0() - .modify(|_, w| w.sw_stall_procpu_c0().bits(0x02)); + .modify(|_, w| w.sw_stall_procpu_c0().bits(c0_value)); } Cpu::AppCpu => { LPWR::regs() .sw_cpu_stall() - .modify(|_, w| w.sw_stall_appcpu_c1().bits(0x21)); + .modify(|_, w| w.sw_stall_appcpu_c1().bits(c1_value)); LPWR::regs() .options0() - .modify(|_, w| w.sw_stall_appcpu_c0().bits(0x02)); + .modify(|_, w| w.sw_stall_appcpu_c0().bits(c0_value)); } } } @@ -186,30 +193,15 @@ impl<'d> CpuControl<'d> { /// /// The user must ensure that the core being parked is not the core which is /// currently executing their code. + #[instability::unstable] pub unsafe fn park_core(&mut self, core: Cpu) { - internal_park_core(core); + internal_park_core(core, true); } /// Unpark the given core + #[instability::unstable] pub fn unpark_core(&mut self, core: Cpu) { - match core { - Cpu::ProCpu => { - LPWR::regs() - .sw_cpu_stall() - .modify(|_, w| unsafe { w.sw_stall_procpu_c1().bits(0) }); - LPWR::regs() - .options0() - .modify(|_, w| unsafe { w.sw_stall_procpu_c0().bits(0) }); - } - Cpu::AppCpu => { - LPWR::regs() - .sw_cpu_stall() - .modify(|_, w| unsafe { w.sw_stall_appcpu_c1().bits(0) }); - LPWR::regs() - .options0() - .modify(|_, w| unsafe { w.sw_stall_appcpu_c0().bits(0) }); - } - } + unsafe { internal_park_core(core, false) }; } fn flush_cache(&mut self, core: Cpu) { @@ -323,7 +315,7 @@ impl<'d> CpuControl<'d> { let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::>()) }; entry(); loop { - unsafe { internal_park_core(Cpu::current()) }; + unsafe { internal_park_core(Cpu::current(), true) }; } } None => panic!("No start function set"), @@ -336,6 +328,7 @@ impl<'d> CpuControl<'d> { /// closure exits, the core will be parked. /// /// Dropping the returned guard will park the core. + #[instability::unstable] pub fn start_app_core<'a, const SIZE: usize, F>( &mut self, stack: &'static mut Stack, diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index 8f65c3c045a..915e8a653ba 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -5,53 +5,6 @@ //! This module provides essential functionality for controlling //! and managing the APP (second) CPU core on the `ESP32-S3` chip. It is used to //! start and stop program execution on the APP core. -//! -//! ## Examples -//! ```rust, no_run -#![doc = crate::before_snippet!()] -//! # use esp_hal::delay::Delay; -//! # use esp_hal::cpu::{CpuControl, Stack}; -//! # use core::{cell::RefCell, ptr::addr_of_mut}; -//! # use critical_section::Mutex; -//! # let delay = Delay::new(); -//! static mut APP_CORE_STACK: Stack<8192> = Stack::new(); -//! -//! let counter = Mutex::new(RefCell::new(0)); -//! -//! let mut cpu_control = CpuControl::new(peripherals.CPU_CTRL); -//! let cpu1_fnctn = || { -//! cpu1_task(&delay, &counter); -//! }; -//! let _guard = cpu_control -//! .start_app_core( -//! unsafe { &mut *addr_of_mut!(APP_CORE_STACK) }, -//! cpu1_fnctn -//! )?; -//! -//! loop { -//! delay.delay(Duration::from_secs(1)); -//! let count = critical_section::with(|cs| *counter.borrow_ref(cs)); -//! } -//! # } -//! -//! // Where `cpu1_task()` may be defined as: -//! # use esp_hal::delay::Delay; -//! # use core::cell::RefCell; -//! -//! fn cpu1_task( -//! delay: &Delay, -//! counter: &critical_section::Mutex>, -//! ) -> ! { -//! loop { -//! delay.delay(Duration::from_millis(500)); -//! -//! critical_section::with(|cs| { -//! let mut val = counter.borrow_ref_mut(cs); -//! *val = val.wrapping_add(1); -//! }); -//! } -//! } -//! ``` use core::{ marker::PhantomData, @@ -61,7 +14,7 @@ use core::{ use crate::{ cpu::Cpu, peripheral::{Peripheral, PeripheralRef}, - peripherals::CPU_CTRL, + peripherals::{CPU_CTRL, LPWR, SYSTEM}, }; /// Data type for a properly aligned stack of N bytes @@ -78,6 +31,7 @@ use crate::{ // Stack frame alignment depends on the SIZE as well as the placement of the // array. #[repr(C, align(16))] +#[instability::unstable] pub struct Stack { /// Memory to be used for the stack pub mem: MaybeUninit<[u8; SIZE]>, @@ -92,6 +46,7 @@ impl Default for Stack { #[allow(clippy::len_without_is_empty)] impl Stack { /// Construct a stack of length SIZE, uninitialized + #[instability::unstable] pub const fn new() -> Stack { ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. @@ -101,16 +56,19 @@ impl Stack { } /// Returns the length of the stack in bytes. + #[instability::unstable] pub const fn len(&self) -> usize { SIZE } /// Returns a mutable pointer to the bottom of the stack. + #[instability::unstable] pub fn bottom(&mut self) -> *mut u32 { self.mem.as_mut_ptr() as *mut u32 } /// Returns a mutable pointer to the top of the stack. + #[instability::unstable] pub fn top(&mut self) -> *mut u32 { unsafe { self.bottom().add(SIZE / 4) } } @@ -122,51 +80,99 @@ static mut START_CORE1_FUNCTION: Option<*mut ()> = None; static mut APP_CORE_STACK_TOP: Option<*mut u32> = None; /// Will park the APP (second) core when dropped -#[must_use] +#[must_use = "Dropping this guard will park the APP core"] +#[instability::unstable] pub struct AppCoreGuard<'a> { phantom: PhantomData<&'a ()>, } impl Drop for AppCoreGuard<'_> { fn drop(&mut self) { - unsafe { - internal_park_core(Cpu::AppCpu); - } + unsafe { internal_park_core(Cpu::AppCpu, true) }; } } /// Represents errors that can occur while working with the core. #[derive(Debug, Clone, Copy, PartialEq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[instability::unstable] pub enum Error { /// The core is already running. CoreAlreadyRunning, } /// Control CPU Cores +/// +/// ## Examples +/// ```rust, no_run +#[doc = crate::before_snippet!()] +/// # use esp_hal::delay::Delay; +/// # use esp_hal::cpu_control::{CpuControl, Stack}; +/// # use core::{cell::RefCell, ptr::addr_of_mut}; +/// # use critical_section::Mutex; +/// # let delay = Delay::new(); +/// static mut APP_CORE_STACK: Stack<8192> = Stack::new(); +/// +/// let counter = Mutex::new(RefCell::new(0)); +/// +/// let mut cpu_control = CpuControl::new(peripherals.CPU_CTRL); +/// let cpu1_fnctn = || { +/// cpu1_task(&delay, &counter); +/// }; +/// let _guard = cpu_control +/// .start_app_core( +/// unsafe { &mut *addr_of_mut!(APP_CORE_STACK) }, +/// cpu1_fnctn +/// )?; +/// +/// loop { +/// delay.delay(Duration::from_secs(1)); +/// let count = critical_section::with(|cs| *counter.borrow_ref(cs)); +/// } +/// # } +/// +/// // Where `cpu1_task()` may be defined as: +/// # use esp_hal::delay::Delay; +/// # use core::cell::RefCell; +/// +/// fn cpu1_task( +/// delay: &Delay, +/// counter: &critical_section::Mutex>, +/// ) -> ! { +/// loop { +/// delay.delay(Duration::from_millis(500)); +/// +/// critical_section::with(|cs| { +/// let mut val = counter.borrow_ref_mut(cs); +/// *val = val.wrapping_add(1); +/// }); +/// } +/// } +/// ``` +#[instability::unstable] pub struct CpuControl<'d> { _cpu_control: PeripheralRef<'d, CPU_CTRL>, } -unsafe fn internal_park_core(core: Cpu) { - let rtc_control = crate::peripherals::LPWR::regs(); - +unsafe fn internal_park_core(core: Cpu, park: bool) { + let c1_value = if park { 0x21 } else { 0 }; + let c0_value = if park { 0x02 } else { 0 }; match core { Cpu::ProCpu => { - rtc_control + LPWR::regs() .sw_cpu_stall() - .modify(|_, w| w.sw_stall_procpu_c1().bits(0x21)); - rtc_control + .modify(|_, w| w.sw_stall_procpu_c1().bits(c1_value)); + LPWR::regs() .options0() - .modify(|_, w| w.sw_stall_procpu_c0().bits(0x02)); + .modify(|_, w| w.sw_stall_procpu_c0().bits(c0_value)); } Cpu::AppCpu => { - rtc_control + LPWR::regs() .sw_cpu_stall() - .modify(|_, w| w.sw_stall_appcpu_c1().bits(0x21)); - rtc_control + .modify(|_, w| w.sw_stall_appcpu_c1().bits(c1_value)); + LPWR::regs() .options0() - .modify(|_, w| w.sw_stall_appcpu_c0().bits(0x02)); + .modify(|_, w| w.sw_stall_appcpu_c0().bits(c0_value)); } } } @@ -188,32 +194,15 @@ impl<'d> CpuControl<'d> { /// /// The user must ensure that the core being parked is not the core which is /// currently executing their code. + #[instability::unstable] pub unsafe fn park_core(&mut self, core: Cpu) { - internal_park_core(core); + internal_park_core(core, true); } /// Unpark the given core + #[instability::unstable] pub fn unpark_core(&mut self, core: Cpu) { - let rtc_control = crate::peripherals::LPWR::regs(); - - match core { - Cpu::ProCpu => { - rtc_control - .sw_cpu_stall() - .modify(|_, w| unsafe { w.sw_stall_procpu_c1().bits(0) }); - rtc_control - .options0() - .modify(|_, w| unsafe { w.sw_stall_procpu_c0().bits(0) }); - } - Cpu::AppCpu => { - rtc_control - .sw_cpu_stall() - .modify(|_, w| unsafe { w.sw_stall_appcpu_c1().bits(0) }); - rtc_control - .options0() - .modify(|_, w| unsafe { w.sw_stall_appcpu_c0().bits(0) }); - } - } + unsafe { internal_park_core(core, false) }; } /// When we get here, the core is out of reset, with a stack setup by ROM @@ -265,19 +254,20 @@ impl<'d> CpuControl<'d> { let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::>()) }; entry(); loop { - unsafe { internal_park_core(Cpu::current()) }; + unsafe { internal_park_core(Cpu::current(), true) }; } } None => panic!("No start function set"), } } - /// Start the APP (second) core + /// Start the APP (second) core. /// /// The second core will start running the closure `entry`. Note that if the /// closure exits, the core will be parked. /// /// Dropping the returned guard will park the core. + #[instability::unstable] pub fn start_app_core<'a, const SIZE: usize, F>( &mut self, stack: &'static mut Stack, @@ -287,7 +277,7 @@ impl<'d> CpuControl<'d> { F: FnOnce(), F: Send + 'a, { - let system_control = crate::peripherals::SYSTEM::regs(); + let system_control = SYSTEM::regs(); if !xtensa_lx::is_debugger_attached() && system_control From 6630fe53b79a06664429dae75915dbb684fdb7a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 12:57:51 +0100 Subject: [PATCH 05/13] Move reset into cpu --- esp-hal/src/cpu.rs | 101 ++++++++++++++++++++++ esp-hal/src/lib.rs | 2 - esp-hal/src/reset.rs | 112 ------------------------- esp-hal/src/rtc_cntl/mod.rs | 3 +- esp-hal/src/soc/esp32/cpu_control.rs | 2 +- esp-hal/src/soc/esp32/mod.rs | 2 +- esp-hal/src/soc/esp32s2/mod.rs | 2 +- esp-hal/src/soc/esp32s3/cpu_control.rs | 2 +- esp-hal/src/soc/esp32s3/mod.rs | 2 +- examples/src/bin/ieee802154_sniffer.rs | 2 +- 10 files changed, 108 insertions(+), 122 deletions(-) delete mode 100644 esp-hal/src/reset.rs diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index b5810a4d96f..f843bafd0cb 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -1,6 +1,7 @@ //! CPU related functionality #[cfg(any(esp32, esp32s3))] +#[allow(unused_imports)] pub use crate::soc::cpu_control::*; /// Available CPU cores @@ -86,3 +87,103 @@ pub(crate) fn raw_core() -> usize { } } } + +use crate::rtc_cntl::SocResetReason; + +/// Source of the wakeup event +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[instability::unstable] +pub enum SleepSource { + /// In case of deep sleep, reset was not caused by exit from deep sleep + Undefined = 0, + /// Not a wakeup cause, used to disable all wakeup sources with + /// esp_sleep_disable_wakeup_source + All, + /// Wakeup caused by external signal using RTC_IO + Ext0, + /// Wakeup caused by external signal using RTC_CNTL + Ext1, + /// Wakeup caused by timer + Timer, + /// Wakeup caused by touchpad + TouchPad, + /// Wakeup caused by ULP program + Ulp, + /// Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3) + Gpio, + /// Wakeup caused by UART (light sleep only) + Uart, + /// Wakeup caused by WIFI (light sleep only) + Wifi, + /// Wakeup caused by COCPU int + Cocpu, + /// Wakeup caused by COCPU crash + CocpuTrapTrig, + /// Wakeup caused by BT (light sleep only) + BT, +} + +bitflags::bitflags! { + #[allow(unused)] + pub(crate) struct WakeupReason: u32 { + const NoSleep = 0; + #[cfg(pm_support_ext0_wakeup)] + /// EXT0 GPIO wakeup + const ExtEvent0Trig = 1 << 0; + #[cfg(pm_support_ext1_wakeup)] + /// EXT1 GPIO wakeup + const ExtEvent1Trig = 1 << 1; + /// GPIO wakeup (light sleep only) + const GpioTrigEn = 1 << 2; + #[cfg(not(any(esp32c6, esp32h2)))] + /// Timer wakeup + const TimerTrigEn = 1 << 3; + #[cfg(any(esp32c6, esp32h2))] + /// Timer wakeup + const TimerTrigEn = 1 << 4; + #[cfg(pm_support_wifi_wakeup)] + /// MAC wakeup (light sleep only) + const WifiTrigEn = 1 << 5; + /// UART0 wakeup (light sleep only) + const Uart0TrigEn = 1 << 6; + /// UART1 wakeup (light sleep only) + const Uart1TrigEn = 1 << 7; + #[cfg(pm_support_touch_sensor_wakeup)] + /// Touch wakeup + const TouchTrigEn = 1 << 8; + #[cfg(ulp_supported)] + /// ULP wakeup + const UlpTrigEn = 1 << 9; + #[cfg(pm_support_bt_wakeup)] + /// BT wakeup (light sleep only) + const BtTrigEn = 1 << 10; + #[cfg(riscv_coproc_supported)] + const CocpuTrigEn = 1 << 11; + #[cfg(riscv_coproc_supported)] + const CocpuTrapTrigEn = 1 << 13; + } +} + +/// Performs a software reset on the chip. +pub fn software_reset() { + crate::rom::software_reset(); +} + +/// Performs a software reset on the CPU. +pub fn software_reset_cpu() { + crate::rom::software_reset_cpu(); +} + +/// Retrieves the reason for the last reset as a SocResetReason enum value. +/// Returns `None` if the reset reason cannot be determined. +#[instability::unstable] +pub fn reset_reason() -> Option { + crate::rtc_cntl::reset_reason(crate::cpu::Cpu::current()) +} + +/// Retrieves the cause of the last wakeup event as a SleepSource enum value. +#[instability::unstable] +pub fn wakeup_cause() -> SleepSource { + crate::rtc_cntl::wakeup_cause() +} diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index 78e47b20db1..7dcd46e7958 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -261,8 +261,6 @@ unstable_module! { pub mod parl_io; #[cfg(pcnt)] pub mod pcnt; - #[cfg(any(lp_clkrst, rtc_cntl))] - pub mod reset; #[cfg(rmt)] pub mod rmt; #[cfg(rng)] diff --git a/esp-hal/src/reset.rs b/esp-hal/src/reset.rs deleted file mode 100644 index 900a45c31c0..00000000000 --- a/esp-hal/src/reset.rs +++ /dev/null @@ -1,112 +0,0 @@ -//! # Hardware and Software Reset -//! -//! ## Overview -//! Espressif chips provide four types of reset that occur at different levels, -//! namely CPU Reset, Core Reset, System Reset, and Chip Reset. All reset types -//! mentioned above (except Chip Reset) preserve the data stored in internal -//! memory. -//! -//! The Hardware and Software Reset module provides functions for -//! performing hardware and software resets and includes functions for -//! retrieving the reset reason and the wakeup cause after a reset. -//! -//! The module defines a set of sleep sources (`SleepSource`) that indicate the -//! source of the wakeup event. It also includes a set of flags (`WakeupReason`) -//! that represent different wakeup sources and enable/disable wakeup triggers -//! for specific events. - -use crate::rtc_cntl::SocResetReason; - -/// Source of the wakeup event -#[derive(Debug, Copy, Clone)] -pub enum SleepSource { - /// In case of deep sleep, reset was not caused by exit from deep sleep - Undefined = 0, - /// Not a wakeup cause, used to disable all wakeup sources with - /// esp_sleep_disable_wakeup_source - All, - /// Wakeup caused by external signal using RTC_IO - Ext0, - /// Wakeup caused by external signal using RTC_CNTL - Ext1, - /// Wakeup caused by timer - Timer, - /// Wakeup caused by touchpad - TouchPad, - /// Wakeup caused by ULP program - Ulp, - /// Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3) - Gpio, - /// Wakeup caused by UART (light sleep only) - Uart, - /// Wakeup caused by WIFI (light sleep only) - Wifi, - /// Wakeup caused by COCPU int - Cocpu, - /// Wakeup caused by COCPU crash - CocpuTrapTrig, - /// Wakeup caused by BT (light sleep only) - BT, -} - -bitflags::bitflags! { - #[allow(unused)] - pub(crate) struct WakeupReason: u32 { - const NoSleep = 0; - #[cfg(pm_support_ext0_wakeup)] - /// EXT0 GPIO wakeup - const ExtEvent0Trig = 1 << 0; - #[cfg(pm_support_ext1_wakeup)] - /// EXT1 GPIO wakeup - const ExtEvent1Trig = 1 << 1; - /// GPIO wakeup (light sleep only) - const GpioTrigEn = 1 << 2; - #[cfg(not(any(esp32c6, esp32h2)))] - /// Timer wakeup - const TimerTrigEn = 1 << 3; - #[cfg(any(esp32c6, esp32h2))] - /// Timer wakeup - const TimerTrigEn = 1 << 4; - #[cfg(pm_support_wifi_wakeup)] - /// MAC wakeup (light sleep only) - const WifiTrigEn = 1 << 5; - /// UART0 wakeup (light sleep only) - const Uart0TrigEn = 1 << 6; - /// UART1 wakeup (light sleep only) - const Uart1TrigEn = 1 << 7; - #[cfg(pm_support_touch_sensor_wakeup)] - /// Touch wakeup - const TouchTrigEn = 1 << 8; - #[cfg(ulp_supported)] - /// ULP wakeup - const UlpTrigEn = 1 << 9; - #[cfg(pm_support_bt_wakeup)] - /// BT wakeup (light sleep only) - const BtTrigEn = 1 << 10; - #[cfg(riscv_coproc_supported)] - const CocpuTrigEn = 1 << 11; - #[cfg(riscv_coproc_supported)] - const CocpuTrapTrigEn = 1 << 13; - } -} - -/// Performs a software reset on the chip. -pub fn software_reset() { - crate::rom::software_reset(); -} - -/// Performs a software reset on the CPU. -pub fn software_reset_cpu() { - crate::rom::software_reset_cpu(); -} - -/// Retrieves the reason for the last reset as a SocResetReason enum value. -/// Returns `None` if the reset reason cannot be determined. -pub fn reset_reason() -> Option { - crate::rtc_cntl::reset_reason(crate::cpu::Cpu::current()) -} - -/// Retrieves the cause of the last wakeup event as a SleepSource enum value. -pub fn wakeup_cause() -> SleepSource { - crate::rtc_cntl::wakeup_cause() -} diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index e52c30f0180..304afa2b24f 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -123,11 +123,10 @@ use crate::efuse::Efuse; use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers}; use crate::{ clock::Clock, - cpu::Cpu, + cpu::{Cpu, SleepSource, WakeupReason}, interrupt::{self, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, - reset::{SleepSource, WakeupReason}, time::Duration, }; #[cfg(not(any(esp32c6, esp32h2)))] diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index fb13cbaef60..7b9c59ac072 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -106,7 +106,7 @@ pub enum Error { /// ```rust, no_run #[doc = crate::before_snippet!()] /// # use esp_hal::delay::Delay; -/// # use esp_hal::cpu_control::{CpuControl, Stack}; +/// # use esp_hal::cpu::{CpuControl, Stack}; /// # use core::{cell::RefCell, ptr::addr_of_mut}; /// # use critical_section::Mutex; /// # let delay = Delay::new(); diff --git a/esp-hal/src/soc/esp32/mod.rs b/esp-hal/src/soc/esp32/mod.rs index 8820fd3baf6..a6d6b414021 100644 --- a/esp-hal/src/soc/esp32/mod.rs +++ b/esp-hal/src/soc/esp32/mod.rs @@ -97,7 +97,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::reset::reset_reason(), + crate::cpu::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/esp-hal/src/soc/esp32s2/mod.rs b/esp-hal/src/soc/esp32s2/mod.rs index 1437d851d5e..248137f7b85 100644 --- a/esp-hal/src/soc/esp32s2/mod.rs +++ b/esp-hal/src/soc/esp32s2/mod.rs @@ -101,7 +101,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::reset::reset_reason(), + crate::cpu::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index 915e8a653ba..ef36d66eb7b 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -107,7 +107,7 @@ pub enum Error { /// ```rust, no_run #[doc = crate::before_snippet!()] /// # use esp_hal::delay::Delay; -/// # use esp_hal::cpu_control::{CpuControl, Stack}; +/// # use esp_hal::cpu::{CpuControl, Stack}; /// # use core::{cell::RefCell, ptr::addr_of_mut}; /// # use critical_section::Mutex; /// # let delay = Delay::new(); diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs index a9d76c61cca..8e7d4b9d4a3 100644 --- a/esp-hal/src/soc/esp32s3/mod.rs +++ b/esp-hal/src/soc/esp32s3/mod.rs @@ -140,7 +140,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::reset::reset_reason(), + crate::cpu::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/examples/src/bin/ieee802154_sniffer.rs b/examples/src/bin/ieee802154_sniffer.rs index e33d8845bbb..ebd556663dd 100644 --- a/examples/src/bin/ieee802154_sniffer.rs +++ b/examples/src/bin/ieee802154_sniffer.rs @@ -10,8 +10,8 @@ use esp_backtrace as _; use esp_hal::{ + cpu::software_reset, main, - reset::software_reset, uart::{self, Uart}, }; use esp_ieee802154::{Config, Ieee802154}; From 148d1043a6cb14b4202bbcb13e3e0da3c00ec757 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 13:03:36 +0100 Subject: [PATCH 06/13] Fix software_reset_cpu --- esp-hal/src/cpu.rs | 9 +++++---- esp-hal/src/rom/mod.rs | 6 +++--- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index f843bafd0cb..66d2dc0d1e6 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -170,16 +170,17 @@ pub fn software_reset() { crate::rom::software_reset(); } -/// Performs a software reset on the CPU. -pub fn software_reset_cpu() { - crate::rom::software_reset_cpu(); +/// Resets the given CPU, leaving peripherals unchanged. +#[instability::unstable] +pub fn software_reset_cpu(cpu: Cpu) { + crate::rom::software_reset_cpu(cpu as u32); } /// Retrieves the reason for the last reset as a SocResetReason enum value. /// Returns `None` if the reset reason cannot be determined. #[instability::unstable] pub fn reset_reason() -> Option { - crate::rtc_cntl::reset_reason(crate::cpu::Cpu::current()) + crate::rtc_cntl::reset_reason(Cpu::current()) } /// Retrieves the cause of the last wakeup event as a SleepSource enum value. diff --git a/esp-hal/src/rom/mod.rs b/esp-hal/src/rom/mod.rs index bcf681c3f98..1ce2e0451ff 100644 --- a/esp-hal/src/rom/mod.rs +++ b/esp-hal/src/rom/mod.rs @@ -113,12 +113,12 @@ pub(crate) fn rtc_get_reset_reason(cpu_num: u32) -> u32 { } #[inline(always)] -pub(crate) fn software_reset_cpu() { +pub(crate) fn software_reset_cpu(cpu_num: u32) { extern "C" { - fn software_reset_cpu(); + fn software_reset_cpu(cpu_num: u32); } - unsafe { software_reset_cpu() }; + unsafe { software_reset_cpu(cpu_num) }; } #[inline(always)] From a1a12aec45c293e30d845fa056142954a5026d86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 13:04:03 +0100 Subject: [PATCH 07/13] Allow inlining cpu functions --- esp-hal/src/cpu.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index 66d2dc0d1e6..28b6409974f 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -166,12 +166,14 @@ bitflags::bitflags! { } /// Performs a software reset on the chip. +#[inline] pub fn software_reset() { crate::rom::software_reset(); } /// Resets the given CPU, leaving peripherals unchanged. #[instability::unstable] +#[inline] pub fn software_reset_cpu(cpu: Cpu) { crate::rom::software_reset_cpu(cpu as u32); } @@ -179,12 +181,14 @@ pub fn software_reset_cpu(cpu: Cpu) { /// Retrieves the reason for the last reset as a SocResetReason enum value. /// Returns `None` if the reset reason cannot be determined. #[instability::unstable] +#[inline] pub fn reset_reason() -> Option { crate::rtc_cntl::reset_reason(Cpu::current()) } /// Retrieves the cause of the last wakeup event as a SleepSource enum value. #[instability::unstable] +#[inline] pub fn wakeup_cause() -> SleepSource { crate::rtc_cntl::wakeup_cause() } From 93ed97e535d15908c9ede211b4abe5fbd54c9130 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 13:06:40 +0100 Subject: [PATCH 08/13] Changelog --- esp-hal/CHANGELOG.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index e19bda92001..92aa8155ab8 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -40,6 +40,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Removed features `psram-quad` and `psram-octal` - replaced by `psram` and the `ESP_HAL_CONFIG_PSRAM_MODE` (`quad`/`octal`) (#3001) - The `esp_hal::time` module no longer reexports `fugit` types (#3083) - The `system::RadioClockController` trait has been replaced by the `clock::RadioClockController` struct. (#3100) +- The `Cpu` struct and contents of the `reset` and `cpu_control` modules have been moved into `cpu`. (#) +- The `software_reset_cpu` now takes which CPU to reset as parameter. (#) - I2C: Async functions are postfixed with `_async`, non-async functions are available in async-mode (#3056) From 82cc03ce2e1b485b4ac53e19abc7856919f9fede Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 5 Feb 2025 13:53:25 +0100 Subject: [PATCH 09/13] Mark software_reset no-return --- esp-hal/src/cpu.rs | 6 +++--- esp-hal/src/rom/mod.rs | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index 28b6409974f..ccbab42fb81 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -167,15 +167,15 @@ bitflags::bitflags! { /// Performs a software reset on the chip. #[inline] -pub fn software_reset() { - crate::rom::software_reset(); +pub fn software_reset() -> ! { + crate::rom::software_reset() } /// Resets the given CPU, leaving peripherals unchanged. #[instability::unstable] #[inline] pub fn software_reset_cpu(cpu: Cpu) { - crate::rom::software_reset_cpu(cpu as u32); + crate::rom::software_reset_cpu(cpu as u32) } /// Retrieves the reason for the last reset as a SocResetReason enum value. diff --git a/esp-hal/src/rom/mod.rs b/esp-hal/src/rom/mod.rs index 1ce2e0451ff..5dc0b59bbe5 100644 --- a/esp-hal/src/rom/mod.rs +++ b/esp-hal/src/rom/mod.rs @@ -122,12 +122,12 @@ pub(crate) fn software_reset_cpu(cpu_num: u32) { } #[inline(always)] -pub(crate) fn software_reset() { +pub(crate) fn software_reset() -> ! { extern "C" { - fn software_reset(); + fn software_reset() -> !; } - unsafe { software_reset() }; + unsafe { software_reset() } } #[cfg(esp32s3)] From e4d5da415a7a3c782fd500fc04a1e7e7c01cf42d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 6 Feb 2025 16:12:56 +0100 Subject: [PATCH 10/13] Move WakeupReason --- esp-hal/src/cpu.rs | 41 ----------------------------------- esp-hal/src/rtc_cntl/mod.rs | 43 ++++++++++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs index ccbab42fb81..2a8f8d96edc 100644 --- a/esp-hal/src/cpu.rs +++ b/esp-hal/src/cpu.rs @@ -124,47 +124,6 @@ pub enum SleepSource { BT, } -bitflags::bitflags! { - #[allow(unused)] - pub(crate) struct WakeupReason: u32 { - const NoSleep = 0; - #[cfg(pm_support_ext0_wakeup)] - /// EXT0 GPIO wakeup - const ExtEvent0Trig = 1 << 0; - #[cfg(pm_support_ext1_wakeup)] - /// EXT1 GPIO wakeup - const ExtEvent1Trig = 1 << 1; - /// GPIO wakeup (light sleep only) - const GpioTrigEn = 1 << 2; - #[cfg(not(any(esp32c6, esp32h2)))] - /// Timer wakeup - const TimerTrigEn = 1 << 3; - #[cfg(any(esp32c6, esp32h2))] - /// Timer wakeup - const TimerTrigEn = 1 << 4; - #[cfg(pm_support_wifi_wakeup)] - /// MAC wakeup (light sleep only) - const WifiTrigEn = 1 << 5; - /// UART0 wakeup (light sleep only) - const Uart0TrigEn = 1 << 6; - /// UART1 wakeup (light sleep only) - const Uart1TrigEn = 1 << 7; - #[cfg(pm_support_touch_sensor_wakeup)] - /// Touch wakeup - const TouchTrigEn = 1 << 8; - #[cfg(ulp_supported)] - /// ULP wakeup - const UlpTrigEn = 1 << 9; - #[cfg(pm_support_bt_wakeup)] - /// BT wakeup (light sleep only) - const BtTrigEn = 1 << 10; - #[cfg(riscv_coproc_supported)] - const CocpuTrigEn = 1 << 11; - #[cfg(riscv_coproc_supported)] - const CocpuTrapTrigEn = 1 << 13; - } -} - /// Performs a software reset on the chip. #[inline] pub fn software_reset() -> ! { diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index 304afa2b24f..b65aef1ba0d 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -123,7 +123,7 @@ use crate::efuse::Efuse; use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers}; use crate::{ clock::Clock, - cpu::{Cpu, SleepSource, WakeupReason}, + cpu::{Cpu, SleepSource}, interrupt::{self, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, @@ -159,6 +159,47 @@ cfg_if::cfg_if! { } } +bitflags::bitflags! { + #[allow(unused)] + struct WakeupReason: u32 { + const NoSleep = 0; + #[cfg(pm_support_ext0_wakeup)] + /// EXT0 GPIO wakeup + const ExtEvent0Trig = 1 << 0; + #[cfg(pm_support_ext1_wakeup)] + /// EXT1 GPIO wakeup + const ExtEvent1Trig = 1 << 1; + /// GPIO wakeup (light sleep only) + const GpioTrigEn = 1 << 2; + #[cfg(not(any(esp32c6, esp32h2)))] + /// Timer wakeup + const TimerTrigEn = 1 << 3; + #[cfg(any(esp32c6, esp32h2))] + /// Timer wakeup + const TimerTrigEn = 1 << 4; + #[cfg(pm_support_wifi_wakeup)] + /// MAC wakeup (light sleep only) + const WifiTrigEn = 1 << 5; + /// UART0 wakeup (light sleep only) + const Uart0TrigEn = 1 << 6; + /// UART1 wakeup (light sleep only) + const Uart1TrigEn = 1 << 7; + #[cfg(pm_support_touch_sensor_wakeup)] + /// Touch wakeup + const TouchTrigEn = 1 << 8; + #[cfg(ulp_supported)] + /// ULP wakeup + const UlpTrigEn = 1 << 9; + #[cfg(pm_support_bt_wakeup)] + /// BT wakeup (light sleep only) + const BtTrigEn = 1 << 10; + #[cfg(riscv_coproc_supported)] + const CocpuTrigEn = 1 << 11; + #[cfg(riscv_coproc_supported)] + const CocpuTrapTrigEn = 1 << 13; + } +} + #[cfg(not(any(esp32c6, esp32h2)))] #[allow(unused)] #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] From f9c2b243f2fa7c8662dee25ca8c1737a42091808 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 6 Feb 2025 16:21:44 +0100 Subject: [PATCH 11/13] Remove PeripheralIter --- esp-hal/src/system.rs | 110 +++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 18 deletions(-) diff --git a/esp-hal/src/system.rs b/esp-hal/src/system.rs index 1c6465abf38..7b47a2f9b87 100755 --- a/esp-hal/src/system.rs +++ b/esp-hal/src/system.rs @@ -3,19 +3,9 @@ use core::cell::RefCell; use critical_section::{CriticalSection, Mutex}; -use strum::{EnumCount, EnumIter, IntoEnumIterator}; use crate::peripherals::SYSTEM; -pub(crate) const KEEP_ENABLED: &[Peripheral] = &[ - Peripheral::Uart0, - #[cfg(usb_device)] - Peripheral::UsbDevice, - #[cfg(systimer)] - Peripheral::Systimer, - Peripheral::Timg0, -]; - /// Peripherals which can be enabled via `PeripheralClockControl`. /// /// This enum represents various hardware peripherals that can be enabled @@ -24,7 +14,7 @@ pub(crate) const KEEP_ENABLED: &[Peripheral] = &[ // FIXME: This enum needs to be public because it's exposed via a bunch of traits, but it's not // useful to users. #[doc(hidden)] -#[derive(Debug, Clone, Copy, PartialEq, Eq, EnumCount, EnumIter)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u8)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Peripheral { @@ -132,6 +122,90 @@ pub enum Peripheral { Tsens, } +impl Peripheral { + const KEEP_ENABLED: &[Peripheral] = &[ + Peripheral::Uart0, + #[cfg(usb_device)] + Peripheral::UsbDevice, + #[cfg(systimer)] + Peripheral::Systimer, + Peripheral::Timg0, + ]; + + const COUNT: usize = Self::ALL.len(); + + const ALL: &[Self] = &[ + #[cfg(spi2)] + Self::Spi2, + #[cfg(spi3)] + Self::Spi3, + #[cfg(i2c0)] + Self::I2cExt0, + #[cfg(i2c1)] + Self::I2cExt1, + #[cfg(rmt)] + Self::Rmt, + #[cfg(ledc)] + Self::Ledc, + #[cfg(mcpwm0)] + Self::Mcpwm0, + #[cfg(mcpwm1)] + Self::Mcpwm1, + #[cfg(pcnt)] + Self::Pcnt, + #[cfg(apb_saradc)] + Self::ApbSarAdc, + #[cfg(gdma)] + Self::Gdma, + #[cfg(pdma)] + Self::Dma, + #[cfg(i2s0)] + Self::I2s0, + #[cfg(i2s1)] + Self::I2s1, + #[cfg(usb0)] + Self::Usb, + #[cfg(aes)] + Self::Aes, + #[cfg(twai0)] + Self::Twai0, + #[cfg(twai1)] + Self::Twai1, + #[cfg(timg0)] + Self::Timg0, + #[cfg(timg1)] + Self::Timg1, + #[cfg(sha)] + Self::Sha, + #[cfg(usb_device)] + Self::UsbDevice, + #[cfg(uart0)] + Self::Uart0, + #[cfg(uart1)] + Self::Uart1, + #[cfg(uart2)] + Self::Uart2, + #[cfg(rsa)] + Self::Rsa, + #[cfg(parl_io)] + Self::ParlIo, + #[cfg(hmac)] + Self::Hmac, + #[cfg(ecc)] + Self::Ecc, + #[cfg(soc_etm)] + Self::Etm, + #[cfg(trace0)] + Self::Trace0, + #[cfg(lcd_cam)] + Self::LcdCam, + #[cfg(systimer)] + Self::Systimer, + #[cfg(tsens)] + Self::Tsens, + ]; +} + impl Peripheral { pub fn try_from(value: u8) -> Option { if value >= Peripheral::COUNT as u8 { @@ -151,11 +225,11 @@ static PERIPHERAL_REF_COUNT: Mutex> = pub(crate) fn disable_peripherals() { // Take the critical section up front to avoid taking it multiple times. critical_section::with(|cs| { - for p in Peripheral::iter() { - if KEEP_ENABLED.contains(&p) { + for p in Peripheral::ALL { + if Peripheral::KEEP_ENABLED.contains(p) { continue; } - PeripheralClockControl::enable_forced_with_cs(p, false, true, cs); + PeripheralClockControl::enable_forced_with_cs(*p, false, true, cs); } }) } @@ -168,7 +242,7 @@ pub(crate) struct PeripheralGuard { impl PeripheralGuard { pub(crate) fn new_with(p: Peripheral, init: fn()) -> Self { - if !KEEP_ENABLED.contains(&p) && PeripheralClockControl::enable(p) { + if !Peripheral::KEEP_ENABLED.contains(&p) && PeripheralClockControl::enable(p) { PeripheralClockControl::reset(p); init(); } @@ -183,7 +257,7 @@ impl PeripheralGuard { impl Drop for PeripheralGuard { fn drop(&mut self) { - if !KEEP_ENABLED.contains(&self.peripheral) { + if !Peripheral::KEEP_ENABLED.contains(&self.peripheral) { PeripheralClockControl::disable(self.peripheral); } } @@ -197,7 +271,7 @@ impl GenericPeripheralGuard

{ pub(crate) fn new_with(init: fn(CriticalSection<'_>)) -> Self { let peripheral = unwrap!(Peripheral::try_from(P)); critical_section::with(|cs| { - if !KEEP_ENABLED.contains(&peripheral) + if !Peripheral::KEEP_ENABLED.contains(&peripheral) && PeripheralClockControl::enable_with_cs(peripheral, cs) { PeripheralClockControl::reset(peripheral); @@ -216,7 +290,7 @@ impl GenericPeripheralGuard

{ impl Drop for GenericPeripheralGuard

{ fn drop(&mut self) { let peripheral = unwrap!(Peripheral::try_from(P)); - if !KEEP_ENABLED.contains(&peripheral) { + if !Peripheral::KEEP_ENABLED.contains(&peripheral) { PeripheralClockControl::disable(peripheral); } } From 8250a8e6ab1b81598b6413f39ae613227d95b6c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 6 Feb 2025 16:23:08 +0100 Subject: [PATCH 12/13] Move cpu into system --- esp-hal-embassy/src/executor/interrupt.rs | 2 +- esp-hal-embassy/src/executor/thread.rs | 2 +- esp-hal/src/analog/adc/riscv.rs | 4 +- esp-hal/src/assist_debug.rs | 2 +- esp-hal/src/cpu.rs | 153 ------------------ esp-hal/src/dma/mod.rs | 6 +- esp-hal/src/ecc.rs | 2 +- esp-hal/src/gpio/mod.rs | 5 +- esp-hal/src/i2c/master/mod.rs | 4 +- esp-hal/src/i2s/master.rs | 4 +- esp-hal/src/interrupt/riscv.rs | 6 +- esp-hal/src/interrupt/software.rs | 2 +- esp-hal/src/interrupt/xtensa.rs | 2 +- esp-hal/src/lcd_cam/mod.rs | 5 +- esp-hal/src/lib.rs | 1 - esp-hal/src/otg_fs.rs | 2 +- esp-hal/src/parl_io.rs | 10 +- esp-hal/src/pcnt/mod.rs | 2 +- esp-hal/src/rmt.rs | 2 +- esp-hal/src/rsa/mod.rs | 5 +- esp-hal/src/rtc_cntl/mod.rs | 4 +- esp-hal/src/rtc_cntl/sleep/mod.rs | 10 +- esp-hal/src/sha.rs | 2 +- esp-hal/src/soc/esp32/cpu_control.rs | 4 +- esp-hal/src/soc/esp32/gpio.rs | 2 +- esp-hal/src/soc/esp32/mod.rs | 2 +- esp-hal/src/soc/esp32s2/mod.rs | 2 +- esp-hal/src/soc/esp32s3/cpu_control.rs | 4 +- esp-hal/src/soc/esp32s3/mod.rs | 2 +- esp-hal/src/spi/master.rs | 5 +- esp-hal/src/sync.rs | 2 +- esp-hal/src/system.rs | 152 +++++++++++++++++ esp-hal/src/timer/mod.rs | 2 +- esp-hal/src/timer/systimer.rs | 5 +- esp-hal/src/timer/timg.rs | 2 +- esp-hal/src/twai/mod.rs | 5 +- esp-hal/src/uart.rs | 4 +- esp-hal/src/usb_serial_jtag.rs | 5 +- esp-wifi/src/ble/os_adapter_esp32s3.rs | 2 +- esp-wifi/src/preempt/timer/riscv.rs | 2 +- esp-wifi/src/radio/radio_esp32.rs | 17 +- esp-wifi/src/radio/radio_esp32c2.rs | 4 +- esp-wifi/src/radio/radio_esp32c3.rs | 6 +- esp-wifi/src/radio/radio_esp32c6.rs | 4 +- esp-wifi/src/radio/radio_esp32h2.rs | 4 +- esp-wifi/src/radio/radio_esp32s3.rs | 4 +- examples/src/bin/embassy_multicore.rs | 2 +- .../src/bin/embassy_multicore_interrupt.rs | 2 +- examples/src/bin/ieee802154_sniffer.rs | 2 +- hil-test/tests/embassy_interrupt_executor.rs | 2 +- hil-test/tests/embassy_interrupt_spi_dma.rs | 2 +- hil-test/tests/esp_wifi_floats.rs | 2 +- qa-test/src/bin/sleep_timer.rs | 2 +- qa-test/src/bin/sleep_timer_ext0.rs | 2 +- qa-test/src/bin/sleep_timer_ext1.rs | 2 +- qa-test/src/bin/sleep_timer_lpio.rs | 2 +- qa-test/src/bin/sleep_timer_rtcio.rs | 2 +- 57 files changed, 251 insertions(+), 249 deletions(-) delete mode 100644 esp-hal/src/cpu.rs diff --git a/esp-hal-embassy/src/executor/interrupt.rs b/esp-hal-embassy/src/executor/interrupt.rs index c32bf5fa69d..2bf8efa3353 100644 --- a/esp-hal-embassy/src/executor/interrupt.rs +++ b/esp-hal-embassy/src/executor/interrupt.rs @@ -4,8 +4,8 @@ use core::{cell::UnsafeCell, mem::MaybeUninit}; use embassy_executor::SendSpawner; use esp_hal::{ - cpu::Cpu, interrupt::{self, software::SoftwareInterrupt, InterruptHandler}, + system::Cpu, }; use portable_atomic::{AtomicUsize, Ordering}; diff --git a/esp-hal-embassy/src/executor/thread.rs b/esp-hal-embassy/src/executor/thread.rs index 14b60d5c1be..5ec9810ab92 100644 --- a/esp-hal-embassy/src/executor/thread.rs +++ b/esp-hal-embassy/src/executor/thread.rs @@ -5,7 +5,7 @@ use core::marker::PhantomData; use embassy_executor::Spawner; #[cfg(all(low_power_wait, multi_core))] use esp_hal::interrupt::software::SoftwareInterrupt; -use esp_hal::{cpu::Cpu, interrupt::Priority}; +use esp_hal::{interrupt::Priority, system::Cpu}; #[cfg(low_power_wait)] use portable_atomic::{AtomicBool, Ordering}; diff --git a/esp-hal/src/analog/adc/riscv.rs b/esp-hal/src/analog/adc/riscv.rs index 34ad588f71d..b9f088ecaac 100644 --- a/esp-hal/src/analog/adc/riscv.rs +++ b/esp-hal/src/analog/adc/riscv.rs @@ -534,7 +534,7 @@ impl crate::private::Sealed for Adc<'_, ADCI, Blocking> {} impl InterruptConfigurable for Adc<'_, ADCI, Blocking> { fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, InterruptSource); } unsafe { crate::interrupt::bind_interrupt(InterruptSource, handler.handler()) }; @@ -643,7 +643,7 @@ where pub fn into_blocking(self) -> Adc<'d, ADCI, Blocking> { if asynch::release_async_adc() { // Disable ADC interrupt on all cores if the last async ADC instance is disabled - for cpu in crate::cpu::Cpu::all() { + for cpu in crate::system::Cpu::all() { crate::interrupt::disable(cpu, InterruptSource); } } diff --git a/esp-hal/src/assist_debug.rs b/esp-hal/src/assist_debug.rs index 586635ac714..185b4e5d079 100644 --- a/esp-hal/src/assist_debug.rs +++ b/esp-hal/src/assist_debug.rs @@ -52,7 +52,7 @@ impl<'d> DebugAssist<'d> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::ASSIST_DEBUG); } unsafe { crate::interrupt::bind_interrupt(Interrupt::ASSIST_DEBUG, handler.handler()) }; diff --git a/esp-hal/src/cpu.rs b/esp-hal/src/cpu.rs deleted file mode 100644 index 2a8f8d96edc..00000000000 --- a/esp-hal/src/cpu.rs +++ /dev/null @@ -1,153 +0,0 @@ -//! CPU related functionality - -#[cfg(any(esp32, esp32s3))] -#[allow(unused_imports)] -pub use crate::soc::cpu_control::*; - -/// Available CPU cores -/// -/// The actual number of available cores depends on the target. -#[derive(Debug, Copy, Clone, PartialEq, Eq, strum::FromRepr)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[repr(C)] -pub enum Cpu { - /// The first core - ProCpu = 0, - /// The second core - #[cfg(multi_core)] - AppCpu = 1, -} - -impl Cpu { - /// The number of available cores. - pub const COUNT: usize = 1 + cfg!(multi_core) as usize; - - /// Returns the core the application is currently executing on - #[inline(always)] - pub fn current() -> Self { - // This works for both RISCV and Xtensa because both - // get_raw_core functions return zero, _or_ something - // greater than zero; 1 in the case of RISCV and 0x2000 - // in the case of Xtensa. - match raw_core() { - 0 => Cpu::ProCpu, - #[cfg(all(multi_core, riscv))] - 1 => Cpu::AppCpu, - #[cfg(all(multi_core, xtensa))] - 0x2000 => Cpu::AppCpu, - _ => unreachable!(), - } - } - - /// Returns an iterator over the "other" cores. - #[inline(always)] - pub(crate) fn other() -> impl Iterator { - cfg_if::cfg_if! { - if #[cfg(multi_core)] { - match Self::current() { - Cpu::ProCpu => [Cpu::AppCpu].into_iter(), - Cpu::AppCpu => [Cpu::ProCpu].into_iter(), - } - } else { - [].into_iter() - } - } - } - - /// Returns an iterator over all cores. - #[inline(always)] - pub(crate) fn all() -> impl Iterator { - cfg_if::cfg_if! { - if #[cfg(multi_core)] { - [Cpu::ProCpu, Cpu::AppCpu].into_iter() - } else { - [Cpu::ProCpu].into_iter() - } - } - } -} - -/// Returns the raw value of the mhartid register. -/// -/// On RISC-V, this is the hardware thread ID. -/// -/// On Xtensa, this returns the result of reading the PRID register logically -/// ANDed with 0x2000, the 13th bit in the register. Espressif Xtensa chips use -/// this bit to determine the core id. -#[inline(always)] -pub(crate) fn raw_core() -> usize { - // This method must never return UNUSED_THREAD_ID_VALUE - cfg_if::cfg_if! { - if #[cfg(all(multi_core, riscv))] { - riscv::register::mhartid::read() - } else if #[cfg(all(multi_core, xtensa))] { - (xtensa_lx::get_processor_id() & 0x2000) as usize - } else { - 0 - } - } -} - -use crate::rtc_cntl::SocResetReason; - -/// Source of the wakeup event -#[derive(Debug, Copy, Clone)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[instability::unstable] -pub enum SleepSource { - /// In case of deep sleep, reset was not caused by exit from deep sleep - Undefined = 0, - /// Not a wakeup cause, used to disable all wakeup sources with - /// esp_sleep_disable_wakeup_source - All, - /// Wakeup caused by external signal using RTC_IO - Ext0, - /// Wakeup caused by external signal using RTC_CNTL - Ext1, - /// Wakeup caused by timer - Timer, - /// Wakeup caused by touchpad - TouchPad, - /// Wakeup caused by ULP program - Ulp, - /// Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3) - Gpio, - /// Wakeup caused by UART (light sleep only) - Uart, - /// Wakeup caused by WIFI (light sleep only) - Wifi, - /// Wakeup caused by COCPU int - Cocpu, - /// Wakeup caused by COCPU crash - CocpuTrapTrig, - /// Wakeup caused by BT (light sleep only) - BT, -} - -/// Performs a software reset on the chip. -#[inline] -pub fn software_reset() -> ! { - crate::rom::software_reset() -} - -/// Resets the given CPU, leaving peripherals unchanged. -#[instability::unstable] -#[inline] -pub fn software_reset_cpu(cpu: Cpu) { - crate::rom::software_reset_cpu(cpu as u32) -} - -/// Retrieves the reason for the last reset as a SocResetReason enum value. -/// Returns `None` if the reset reason cannot be determined. -#[instability::unstable] -#[inline] -pub fn reset_reason() -> Option { - crate::rtc_cntl::reset_reason(Cpu::current()) -} - -/// Retrieves the cause of the last wakeup event as a SleepSource enum value. -#[instability::unstable] -#[inline] -pub fn wakeup_cause() -> SleepSource { - crate::rtc_cntl::wakeup_cause() -} diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs index 0deb80f723d..ab7a4cb34ee 100644 --- a/esp-hal/src/dma/mod.rs +++ b/esp-hal/src/dma/mod.rs @@ -61,12 +61,12 @@ pub use self::m2m::*; #[cfg(pdma)] pub use self::pdma::*; use crate::{ - cpu::Cpu, interrupt::InterruptHandler, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, soc::{is_slice_in_dram, is_valid_memory_address, is_valid_ram_address}, system, + system::Cpu, Async, Blocking, DriverMode, @@ -1873,7 +1873,7 @@ where self.clear_in(EnumSet::all()); if let Some(interrupt) = self.rx_impl.peripheral_interrupt() { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; @@ -2168,7 +2168,7 @@ where self.clear_out(EnumSet::all()); if let Some(interrupt) = self.tx_impl.peripheral_interrupt() { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/ecc.rs b/esp-hal/src/ecc.rs index 71dbb6bbabd..efa7af1160e 100644 --- a/esp-hal/src/ecc.rs +++ b/esp-hal/src/ecc.rs @@ -992,7 +992,7 @@ impl Ecc<'_, Dm> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::ECC); } unsafe { crate::interrupt::bind_interrupt(Interrupt::ECC, handler.handler()) }; diff --git a/esp-hal/src/gpio/mod.rs b/esp-hal/src/gpio/mod.rs index a421bedfe77..e3189072b5e 100644 --- a/esp-hal/src/gpio/mod.rs +++ b/esp-hal/src/gpio/mod.rs @@ -717,7 +717,8 @@ pub(crate) fn bind_default_interrupt_handler() { } // The vector table doesn't contain a custom entry.Still, the // peripheral interrupt may already be bound to something else. - if interrupt::bound_cpu_interrupt_for(crate::cpu::Cpu::current(), Interrupt::GPIO).is_some() { + if interrupt::bound_cpu_interrupt_for(crate::system::Cpu::current(), Interrupt::GPIO).is_some() + { info!("Not using default GPIO interrupt handler: peripheral interrupt already in use"); return; } @@ -773,7 +774,7 @@ impl Io { /// `None`) #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::GPIO); } self.set_interrupt_priority(handler.priority()); diff --git a/esp-hal/src/i2c/master/mod.rs b/esp-hal/src/i2c/master/mod.rs index 9d78647c465..1d84cc571ee 100644 --- a/esp-hal/src/i2c/master/mod.rs +++ b/esp-hal/src/i2c/master/mod.rs @@ -1332,7 +1332,7 @@ impl Info { } fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, self.interrupt); } self.enable_listen(EnumSet::all(), false); @@ -1342,7 +1342,7 @@ impl Info { } fn disable_interrupts(&self) { - crate::interrupt::disable(crate::cpu::Cpu::current(), self.interrupt); + crate::interrupt::disable(crate::system::Cpu::current(), self.interrupt); } } diff --git a/esp-hal/src/i2s/master.rs b/esp-hal/src/i2s/master.rs index 6de8a067e81..ceabc9b0e9b 100644 --- a/esp-hal/src/i2s/master.rs +++ b/esp-hal/src/i2s/master.rs @@ -1518,7 +1518,7 @@ mod private { impl RegisterAccessPrivate for I2S0 { fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::I2S0); } unsafe { crate::peripherals::I2S0::steal() }.bind_i2s0_interrupt(handler.handler()); @@ -1627,7 +1627,7 @@ mod private { #[cfg(i2s1)] impl RegisterAccessPrivate for I2S1 { fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::I2S1); } unsafe { crate::peripherals::I2S1::steal() }.bind_i2s1_interrupt(handler.handler()); diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 430f5e1fd7c..c386eb34a4c 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -23,9 +23,9 @@ pub use self::plic::*; pub use self::vectored::*; use super::InterruptStatus; use crate::{ - cpu::Cpu, pac, peripherals::{Interrupt, INTERRUPT_CORE0}, + system::Cpu, }; /// Interrupt Error @@ -560,7 +560,7 @@ mod vectored { #[cfg(not(plic))] mod classic { use super::{CpuInterrupt, InterruptKind, Priority}; - use crate::{cpu::Cpu, peripherals::INTERRUPT_CORE0}; + use crate::{peripherals::INTERRUPT_CORE0, system::Cpu}; #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")] pub(super) static DISABLED_CPU_INTERRUPT: u32 = 0; @@ -710,7 +710,7 @@ mod classic { #[cfg(plic)] mod plic { use super::{CpuInterrupt, InterruptKind, Priority}; - use crate::{cpu::Cpu, peripherals::PLIC_MX}; + use crate::{peripherals::PLIC_MX, system::Cpu}; #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")] pub(super) static DISABLED_CPU_INTERRUPT: u32 = 31; diff --git a/esp-hal/src/interrupt/software.rs b/esp-hal/src/interrupt/software.rs index e6abc55604d..92e8a24a609 100644 --- a/esp-hal/src/interrupt/software.rs +++ b/esp-hal/src/interrupt/software.rs @@ -66,7 +66,7 @@ impl SoftwareInterrupt { _ => unreachable!(), }; - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/interrupt/xtensa.rs b/esp-hal/src/interrupt/xtensa.rs index fac161bbd1b..27b02ae2310 100644 --- a/esp-hal/src/interrupt/xtensa.rs +++ b/esp-hal/src/interrupt/xtensa.rs @@ -6,7 +6,7 @@ use xtensa_lx_rt::exception::Context; pub use self::vectored::*; use super::InterruptStatus; -use crate::{cpu::Cpu, pac, peripherals::Interrupt}; +use crate::{pac, peripherals::Interrupt, system::Cpu}; /// Interrupt Error #[derive(Copy, Clone, Debug, PartialEq, Eq)] diff --git a/esp-hal/src/lcd_cam/mod.rs b/esp-hal/src/lcd_cam/mod.rs index b93b2c7f689..44b3316170d 100644 --- a/esp-hal/src/lcd_cam/mod.rs +++ b/esp-hal/src/lcd_cam/mod.rs @@ -12,13 +12,12 @@ use core::marker::PhantomData; use crate::{ asynch::AtomicWaker, - cpu::Cpu, handler, interrupt::InterruptHandler, lcd_cam::{cam::Cam, lcd::Lcd}, peripheral::Peripheral, peripherals::{Interrupt, LCD_CAM}, - system::GenericPeripheralGuard, + system::{Cpu, GenericPeripheralGuard}, Async, Blocking, }; @@ -71,7 +70,7 @@ impl<'d> LcdCam<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::LCD_CAM); } unsafe { crate::interrupt::bind_interrupt(Interrupt::LCD_CAM, handler.handler()) }; diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index 7dcd46e7958..b7da01fe7d5 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -175,7 +175,6 @@ pub use self::soc::ulp_core; #[cfg(any(dport, hp_sys, pcr, system))] pub mod clock; -pub mod cpu; #[cfg(gpio)] pub mod gpio; #[cfg(any(i2c0, i2c1))] diff --git a/esp-hal/src/otg_fs.rs b/esp-hal/src/otg_fs.rs index 603d7620ac3..73ba0be6124 100644 --- a/esp-hal/src/otg_fs.rs +++ b/esp-hal/src/otg_fs.rs @@ -147,7 +147,7 @@ pub mod asynch { use procmacros::handler; use super::*; - use crate::cpu::Cpu; + use crate::system::Cpu; // From ESP32-S3 TRM: // Six additional endpoints (endpoint numbers 1 to 6), configurable as IN or OUT diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs index e030ea538c3..ee43fd62163 100644 --- a/esp-hal/src/parl_io.rs +++ b/esp-hal/src/parl_io.rs @@ -985,7 +985,7 @@ fn internal_set_interrupt_handler(handler: InterruptHandler) { let mut peri = unsafe { PARL_IO::steal() }; #[cfg(esp32c6)] { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::PARL_IO); } internal_listen(EnumSet::all(), false); @@ -999,7 +999,7 @@ fn internal_set_interrupt_handler(handler: InterruptHandler) { } #[cfg(esp32h2)] { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::PARL_IO_RX); crate::interrupt::disable(core, Interrupt::PARL_IO_TX); } @@ -1107,7 +1107,7 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> { /// Convert to an async version. pub fn into_async(self) -> ParlIoFullDuplex<'d, Async> { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); @@ -1244,7 +1244,7 @@ impl<'d> ParlIoTxOnly<'d, Blocking> { /// Converts to Async mode. pub fn into_async(self) -> ParlIoTxOnly<'d, Async> { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); @@ -1372,7 +1372,7 @@ impl<'d> ParlIoRxOnly<'d, Blocking> { /// Converts to Async mode. pub fn into_async(self) -> ParlIoRxOnly<'d, Async> { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { #[cfg(esp32c6)] { crate::interrupt::disable(core, Interrupt::PARL_IO); diff --git a/esp-hal/src/pcnt/mod.rs b/esp-hal/src/pcnt/mod.rs index dd3b56de5ac..28135c8f505 100644 --- a/esp-hal/src/pcnt/mod.rs +++ b/esp-hal/src/pcnt/mod.rs @@ -188,7 +188,7 @@ impl<'d> Pcnt<'d> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::PCNT); } unsafe { interrupt::bind_interrupt(Interrupt::PCNT, handler.handler()) }; diff --git a/esp-hal/src/rmt.rs b/esp-hal/src/rmt.rs index 12ec096c5ee..a5e85bb0252 100644 --- a/esp-hal/src/rmt.rs +++ b/esp-hal/src/rmt.rs @@ -449,7 +449,7 @@ impl<'d> Rmt<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::RMT); } unsafe { crate::interrupt::bind_interrupt(Interrupt::RMT, handler.handler()) }; diff --git a/esp-hal/src/rsa/mod.rs b/esp-hal/src/rsa/mod.rs index 697e7b0f005..96c8219711c 100644 --- a/esp-hal/src/rsa/mod.rs +++ b/esp-hal/src/rsa/mod.rs @@ -24,12 +24,11 @@ use core::{marker::PhantomData, ptr::copy_nonoverlapping}; use crate::{ - cpu::Cpu, interrupt::InterruptHandler, pac, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, RSA}, - system::{GenericPeripheralGuard, Peripheral as PeripheralEnable}, + system::{Cpu, GenericPeripheralGuard, Peripheral as PeripheralEnable}, Async, Blocking, }; @@ -75,7 +74,7 @@ impl<'d> Rsa<'d, Blocking> { /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::RSA); } unsafe { crate::interrupt::bind_interrupt(Interrupt::RSA, handler.handler()) }; diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index b65aef1ba0d..b4e84b46a48 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -123,10 +123,10 @@ use crate::efuse::Efuse; use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers}; use crate::{ clock::Clock, - cpu::{Cpu, SleepSource}, interrupt::{self, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, + system::{Cpu, SleepSource}, time::Duration, }; #[cfg(not(any(esp32c6, esp32h2)))] @@ -514,7 +514,7 @@ impl<'d> Rtc<'d> { let interrupt = Interrupt::RTC_CORE; } } - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/rtc_cntl/sleep/mod.rs b/esp-hal/src/rtc_cntl/sleep/mod.rs index 6207c194d22..362d043a5e6 100644 --- a/esp-hal/src/rtc_cntl/sleep/mod.rs +++ b/esp-hal/src/rtc_cntl/sleep/mod.rs @@ -56,7 +56,7 @@ pub enum WakeupLevel { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::TimerWakeupSource, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::cpu::Cpu; +/// # use esp_hal::system::Cpu; /// /// let delay = Delay::new(); /// let mut rtc = Rtc::new(peripherals.LPWR); @@ -104,7 +104,7 @@ pub enum Error { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext0WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::cpu::Cpu; +/// # use esp_hal::system::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull}; /// /// let delay = Delay::new(); @@ -157,7 +157,7 @@ impl<'a, P: RtcIoWakeupPinType> Ext0WakeupSource<'a, P> { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext1WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::cpu::Cpu; +/// # use esp_hal::system::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull, RtcPin}; /// # use esp_hal::peripheral::Peripheral; /// @@ -214,7 +214,7 @@ impl<'a, 'b> Ext1WakeupSource<'a, 'b> { /// # use core::time::Duration; /// # use esp_hal::delay::Delay; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{Ext1WakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::cpu::Cpu; +/// # use esp_hal::system::Cpu; /// # use esp_hal::gpio::{Input, InputConfig, Pull, RtcPinWithResistors}; /// # use esp_hal::peripheral::Peripheral; /// @@ -276,7 +276,7 @@ impl<'a, 'b> Ext1WakeupSource<'a, 'b> { /// # use esp_hal::delay::Delay; /// # use esp_hal::gpio::{self, Input, InputConfig, Pull}; /// # use esp_hal::rtc_cntl::{reset_reason, sleep::{RtcioWakeupSource, TimerWakeupSource, WakeupLevel}, wakeup_cause, Rtc, SocResetReason}; -/// # use esp_hal::cpu::Cpu; +/// # use esp_hal::system::Cpu; /// # use esp_hal::peripheral::Peripheral; /// /// let mut rtc = Rtc::new(peripherals.LPWR); diff --git a/esp-hal/src/sha.rs b/esp-hal/src/sha.rs index 3f3158c76a0..13e8fd618a8 100644 --- a/esp-hal/src/sha.rs +++ b/esp-hal/src/sha.rs @@ -111,7 +111,7 @@ impl crate::private::Sealed for Sha<'_> {} #[instability::unstable] impl crate::interrupt::InterruptConfigurable for Sha<'_> { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::SHA); } unsafe { crate::interrupt::bind_interrupt(Interrupt::SHA, handler.handler()) }; diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index 7b9c59ac072..b3774341561 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -11,9 +11,9 @@ use core::{ }; use crate::{ - cpu::Cpu, peripheral::{Peripheral, PeripheralRef}, peripherals::{CPU_CTRL, DPORT, LPWR, SPI0}, + system::Cpu, }; /// Data type for a properly aligned stack of N bytes @@ -106,7 +106,7 @@ pub enum Error { /// ```rust, no_run #[doc = crate::before_snippet!()] /// # use esp_hal::delay::Delay; -/// # use esp_hal::cpu::{CpuControl, Stack}; +/// # use esp_hal::system::{CpuControl, Stack}; /// # use core::{cell::RefCell, ptr::addr_of_mut}; /// # use critical_section::Mutex; /// # let delay = Delay::new(); diff --git a/esp-hal/src/soc/esp32/gpio.rs b/esp-hal/src/soc/esp32/gpio.rs index 38bb0d1dff5..b6445c39e39 100644 --- a/esp-hal/src/soc/esp32/gpio.rs +++ b/esp-hal/src/soc/esp32/gpio.rs @@ -43,10 +43,10 @@ use core::mem::transmute; use crate::{ - cpu::Cpu, gpio::{AlternateFunction, GpioPin}, pac::io_mux, peripherals::{GPIO, IO_MUX}, + system::Cpu, }; /// The total number of GPIO pins available. diff --git a/esp-hal/src/soc/esp32/mod.rs b/esp-hal/src/soc/esp32/mod.rs index a6d6b414021..05a7b3a8c9b 100644 --- a/esp-hal/src/soc/esp32/mod.rs +++ b/esp-hal/src/soc/esp32/mod.rs @@ -97,7 +97,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::cpu::reset_reason(), + crate::system::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/esp-hal/src/soc/esp32s2/mod.rs b/esp-hal/src/soc/esp32s2/mod.rs index 248137f7b85..b5401c4d64d 100644 --- a/esp-hal/src/soc/esp32s2/mod.rs +++ b/esp-hal/src/soc/esp32s2/mod.rs @@ -101,7 +101,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::cpu::reset_reason(), + crate::system::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index ef36d66eb7b..e763262a151 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -12,9 +12,9 @@ use core::{ }; use crate::{ - cpu::Cpu, peripheral::{Peripheral, PeripheralRef}, peripherals::{CPU_CTRL, LPWR, SYSTEM}, + system::Cpu, }; /// Data type for a properly aligned stack of N bytes @@ -107,7 +107,7 @@ pub enum Error { /// ```rust, no_run #[doc = crate::before_snippet!()] /// # use esp_hal::delay::Delay; -/// # use esp_hal::cpu::{CpuControl, Stack}; +/// # use esp_hal::system::{CpuControl, Stack}; /// # use core::{cell::RefCell, ptr::addr_of_mut}; /// # use critical_section::Mutex; /// # let delay = Delay::new(); diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs index 8e7d4b9d4a3..f0c3fe44069 100644 --- a/esp-hal/src/soc/esp32s3/mod.rs +++ b/esp-hal/src/soc/esp32s3/mod.rs @@ -140,7 +140,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { addr_of_mut!(_rtc_slow_bss_end), ); if matches!( - crate::cpu::reset_reason(), + crate::system::reset_reason(), None | Some(SocResetReason::ChipPowerOn) ) { xtensa_lx_rt::zero_bss( diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index 492f34afc65..ce2478549e0 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -46,7 +46,6 @@ use super::{BitOrder, DataMode, DmaError, Error, Mode}; use crate::{ asynch::AtomicWaker, clock::Clocks, - cpu::Cpu, dma::{DmaChannelFor, DmaEligible, DmaRxBuffer, DmaTxBuffer, Rx, Tx}, gpio::{ interconnect::{OutputConnection, PeripheralInput, PeripheralOutput}, @@ -60,7 +59,7 @@ use crate::{ peripheral::{Peripheral, PeripheralRef}, private::{self, Sealed}, spi::AnySpi, - system::PeripheralGuard, + system::{Cpu, PeripheralGuard}, time::Rate, Async, Blocking, @@ -1345,7 +1344,7 @@ mod dma { /// Interrupts are not enabled at the peripheral level here. fn set_interrupt_handler(&mut self, handler: InterruptHandler) { let interrupt = self.driver().info.interrupt; - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/sync.rs b/esp-hal/src/sync.rs index edbf7f6bc4a..ed66a3df833 100644 --- a/esp-hal/src/sync.rs +++ b/esp-hal/src/sync.rs @@ -128,7 +128,7 @@ mod multicore { const UNUSED_THREAD_ID_VALUE: usize = 0x100; pub fn thread_id() -> usize { - crate::cpu::raw_core() + crate::system::raw_core() } pub(super) struct AtomicLock { diff --git a/esp-hal/src/system.rs b/esp-hal/src/system.rs index 7b47a2f9b87..6000ce60ecd 100755 --- a/esp-hal/src/system.rs +++ b/esp-hal/src/system.rs @@ -1149,3 +1149,155 @@ impl PeripheralClockControl { true } } + +#[cfg(any(esp32, esp32s3))] +#[allow(unused_imports)] +pub use crate::soc::cpu_control::*; + +/// Available CPU cores +/// +/// The actual number of available cores depends on the target. +#[derive(Debug, Copy, Clone, PartialEq, Eq, strum::FromRepr)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(C)] +pub enum Cpu { + /// The first core + ProCpu = 0, + /// The second core + #[cfg(multi_core)] + AppCpu = 1, +} + +impl Cpu { + /// The number of available cores. + pub const COUNT: usize = 1 + cfg!(multi_core) as usize; + + /// Returns the core the application is currently executing on + #[inline(always)] + pub fn current() -> Self { + // This works for both RISCV and Xtensa because both + // get_raw_core functions return zero, _or_ something + // greater than zero; 1 in the case of RISCV and 0x2000 + // in the case of Xtensa. + match raw_core() { + 0 => Cpu::ProCpu, + #[cfg(all(multi_core, riscv))] + 1 => Cpu::AppCpu, + #[cfg(all(multi_core, xtensa))] + 0x2000 => Cpu::AppCpu, + _ => unreachable!(), + } + } + + /// Returns an iterator over the "other" cores. + #[inline(always)] + pub(crate) fn other() -> impl Iterator { + cfg_if::cfg_if! { + if #[cfg(multi_core)] { + match Self::current() { + Cpu::ProCpu => [Cpu::AppCpu].into_iter(), + Cpu::AppCpu => [Cpu::ProCpu].into_iter(), + } + } else { + [].into_iter() + } + } + } + + /// Returns an iterator over all cores. + #[inline(always)] + pub(crate) fn all() -> impl Iterator { + cfg_if::cfg_if! { + if #[cfg(multi_core)] { + [Cpu::ProCpu, Cpu::AppCpu].into_iter() + } else { + [Cpu::ProCpu].into_iter() + } + } + } +} + +/// Returns the raw value of the mhartid register. +/// +/// On RISC-V, this is the hardware thread ID. +/// +/// On Xtensa, this returns the result of reading the PRID register logically +/// ANDed with 0x2000, the 13th bit in the register. Espressif Xtensa chips use +/// this bit to determine the core id. +#[inline(always)] +pub(crate) fn raw_core() -> usize { + // This method must never return UNUSED_THREAD_ID_VALUE + cfg_if::cfg_if! { + if #[cfg(all(multi_core, riscv))] { + riscv::register::mhartid::read() + } else if #[cfg(all(multi_core, xtensa))] { + (xtensa_lx::get_processor_id() & 0x2000) as usize + } else { + 0 + } + } +} + +use crate::rtc_cntl::SocResetReason; + +/// Source of the wakeup event +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[instability::unstable] +pub enum SleepSource { + /// In case of deep sleep, reset was not caused by exit from deep sleep + Undefined = 0, + /// Not a wakeup cause, used to disable all wakeup sources with + /// esp_sleep_disable_wakeup_source + All, + /// Wakeup caused by external signal using RTC_IO + Ext0, + /// Wakeup caused by external signal using RTC_CNTL + Ext1, + /// Wakeup caused by timer + Timer, + /// Wakeup caused by touchpad + TouchPad, + /// Wakeup caused by ULP program + Ulp, + /// Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3) + Gpio, + /// Wakeup caused by UART (light sleep only) + Uart, + /// Wakeup caused by WIFI (light sleep only) + Wifi, + /// Wakeup caused by COCPU int + Cocpu, + /// Wakeup caused by COCPU crash + CocpuTrapTrig, + /// Wakeup caused by BT (light sleep only) + BT, +} + +/// Performs a software reset on the chip. +#[inline] +pub fn software_reset() -> ! { + crate::rom::software_reset() +} + +/// Resets the given CPU, leaving peripherals unchanged. +#[instability::unstable] +#[inline] +pub fn software_reset_cpu(cpu: Cpu) { + crate::rom::software_reset_cpu(cpu as u32) +} + +/// Retrieves the reason for the last reset as a SocResetReason enum value. +/// Returns `None` if the reset reason cannot be determined. +#[instability::unstable] +#[inline] +pub fn reset_reason() -> Option { + crate::rtc_cntl::reset_reason(Cpu::current()) +} + +/// Retrieves the cause of the last wakeup event as a SleepSource enum value. +#[instability::unstable] +#[inline] +pub fn wakeup_cause() -> SleepSource { + crate::rtc_cntl::wakeup_cause() +} diff --git a/esp-hal/src/timer/mod.rs b/esp-hal/src/timer/mod.rs index 16738f0f668..e733be83dbd 100644 --- a/esp-hal/src/timer/mod.rs +++ b/esp-hal/src/timer/mod.rs @@ -49,10 +49,10 @@ use core::{ use crate::{ asynch::AtomicWaker, - cpu::Cpu, interrupt::{InterruptConfigurable, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, peripherals::Interrupt, + system::Cpu, time::{Duration, Instant}, Async, Blocking, diff --git a/esp-hal/src/timer/systimer.rs b/esp-hal/src/timer/systimer.rs index 845974b7fc7..35dcd2b886e 100644 --- a/esp-hal/src/timer/systimer.rs +++ b/esp-hal/src/timer/systimer.rs @@ -22,12 +22,11 @@ use core::fmt::Debug; use super::{Error, Timer as _}; use crate::{ asynch::AtomicWaker, - cpu::Cpu, interrupt::{self, InterruptHandler}, peripheral::Peripheral, peripherals::{Interrupt, SYSTIMER}, sync::{lock, RawMutex}, - system::{Peripheral as PeripheralEnable, PeripheralClockControl}, + system::{Cpu, Peripheral as PeripheralEnable, PeripheralClockControl}, time::{Duration, Instant}, }; @@ -397,7 +396,7 @@ impl Alarm { _ => unreachable!(), }; - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs index 2b7d034b9cc..1521936bec9 100644 --- a/esp-hal/src/timer/timg.rs +++ b/esp-hal/src/timer/timg.rs @@ -391,7 +391,7 @@ impl Timer { _ => unreachable!(), }; - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, interrupt); } unsafe { interrupt::bind_interrupt(interrupt, handler.handler()) }; diff --git a/esp-hal/src/twai/mod.rs b/esp-hal/src/twai/mod.rs index e4564882476..05fb4850cac 100644 --- a/esp-hal/src/twai/mod.rs +++ b/esp-hal/src/twai/mod.rs @@ -122,7 +122,6 @@ use core::marker::PhantomData; use self::filter::{Filter, FilterType}; use crate::{ - cpu::Cpu, gpio::{ interconnect::{PeripheralInput, PeripheralOutput}, InputSignal, @@ -132,7 +131,7 @@ use crate::{ interrupt::InterruptHandler, pac::twai0::RegisterBlock, peripheral::{Peripheral, PeripheralRef}, - system::PeripheralGuard, + system::{Cpu, PeripheralGuard}, twai::filter::SingleStandardFilter, Async, Blocking, @@ -987,7 +986,7 @@ impl<'d> TwaiConfiguration<'d, Blocking> { impl<'d> TwaiConfiguration<'d, Async> { /// Convert the configuration into a blocking configuration. pub fn into_blocking(self) -> TwaiConfiguration<'d, Blocking> { - use crate::{cpu::Cpu, interrupt}; + use crate::{interrupt, system::Cpu}; interrupt::disable(Cpu::current(), self.twai.interrupt()); diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 61baa5ed6aa..490c863aab8 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2234,7 +2234,7 @@ impl Info { } fn set_interrupt_handler(&self, handler: InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, self.interrupt); } self.enable_listen(EnumSet::all(), false); @@ -2244,7 +2244,7 @@ impl Info { } fn disable_interrupts(&self) { - crate::interrupt::disable(crate::cpu::Cpu::current(), self.interrupt); + crate::interrupt::disable(crate::system::Cpu::current(), self.interrupt); } fn apply_config(&self, config: &Config) -> Result<(), ConfigError> { diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs index 22f72a7faa8..5caadf73495 100644 --- a/esp-hal/src/usb_serial_jtag.rs +++ b/esp-hal/src/usb_serial_jtag.rs @@ -129,11 +129,10 @@ use procmacros::handler; use crate::{ asynch::AtomicWaker, - cpu::Cpu, pac::usb_device::RegisterBlock, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, USB_DEVICE}, - system::PeripheralClockControl, + system::{Cpu, PeripheralClockControl}, Async, Blocking, DriverMode, @@ -447,7 +446,7 @@ where /// handlers. #[instability::unstable] pub fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { - for core in crate::cpu::Cpu::other() { + for core in crate::system::Cpu::other() { crate::interrupt::disable(core, Interrupt::USB_DEVICE); } unsafe { crate::interrupt::bind_interrupt(Interrupt::USB_DEVICE, handler.handler()) }; diff --git a/esp-wifi/src/ble/os_adapter_esp32s3.rs b/esp-wifi/src/ble/os_adapter_esp32s3.rs index 498f054eefe..3a9c26dd87b 100644 --- a/esp-wifi/src/ble/os_adapter_esp32s3.rs +++ b/esp-wifi/src/ble/os_adapter_esp32s3.rs @@ -306,7 +306,7 @@ pub(crate) unsafe extern "C" fn interrupt_on(intr_num: i32) -> i32 { pub(crate) unsafe extern "C" fn interrupt_off(intr_num: i32) -> i32 { trace!("interrupt_off {}", intr_num); interrupt::disable( - crate::hal::cpu::Cpu::ProCpu, + crate::hal::system::Cpu::ProCpu, Interrupt::try_from(intr_num as u16).unwrap(), ); diff --git a/esp-wifi/src/preempt/timer/riscv.rs b/esp-wifi/src/preempt/timer/riscv.rs index 33a303cfaf6..53ec4235f81 100644 --- a/esp-wifi/src/preempt/timer/riscv.rs +++ b/esp-wifi/src/preempt/timer/riscv.rs @@ -53,7 +53,7 @@ pub(crate) fn setup_multitasking() { } pub(crate) fn disable_multitasking() { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::FROM_CPU_INTR3); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::FROM_CPU_INTR3); } extern "C" fn handler(trap_frame: &mut TrapFrame) { diff --git a/esp-wifi/src/radio/radio_esp32.rs b/esp-wifi/src/radio/radio_esp32.rs index 38e815f7903..6b3964874ba 100644 --- a/esp-wifi/src/radio/radio_esp32.rs +++ b/esp-wifi/src/radio/radio_esp32.rs @@ -8,18 +8,27 @@ pub(crate) fn setup_radio_isr() { // It's a mystery why these interrupts are enabled now since it worked without // this before Now at least without disabling these nothing will work interrupt::disable( - crate::hal::cpu::Cpu::ProCpu, + crate::hal::system::Cpu::ProCpu, peripherals::Interrupt::ETH_MAC, ); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::UART0); + interrupt::disable( + crate::hal::system::Cpu::ProCpu, + peripherals::Interrupt::UART0, + ); } } pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::RWBT); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, peripherals::Interrupt::BT_BB); + interrupt::disable( + crate::hal::system::Cpu::ProCpu, + peripherals::Interrupt::RWBT, + ); + interrupt::disable( + crate::hal::system::Cpu::ProCpu, + peripherals::Interrupt::BT_BB, + ); } } diff --git a/esp-wifi/src/radio/radio_esp32c2.rs b/esp-wifi/src/radio/radio_esp32c2.rs index 8e74d6656bd..ddd302df632 100644 --- a/esp-wifi/src/radio/radio_esp32c2.rs +++ b/esp-wifi/src/radio/radio_esp32c2.rs @@ -12,8 +12,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_TIMER); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::LP_TIMER); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32c3.rs b/esp-wifi/src/radio/radio_esp32c3.rs index 8250f3d7318..11b6e269531 100644 --- a/esp-wifi/src/radio/radio_esp32c3.rs +++ b/esp-wifi/src/radio/radio_esp32c3.rs @@ -12,9 +12,9 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBT); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBLE); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_BB); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::RWBT); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::RWBLE); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::BT_BB); } } diff --git a/esp-wifi/src/radio/radio_esp32c6.rs b/esp-wifi/src/radio/radio_esp32c6.rs index 93f9f254a8c..e990407481d 100644 --- a/esp-wifi/src/radio/radio_esp32c6.rs +++ b/esp-wifi/src/radio/radio_esp32c6.rs @@ -23,8 +23,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_TIMER); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::LP_TIMER); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32h2.rs b/esp-wifi/src/radio/radio_esp32h2.rs index 29d8695de2f..b75f805e7e6 100644 --- a/esp-wifi/src/radio/radio_esp32h2.rs +++ b/esp-wifi/src/radio/radio_esp32h2.rs @@ -11,8 +11,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::LP_BLE_TIMER); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_MAC); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::LP_BLE_TIMER); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::BT_MAC); } } diff --git a/esp-wifi/src/radio/radio_esp32s3.rs b/esp-wifi/src/radio/radio_esp32s3.rs index 1baf898ed6b..5b903e9abee 100644 --- a/esp-wifi/src/radio/radio_esp32s3.rs +++ b/esp-wifi/src/radio/radio_esp32s3.rs @@ -9,8 +9,8 @@ pub(crate) fn setup_radio_isr() { pub(crate) fn shutdown_radio_isr() { #[cfg(feature = "ble")] { - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::BT_BB); - interrupt::disable(crate::hal::cpu::Cpu::ProCpu, Interrupt::RWBLE); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::BT_BB); + interrupt::disable(crate::hal::system::Cpu::ProCpu, Interrupt::RWBLE); } } diff --git a/examples/src/bin/embassy_multicore.rs b/examples/src/bin/embassy_multicore.rs index aa5b6fde1a3..188829a9584 100644 --- a/examples/src/bin/embassy_multicore.rs +++ b/examples/src/bin/embassy_multicore.rs @@ -19,8 +19,8 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal} use embassy_time::{Duration, Ticker}; use esp_backtrace as _; use esp_hal::{ - cpu::{Cpu, CpuControl, Stack}, gpio::{Level, Output, OutputConfig}, + system::{Cpu, CpuControl, Stack}, timer::{timg::TimerGroup, AnyTimer}, }; use esp_hal_embassy::Executor; diff --git a/examples/src/bin/embassy_multicore_interrupt.rs b/examples/src/bin/embassy_multicore_interrupt.rs index a193d116e98..7f02ed0535d 100644 --- a/examples/src/bin/embassy_multicore_interrupt.rs +++ b/examples/src/bin/embassy_multicore_interrupt.rs @@ -18,10 +18,10 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal} use embassy_time::{Duration, Ticker}; use esp_backtrace as _; use esp_hal::{ - cpu::{Cpu, CpuControl, Stack}, gpio::{Level, Output, OutputConfig}, interrupt::{software::SoftwareInterruptControl, Priority}, main, + system::{Cpu, CpuControl, Stack}, timer::{timg::TimerGroup, AnyTimer}, }; use esp_hal_embassy::InterruptExecutor; diff --git a/examples/src/bin/ieee802154_sniffer.rs b/examples/src/bin/ieee802154_sniffer.rs index ebd556663dd..7b23a143fe2 100644 --- a/examples/src/bin/ieee802154_sniffer.rs +++ b/examples/src/bin/ieee802154_sniffer.rs @@ -10,8 +10,8 @@ use esp_backtrace as _; use esp_hal::{ - cpu::software_reset, main, + system::software_reset, uart::{self, Uart}, }; use esp_ieee802154::{Config, Ieee802154}; diff --git a/hil-test/tests/embassy_interrupt_executor.rs b/hil-test/tests/embassy_interrupt_executor.rs index 7346ddecb25..578b3352f13 100644 --- a/hil-test/tests/embassy_interrupt_executor.rs +++ b/hil-test/tests/embassy_interrupt_executor.rs @@ -15,7 +15,7 @@ use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, signal::Signal}; #[cfg(multi_core)] -use esp_hal::cpu::{CpuControl, Stack}; +use esp_hal::system::{CpuControl, Stack}; use esp_hal::{ interrupt::{ software::{SoftwareInterrupt, SoftwareInterruptControl}, diff --git a/hil-test/tests/embassy_interrupt_spi_dma.rs b/hil-test/tests/embassy_interrupt_spi_dma.rs index 1449dcfc483..637ce1d0404 100644 --- a/hil-test/tests/embassy_interrupt_spi_dma.rs +++ b/hil-test/tests/embassy_interrupt_spi_dma.rs @@ -308,7 +308,7 @@ mod test { } }; - use esp_hal::cpu::{CpuControl, Stack}; + use esp_hal::system::{CpuControl, Stack}; const DISPLAY_STACK_SIZE: usize = 8192; let app_core_stack = mk_static!(Stack, Stack::new()); let cpu_control = CpuControl::new(peripherals.CPU_CTRL); diff --git a/hil-test/tests/esp_wifi_floats.rs b/hil-test/tests/esp_wifi_floats.rs index e12202d38e0..5a28aaa0ed5 100644 --- a/hil-test/tests/esp_wifi_floats.rs +++ b/hil-test/tests/esp_wifi_floats.rs @@ -42,7 +42,7 @@ cfg_if::cfg_if! { if #[cfg(multi_core)] { use core::sync::atomic::{AtomicBool, Ordering}; - use esp_hal::cpu::{CpuControl, Stack}; + use esp_hal::system::{CpuControl, Stack}; static DONE: AtomicBool = AtomicBool::new(false); static mut APP_CORE_STACK: Stack<8192> = Stack::new(); diff --git a/qa-test/src/bin/sleep_timer.rs b/qa-test/src/bin/sleep_timer.rs index 1137534a983..bd395c7e1cd 100644 --- a/qa-test/src/bin/sleep_timer.rs +++ b/qa-test/src/bin/sleep_timer.rs @@ -9,10 +9,10 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ - cpu::Cpu, delay::Delay, main, rtc_cntl::{reset_reason, sleep::TimerWakeupSource, wakeup_cause, Rtc, SocResetReason}, + system::Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_ext0.rs b/qa-test/src/bin/sleep_timer_ext0.rs index f396c2da18a..7879a2bf984 100644 --- a/qa-test/src/bin/sleep_timer_ext0.rs +++ b/qa-test/src/bin/sleep_timer_ext0.rs @@ -12,7 +12,6 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ - cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull}, main, @@ -23,6 +22,7 @@ use esp_hal::{ Rtc, SocResetReason, }, + system::Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_ext1.rs b/qa-test/src/bin/sleep_timer_ext1.rs index 87bece606ad..9d139c8ec3e 100644 --- a/qa-test/src/bin/sleep_timer_ext1.rs +++ b/qa-test/src/bin/sleep_timer_ext1.rs @@ -12,7 +12,6 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ - cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull, RtcPin}, main, @@ -23,6 +22,7 @@ use esp_hal::{ Rtc, SocResetReason, }, + system::Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_lpio.rs b/qa-test/src/bin/sleep_timer_lpio.rs index 5341db7c6f0..2c44aa062f0 100644 --- a/qa-test/src/bin/sleep_timer_lpio.rs +++ b/qa-test/src/bin/sleep_timer_lpio.rs @@ -13,7 +13,6 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ - cpu::Cpu, delay::Delay, gpio::{Input, InputConfig, Pull, RtcPinWithResistors}, main, @@ -24,6 +23,7 @@ use esp_hal::{ Rtc, SocResetReason, }, + system::Cpu, }; use esp_println::println; diff --git a/qa-test/src/bin/sleep_timer_rtcio.rs b/qa-test/src/bin/sleep_timer_rtcio.rs index 80a2f6e58e1..b1b81d87838 100644 --- a/qa-test/src/bin/sleep_timer_rtcio.rs +++ b/qa-test/src/bin/sleep_timer_rtcio.rs @@ -16,7 +16,6 @@ use core::time::Duration; use esp_backtrace as _; use esp_hal::{ - cpu::Cpu, delay::Delay, gpio, gpio::{Input, InputConfig, Pull}, @@ -28,6 +27,7 @@ use esp_hal::{ Rtc, SocResetReason, }, + system::Cpu, }; use esp_println::println; From 5198816ad4d51a28c4cdd0203c46a018554fdd10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Thu, 6 Feb 2025 16:23:25 +0100 Subject: [PATCH 13/13] Mark system stable --- esp-hal/src/lib.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index b7da01fe7d5..8bf5b0dd1ed 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -184,6 +184,7 @@ pub mod peripheral; mod reg_access; #[cfg(any(spi0, spi1, spi2, spi3))] pub mod spi; +pub mod system; pub mod time; #[cfg(any(uart0, uart1, uart2))] pub mod uart; @@ -273,8 +274,6 @@ unstable_module! { pub mod sha; #[doc(hidden)] pub mod sync; - #[cfg(any(dport, hp_sys, pcr, system))] - pub mod system; #[cfg(any(systimer, timg0, timg1))] pub mod timer; #[cfg(touch)]