hacknet feature request (verilog): indicate port directions

[fangism]

Currently hacknet -f output_format=verilog ... produces modules like:

module (_sReset, error, ...);
wire __sReset;
wire error;
wire local;
endmodule

when hacknet does have port direction information from -f emit_port_summary:

// BEGIN node port info
//      __sReset : input
//      error : inout
// END mode port info

It would be helpful to directly generate:

module (_sReset, error, ...);
input wire __sReset;
output wire error;
wire local;
endmodule

This would simplify wrapper generation for cosimulation (especially 3-way: analog, verilog, HAC).