|
11 | 11 | * EFFECTIVE ADDRESS ==> #imm 16 or 32 (propagate size)
|
12 | 12 | * EFFECTIVE ADDRESS ==> Resolve PC Relative address
|
13 | 13 | * DECODE_LABEL() ==> Resolve Correct Relative address
|
14 |
| - * DIVxL ==> Implements |
15 | 14 | ************************************************************************************
|
16 | 15 | * Useful links
|
17 | 16 | * http://www.apollo-core.com/bringup/decoder_cpu.ods
|
@@ -967,20 +966,24 @@ APTR DECODE_020_CMP2(APTR p, UINT16 op, UINT16 ex, int size) {
|
967 | 966 | OUT("CMP2.%c %s,%c%i", SZ[size], ea, DA[BIT(ex, 15)], DOWNTO(ex, 14, 12));
|
968 | 967 | return p;
|
969 | 968 | }
|
970 |
| -APTR DECODE_020_DIV(APTR p, UINT16 op) { // TODO: DIVxL <ea>,Dr:Dq |
| 969 | +APTR DECODE_020_DIV(APTR p, UINT16 op) { |
971 | 970 | // DIVU.L <ea>,Dq 32/16 => 32q
|
972 | 971 | // DIVU.L <ea>,Dr:Dq 64/32 => 32r-32q
|
973 |
| - // DIVUL.L <ea>,Dr:Dq 32/32 => 32r-32q ==> TODO: Implement |
| 972 | + // DIVUL.L <ea>,Dr:Dq 32/32 => 32r-32q |
974 | 973 | // DIVS.L <ea>,Dq 32/32 => 32q
|
975 | 974 | // DIVS.L <ea>,Dr:Dq 64/32 => 32r-32q
|
976 |
| - // DIVSL.L <ea>,Dr:Dq 32/32 => 32r-32q ==> TODO: Implement |
977 |
| - UINT16 ex; |
| 975 | + // DIVSL.L <ea>,Dr:Dq 32/32 => 32r-32q |
| 976 | + UINT16 ex, dq, dr; |
978 | 977 | p = READWORD(p, &ex);
|
979 | 978 | p = DECODE_EA(p, op);
|
980 |
| - OUT("DIV%s.L %s,", BIT(ex, 11) ? "S" : "U", ea); |
981 |
| - if (BIT(ex, 10)) |
982 |
| - OUT("d%i:", DOWNTO(ex, 14, 12)); |
983 |
| - OUT("d%i", DOWNTO(ex, 2, 0)); |
| 979 | + dr = DOWNTO(ex, 2, 0); |
| 980 | + dq = DOWNTO(ex, 14, 12); |
| 981 | + OUT("DIV%s%s %s,d%i", |
| 982 | + BIT(ex, 11) ? "S" : "U", |
| 983 | + BIT(ex, 10) ? ".l " : "L.l", |
| 984 | + ea, dr); |
| 985 | + if (dq != dr) |
| 986 | + OUT(":d%i", dq); |
984 | 987 | return p;
|
985 | 988 | }
|
986 | 989 | APTR DECODE_020_EXTB(APTR p, UINT16 op) {
|
@@ -1863,6 +1866,11 @@ int main(int argc, char *argv[]) {
|
1863 | 1866 | UINT16 sample[100] = {
|
1864 | 1867 | 0x4cdf,0x7cfc,
|
1865 | 1868 | 0x3228,0x001c,
|
| 1869 | + |
| 1870 | + 0x4c40,0x1001, // DIVU.L d0,d1 |
| 1871 | + 0x4c40,0x2401, // DIVU.L d0,d1:d2 |
| 1872 | + 0x4c40,0x2001, // DIVUL.L d0,d1:d2 |
| 1873 | + |
1866 | 1874 | 0x690f,
|
1867 | 1875 | 0x69f0,
|
1868 | 1876 | 0xe000,
|
|
0 commit comments