With a high V_Scale value we get what appears to be line 480 copied down the screen. This feels unintuitive. It should either be line 479 (where line 0 is the first line), draw nothing, or should continue to render without the 480 constraint.
So either change this to 479, or remove the check?
https://github.com/fvdhoef/vera-module/blob/rev4/fpga/source/graphics/composer.v#L157

Test app for above:
code: test.zip
prg: example.zip