-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathgd32e505.mmap
12595 lines (12595 loc) · 747 KB
/
gd32e505.mmap
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
0x40000000 A PERIPHERAL TIMER1
0x40000000 B REGISTER CTL0 (rw): control register 0
0x40000000 C FIELD 00w01 CEN: Counter enable
0x40000000 C FIELD 01w01 UPDIS: Update disable
0x40000000 C FIELD 02w01 UPS: Update source
0x40000000 C FIELD 03w01 SPM: Single pulse mode
0x40000000 C FIELD 04w01 DIR: Direction
0x40000000 C FIELD 05w02 CAM: Counter aligns mode selection
0x40000000 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40000000 C FIELD 08w02 CKDIV: Clock division
0x40000004 B REGISTER CTL1 (rw): control register 1
0x40000004 C FIELD 03w01 DMAS: DMA request source selection
0x40000004 C FIELD 04w03 MMC: Master mode control
0x40000004 C FIELD 07w01 TI0S: Channel 0 trigger input selection
0x40000008 B REGISTER SMCFG (rw): slave mode control register
0x40000008 C FIELD 00w03 SMC: Slave mode control
0x40000008 C FIELD 04w03 TRGS: Trigger selection
0x40000008 C FIELD 07w01 MSM: Master-slave mode
0x40000008 C FIELD 08w04 ETFC: External trigger filter control
0x40000008 C FIELD 12w02 ETPSC: External trigger prescaler
0x40000008 C FIELD 14w01 SMC1: Part of SMC for enable External clock mode1
0x40000008 C FIELD 15w01 ETP: External trigger polarity
0x4000000C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000000C C FIELD 00w01 UPIE: Update interrupt enable
0x4000000C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x4000000C C FIELD 02w01 CH1IE: Channel 1 capture/compare interrupt enable
0x4000000C C FIELD 03w01 CH2IE: Channel 2 capture/compare interrupt enable
0x4000000C C FIELD 04w01 CH3IE: Channel 3 capture/compare interrupt enable
0x4000000C C FIELD 06w01 TRGIE: Trigger interrupt enable
0x4000000C C FIELD 08w01 UPDEN: Update DMA request enable
0x4000000C C FIELD 09w01 CH0DEN: Channel 0 capture/compare DMA request enable
0x4000000C C FIELD 10w01 CH1DEN: Channel 1 capture/compare DMA request enable
0x4000000C C FIELD 11w01 CH2DEN: Channel 2 capture/compare DMA request enable
0x4000000C C FIELD 12w01 CH3DEN: Channel 3 capture/compare DMA request enable
0x4000000C C FIELD 14w01 TRGDEN: Trigger DMA request enable
0x40000010 B REGISTER INTF (rw): interrupt flag register
0x40000010 C FIELD 00w01 UPIF: Update interrupt flag
0x40000010 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40000010 C FIELD 02w01 CH1IF: Channel 1 capture/compare interrupt flag
0x40000010 C FIELD 03w01 CH2IF: Channel 2 capture/compare interrupt enable
0x40000010 C FIELD 04w01 CH3IF: Channel 3 capture/compare interrupt enable
0x40000010 C FIELD 06w01 TRGIF: Trigger interrupt flag
0x40000010 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40000010 C FIELD 10w01 CH1OF: Channel 1 over capture flag
0x40000010 C FIELD 11w01 CH2OF: Channel 2 over capture flag
0x40000010 C FIELD 12w01 CH3OF: Channel 3 over capture flag
0x40000014 B REGISTER SWEVG (wo): event generation register
0x40000014 C FIELD 00w01 UPG: Update generation
0x40000014 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40000014 C FIELD 02w01 CH1G: Channel 1 capture or compare event generation
0x40000014 C FIELD 03w01 CH2G: Channel 2 capture or compare event generation
0x40000014 C FIELD 04w01 CH3G: Channel 3 capture or compare event generation
0x40000014 C FIELD 06w01 TRGG: Trigger event generation
0x40000018 B REGISTER CHCTL0_Input (rw): Channel control register 0 (input mode)
0x40000018 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40000018 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40000018 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40000018 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40000018 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40000018 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40000018 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40000018 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40000018 C FIELD 07w01 CH0COMCEN: Channel 0 output compare clear enable
0x40000018 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000018 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000018 C FIELD 10w01 CH1COMFEN: Channel 1 output compare fast enable
0x40000018 C FIELD 10w02 CH1CAPPSC: Channel 1 input capture prescaler
0x40000018 C FIELD 11w01 CH1COMSEN: Channel 1 output compare shadow enable
0x40000018 C FIELD 12w03 CH1COMCTL: Channel 1 compare output control
0x40000018 C FIELD 12w04 CH1CAPFLT: Channel 1 input capture filter control
0x40000018 C FIELD 15w01 CH1COMCEN: Channel 1 output compare clear enable
0x4000001C B REGISTER CHCTL1_Input (rw): Channel control register 1 (input mode)
0x4000001C B REGISTER CHCTL1_Output (rw): Channel control register 1 (output mode)
0x4000001C C FIELD 00w02 CH2MS: Channel 2 I/O mode selection
0x4000001C C FIELD 00w02 CH2MS: Channel 2 mode selection
0x4000001C C FIELD 02w01 CH2COMFEN: Channel 2 output compare fast enable
0x4000001C C FIELD 02w02 CH2CAPPSC: Channel 2 input capture prescaler
0x4000001C C FIELD 03w01 CH2COMSEN: Channel 2 compare output shadow enable
0x4000001C C FIELD 04w03 CH2COMCTL: Channel 2 compare output control
0x4000001C C FIELD 04w04 CH2CAPFLT: Channel 2 input capture filter control
0x4000001C C FIELD 07w01 CH2COMCEN: Channel 2 output compare clear enable
0x4000001C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000001C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000001C C FIELD 10w01 CH3COMFEN: Channel 3 output compare fast enable
0x4000001C C FIELD 10w02 CH3CAPPSC: Channel 3 input capture prescaler
0x4000001C C FIELD 11w01 CH3COMSEN: Channel 3 output compare shadow enable
0x4000001C C FIELD 12w03 CH3COMCTL: Channel 3 compare output control
0x4000001C C FIELD 12w04 CH3CAPFLT: Channel 3 input capture filter control
0x4000001C C FIELD 15w01 CH3COMCEN: Channel 3 output compare clear enable
0x40000020 B REGISTER CHCTL2 (rw): Channel control register 2
0x40000020 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40000020 C FIELD 01w01 CH0P: Channel 0 capture/compare function polarity
0x40000020 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40000020 C FIELD 04w01 CH1EN: Channel 1 capture/compare function enable
0x40000020 C FIELD 05w01 CH1P: Channel 1 capture/compare function polarity
0x40000020 C FIELD 07w01 CH1NP: Channel 1 complementary output polarity
0x40000020 C FIELD 08w01 CH2EN: Channel 2 capture/compare function enable
0x40000020 C FIELD 09w01 CH2P: Channel 2 capture/compare function polarity
0x40000020 C FIELD 11w01 CH2NP: Channel 2 complementary output polarity
0x40000020 C FIELD 12w01 CH3EN: Channel 3 capture/compare function enable
0x40000020 C FIELD 13w01 CH3P: Channel 3 capture/compare function polarity
0x40000020 C FIELD 15w01 CH3NP: Channel 3 complementary output polarity
0x40000024 B REGISTER CNT (rw): Counter register
0x40000024 C FIELD 00w32 CNT: counter value
0x40000028 B REGISTER PSC (rw): Prescaler register
0x40000028 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000002C B REGISTER CAR (rw): Counter auto reload register
0x4000002C C FIELD 00w32 CAR: Counter auto reload value
0x40000034 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40000034 C FIELD 00w32 CH0VAL: Capture or compare value of channel 0
0x40000038 B REGISTER CH1CV (rw): Channel 1 capture/compare value register
0x40000038 C FIELD 00w32 CH1VAL: Capture or compare value of channel1
0x4000003C B REGISTER CH2CV (rw): Channel 2 capture/compare value register
0x4000003C C FIELD 00w32 CH2VAL: Capture or compare value of channel 2
0x40000040 B REGISTER CH3CV (rw): Channel 3 capture/compare value register
0x40000040 C FIELD 00w32 CH3VAL: Capture or compare value of channel 3
0x40000048 B REGISTER DMACFG (rw): DMA configuration register
0x40000048 C FIELD 00w05 DMATA: DMA transfer access start address
0x40000048 C FIELD 08w05 DMATC: DMA transfer count
0x4000004C B REGISTER DMATB (rw): DMA transfer buffer register
0x4000004C C FIELD 00w16 DMATB: DMA transfer buffer
0x400000FC B REGISTER CFG (rw): Configuration
0x400000FC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40000400 A PERIPHERAL TIMER2
0x40000400 B REGISTER CTL0 (rw): control register 0
0x40000400 C FIELD 00w01 CEN: Counter enable
0x40000400 C FIELD 01w01 UPDIS: Update disable
0x40000400 C FIELD 02w01 UPS: Update source
0x40000400 C FIELD 03w01 SPM: Single pulse mode
0x40000400 C FIELD 04w01 DIR: Direction
0x40000400 C FIELD 05w02 CAM: Counter aligns mode selection
0x40000400 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40000400 C FIELD 08w02 CKDIV: Clock division
0x40000404 B REGISTER CTL1 (rw): control register 1
0x40000404 C FIELD 03w01 DMAS: DMA request source selection
0x40000404 C FIELD 04w03 MMC: Master mode control
0x40000404 C FIELD 07w01 TI0S: Channel 0 trigger input selection
0x40000408 B REGISTER SMCFG (rw): slave mode control register
0x40000408 C FIELD 00w03 SMC: Slave mode control
0x40000408 C FIELD 04w03 TRGS: Trigger selection
0x40000408 C FIELD 07w01 MSM: Master-slave mode
0x40000408 C FIELD 08w04 ETFC: External trigger filter control
0x40000408 C FIELD 12w02 ETPSC: External trigger prescaler
0x40000408 C FIELD 14w01 SMC1: Part of SMC for enable External clock mode1
0x40000408 C FIELD 15w01 ETP: External trigger polarity
0x4000040C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000040C C FIELD 00w01 UPIE: Update interrupt enable
0x4000040C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x4000040C C FIELD 02w01 CH1IE: Channel 1 capture/compare interrupt enable
0x4000040C C FIELD 03w01 CH2IE: Channel 2 capture/compare interrupt enable
0x4000040C C FIELD 04w01 CH3IE: Channel 3 capture/compare interrupt enable
0x4000040C C FIELD 06w01 TRGIE: Trigger interrupt enable
0x4000040C C FIELD 08w01 UPDEN: Update DMA request enable
0x4000040C C FIELD 09w01 CH0DEN: Channel 0 capture/compare DMA request enable
0x4000040C C FIELD 10w01 CH1DEN: Channel 1 capture/compare DMA request enable
0x4000040C C FIELD 11w01 CH2DEN: Channel 2 capture/compare DMA request enable
0x4000040C C FIELD 12w01 CH3DEN: Channel 3 capture/compare DMA request enable
0x4000040C C FIELD 14w01 TRGDEN: Trigger DMA request enable
0x40000410 B REGISTER INTF (rw): interrupt flag register
0x40000410 C FIELD 00w01 UPIF: Update interrupt flag
0x40000410 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40000410 C FIELD 02w01 CH1IF: Channel 1 capture/compare interrupt flag
0x40000410 C FIELD 03w01 CH2IF: Channel 2 capture/compare interrupt enable
0x40000410 C FIELD 04w01 CH3IF: Channel 3 capture/compare interrupt enable
0x40000410 C FIELD 06w01 TRGIF: Trigger interrupt flag
0x40000410 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40000410 C FIELD 10w01 CH1OF: Channel 1 over capture flag
0x40000410 C FIELD 11w01 CH2OF: Channel 2 over capture flag
0x40000410 C FIELD 12w01 CH3OF: Channel 3 over capture flag
0x40000414 B REGISTER SWEVG (wo): event generation register
0x40000414 C FIELD 00w01 UPG: Update generation
0x40000414 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40000414 C FIELD 02w01 CH1G: Channel 1 capture or compare event generation
0x40000414 C FIELD 03w01 CH2G: Channel 2 capture or compare event generation
0x40000414 C FIELD 04w01 CH3G: Channel 3 capture or compare event generation
0x40000414 C FIELD 06w01 TRGG: Trigger event generation
0x40000418 B REGISTER CHCTL0_Input (rw): Channel control register 0 (input mode)
0x40000418 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40000418 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40000418 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40000418 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40000418 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40000418 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40000418 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40000418 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40000418 C FIELD 07w01 CH0COMCEN: Channel 0 output compare clear enable
0x40000418 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000418 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000418 C FIELD 10w01 CH1COMFEN: Channel 1 output compare fast enable
0x40000418 C FIELD 10w02 CH1CAPPSC: Channel 1 input capture prescaler
0x40000418 C FIELD 11w01 CH1COMSEN: Channel 1 output compare shadow enable
0x40000418 C FIELD 12w03 CH1COMCTL: Channel 1 compare output control
0x40000418 C FIELD 12w04 CH1CAPFLT: Channel 1 input capture filter control
0x40000418 C FIELD 15w01 CH1COMCEN: Channel 1 output compare clear enable
0x4000041C B REGISTER CHCTL1_Input (rw): Channel control register 1 (input mode)
0x4000041C B REGISTER CHCTL1_Output (rw): Channel control register 1 (output mode)
0x4000041C C FIELD 00w02 CH2MS: Channel 2 I/O mode selection
0x4000041C C FIELD 00w02 CH2MS: Channel 2 mode selection
0x4000041C C FIELD 02w01 CH2COMFEN: Channel 2 output compare fast enable
0x4000041C C FIELD 02w02 CH2CAPPSC: Channel 2 input capture prescaler
0x4000041C C FIELD 03w01 CH2COMSEN: Channel 2 compare output shadow enable
0x4000041C C FIELD 04w03 CH2COMCTL: Channel 2 compare output control
0x4000041C C FIELD 04w04 CH2CAPFLT: Channel 2 input capture filter control
0x4000041C C FIELD 07w01 CH2COMCEN: Channel 2 output compare clear enable
0x4000041C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000041C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000041C C FIELD 10w01 CH3COMFEN: Channel 3 output compare fast enable
0x4000041C C FIELD 10w02 CH3CAPPSC: Channel 3 input capture prescaler
0x4000041C C FIELD 11w01 CH3COMSEN: Channel 3 output compare shadow enable
0x4000041C C FIELD 12w03 CH3COMCTL: Channel 3 compare output control
0x4000041C C FIELD 12w04 CH3CAPFLT: Channel 3 input capture filter control
0x4000041C C FIELD 15w01 CH3COMCEN: Channel 3 output compare clear enable
0x40000420 B REGISTER CHCTL2 (rw): Channel control register 2
0x40000420 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40000420 C FIELD 01w01 CH0P: Channel 0 capture/compare function polarity
0x40000420 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40000420 C FIELD 04w01 CH1EN: Channel 1 capture/compare function enable
0x40000420 C FIELD 05w01 CH1P: Channel 1 capture/compare function polarity
0x40000420 C FIELD 07w01 CH1NP: Channel 1 complementary output polarity
0x40000420 C FIELD 08w01 CH2EN: Channel 2 capture/compare function enable
0x40000420 C FIELD 09w01 CH2P: Channel 2 capture/compare function polarity
0x40000420 C FIELD 11w01 CH2NP: Channel 2 complementary output polarity
0x40000420 C FIELD 12w01 CH3EN: Channel 3 capture/compare function enable
0x40000420 C FIELD 13w01 CH3P: Channel 3 capture/compare function polarity
0x40000420 C FIELD 15w01 CH3NP: Channel 3 complementary output polarity
0x40000424 B REGISTER CNT (rw): Counter register
0x40000424 C FIELD 00w16 CNT: counter value
0x40000428 B REGISTER PSC (rw): Prescaler register
0x40000428 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000042C B REGISTER CAR (rw): Counter auto reload register
0x4000042C C FIELD 00w16 CAR: Counter auto reload value
0x40000434 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40000434 C FIELD 00w16 CH0VAL: Capture or compare value of channel 0
0x40000438 B REGISTER CH1CV (rw): Channel 1 capture/compare value register
0x40000438 C FIELD 00w16 CH1VAL: Capture or compare value of channel1
0x4000043C B REGISTER CH2CV (rw): Channel 2 capture/compare value register
0x4000043C C FIELD 00w16 CH2VAL: Capture or compare value of channel 2
0x40000440 B REGISTER CH3CV (rw): Channel 3 capture/compare value register
0x40000440 C FIELD 00w16 CH3VAL: Capture or compare value of channel 3
0x40000448 B REGISTER DMACFG (rw): DMA configuration register
0x40000448 C FIELD 00w05 DMATA: DMA transfer access start address
0x40000448 C FIELD 08w05 DMATC: DMA transfer count
0x4000044C B REGISTER DMATB (rw): DMA transfer buffer register
0x4000044C C FIELD 00w16 DMATB: DMA transfer buffer
0x400004FC B REGISTER CFG (rw): Configuration
0x400004FC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40000800 A PERIPHERAL TIMER3
0x40000800 B REGISTER CTL0 (rw): control register 0
0x40000800 C FIELD 00w01 CEN: Counter enable
0x40000800 C FIELD 01w01 UPDIS: Update disable
0x40000800 C FIELD 02w01 UPS: Update source
0x40000800 C FIELD 03w01 SPM: Single pulse mode
0x40000800 C FIELD 04w01 DIR: Direction
0x40000800 C FIELD 05w02 CAM: Counter aligns mode selection
0x40000800 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40000800 C FIELD 08w02 CKDIV: Clock division
0x40000804 B REGISTER CTL1 (rw): control register 1
0x40000804 C FIELD 03w01 DMAS: DMA request source selection
0x40000804 C FIELD 04w03 MMC: Master mode control
0x40000804 C FIELD 07w01 TI0S: Channel 0 trigger input selection
0x40000808 B REGISTER SMCFG (rw): slave mode control register
0x40000808 C FIELD 00w03 SMC: Slave mode control
0x40000808 C FIELD 04w03 TRGS: Trigger selection
0x40000808 C FIELD 07w01 MSM: Master-slave mode
0x40000808 C FIELD 08w04 ETFC: External trigger filter control
0x40000808 C FIELD 12w02 ETPSC: External trigger prescaler
0x40000808 C FIELD 14w01 SMC1: Part of SMC for enable External clock mode1
0x40000808 C FIELD 15w01 ETP: External trigger polarity
0x4000080C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000080C C FIELD 00w01 UPIE: Update interrupt enable
0x4000080C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x4000080C C FIELD 02w01 CH1IE: Channel 1 capture/compare interrupt enable
0x4000080C C FIELD 03w01 CH2IE: Channel 2 capture/compare interrupt enable
0x4000080C C FIELD 04w01 CH3IE: Channel 3 capture/compare interrupt enable
0x4000080C C FIELD 06w01 TRGIE: Trigger interrupt enable
0x4000080C C FIELD 08w01 UPDEN: Update DMA request enable
0x4000080C C FIELD 09w01 CH0DEN: Channel 0 capture/compare DMA request enable
0x4000080C C FIELD 10w01 CH1DEN: Channel 1 capture/compare DMA request enable
0x4000080C C FIELD 11w01 CH2DEN: Channel 2 capture/compare DMA request enable
0x4000080C C FIELD 12w01 CH3DEN: Channel 3 capture/compare DMA request enable
0x4000080C C FIELD 14w01 TRGDEN: Trigger DMA request enable
0x40000810 B REGISTER INTF (rw): interrupt flag register
0x40000810 C FIELD 00w01 UPIF: Update interrupt flag
0x40000810 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40000810 C FIELD 02w01 CH1IF: Channel 1 capture/compare interrupt flag
0x40000810 C FIELD 03w01 CH2IF: Channel 2 capture/compare interrupt enable
0x40000810 C FIELD 04w01 CH3IF: Channel 3 capture/compare interrupt enable
0x40000810 C FIELD 06w01 TRGIF: Trigger interrupt flag
0x40000810 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40000810 C FIELD 10w01 CH1OF: Channel 1 over capture flag
0x40000810 C FIELD 11w01 CH2OF: Channel 2 over capture flag
0x40000810 C FIELD 12w01 CH3OF: Channel 3 over capture flag
0x40000814 B REGISTER SWEVG (wo): event generation register
0x40000814 C FIELD 00w01 UPG: Update generation
0x40000814 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40000814 C FIELD 02w01 CH1G: Channel 1 capture or compare event generation
0x40000814 C FIELD 03w01 CH2G: Channel 2 capture or compare event generation
0x40000814 C FIELD 04w01 CH3G: Channel 3 capture or compare event generation
0x40000814 C FIELD 06w01 TRGG: Trigger event generation
0x40000818 B REGISTER CHCTL0_Input (rw): Channel control register 0 (input mode)
0x40000818 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40000818 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40000818 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40000818 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40000818 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40000818 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40000818 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40000818 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40000818 C FIELD 07w01 CH0COMCEN: Channel 0 output compare clear enable
0x40000818 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000818 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000818 C FIELD 10w01 CH1COMFEN: Channel 1 output compare fast enable
0x40000818 C FIELD 10w02 CH1CAPPSC: Channel 1 input capture prescaler
0x40000818 C FIELD 11w01 CH1COMSEN: Channel 1 output compare shadow enable
0x40000818 C FIELD 12w03 CH1COMCTL: Channel 1 compare output control
0x40000818 C FIELD 12w04 CH1CAPFLT: Channel 1 input capture filter control
0x40000818 C FIELD 15w01 CH1COMCEN: Channel 1 output compare clear enable
0x4000081C B REGISTER CHCTL1_Input (rw): Channel control register 1 (input mode)
0x4000081C B REGISTER CHCTL1_Output (rw): Channel control register 1 (output mode)
0x4000081C C FIELD 00w02 CH2MS: Channel 2 I/O mode selection
0x4000081C C FIELD 00w02 CH2MS: Channel 2 mode selection
0x4000081C C FIELD 02w01 CH2COMFEN: Channel 2 output compare fast enable
0x4000081C C FIELD 02w02 CH2CAPPSC: Channel 2 input capture prescaler
0x4000081C C FIELD 03w01 CH2COMSEN: Channel 2 compare output shadow enable
0x4000081C C FIELD 04w03 CH2COMCTL: Channel 2 compare output control
0x4000081C C FIELD 04w04 CH2CAPFLT: Channel 2 input capture filter control
0x4000081C C FIELD 07w01 CH2COMCEN: Channel 2 output compare clear enable
0x4000081C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000081C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x4000081C C FIELD 10w01 CH3COMFEN: Channel 3 output compare fast enable
0x4000081C C FIELD 10w02 CH3CAPPSC: Channel 3 input capture prescaler
0x4000081C C FIELD 11w01 CH3COMSEN: Channel 3 output compare shadow enable
0x4000081C C FIELD 12w03 CH3COMCTL: Channel 3 compare output control
0x4000081C C FIELD 12w04 CH3CAPFLT: Channel 3 input capture filter control
0x4000081C C FIELD 15w01 CH3COMCEN: Channel 3 output compare clear enable
0x40000820 B REGISTER CHCTL2 (rw): Channel control register 2
0x40000820 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40000820 C FIELD 01w01 CH0P: Channel 0 capture/compare function polarity
0x40000820 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40000820 C FIELD 04w01 CH1EN: Channel 1 capture/compare function enable
0x40000820 C FIELD 05w01 CH1P: Channel 1 capture/compare function polarity
0x40000820 C FIELD 07w01 CH1NP: Channel 1 complementary output polarity
0x40000820 C FIELD 08w01 CH2EN: Channel 2 capture/compare function enable
0x40000820 C FIELD 09w01 CH2P: Channel 2 capture/compare function polarity
0x40000820 C FIELD 11w01 CH2NP: Channel 2 complementary output polarity
0x40000820 C FIELD 12w01 CH3EN: Channel 3 capture/compare function enable
0x40000820 C FIELD 13w01 CH3P: Channel 3 capture/compare function polarity
0x40000820 C FIELD 15w01 CH3NP: Channel 3 complementary output polarity
0x40000824 B REGISTER CNT (rw): Counter register
0x40000824 C FIELD 00w16 CNT: counter value
0x40000828 B REGISTER PSC (rw): Prescaler register
0x40000828 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000082C B REGISTER CAR (rw): Counter auto reload register
0x4000082C C FIELD 00w16 CAR: Counter auto reload value
0x40000834 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40000834 C FIELD 00w16 CH0VAL: Capture or compare value of channel 0
0x40000838 B REGISTER CH1CV (rw): Channel 1 capture/compare value register
0x40000838 C FIELD 00w16 CH1VAL: Capture or compare value of channel1
0x4000083C B REGISTER CH2CV (rw): Channel 2 capture/compare value register
0x4000083C C FIELD 00w16 CH2VAL: Capture or compare value of channel 2
0x40000840 B REGISTER CH3CV (rw): Channel 3 capture/compare value register
0x40000840 C FIELD 00w16 CH3VAL: Capture or compare value of channel 3
0x40000848 B REGISTER DMACFG (rw): DMA configuration register
0x40000848 C FIELD 00w05 DMATA: DMA transfer access start address
0x40000848 C FIELD 08w05 DMATC: DMA transfer count
0x4000084C B REGISTER DMATB (rw): DMA transfer buffer register
0x4000084C C FIELD 00w16 DMATB: DMA transfer buffer
0x400008FC B REGISTER CFG (rw): Configuration
0x400008FC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40000C00 A PERIPHERAL TIMER4
0x40000C00 B REGISTER CTL0 (rw): control register 0
0x40000C00 C FIELD 00w01 CEN: Counter enable
0x40000C00 C FIELD 01w01 UPDIS: Update disable
0x40000C00 C FIELD 02w01 UPS: Update source
0x40000C00 C FIELD 03w01 SPM: Single pulse mode
0x40000C00 C FIELD 04w01 DIR: Direction
0x40000C00 C FIELD 05w02 CAM: Counter aligns mode selection
0x40000C00 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40000C00 C FIELD 08w02 CKDIV: Clock division
0x40000C04 B REGISTER CTL1 (rw): control register 1
0x40000C04 C FIELD 03w01 DMAS: DMA request source selection
0x40000C04 C FIELD 04w03 MMC: Master mode control
0x40000C04 C FIELD 07w01 TI0S: Channel 0 trigger input selection
0x40000C08 B REGISTER SMCFG (rw): slave mode control register
0x40000C08 C FIELD 00w03 SMC: Slave mode control
0x40000C08 C FIELD 04w03 TRGS: Trigger selection
0x40000C08 C FIELD 07w01 MSM: Master-slave mode
0x40000C08 C FIELD 08w04 ETFC: External trigger filter control
0x40000C08 C FIELD 12w02 ETPSC: External trigger prescaler
0x40000C08 C FIELD 14w01 SMC1: Part of SMC for enable External clock mode1
0x40000C08 C FIELD 15w01 ETP: External trigger polarity
0x40000C0C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x40000C0C C FIELD 00w01 UPIE: Update interrupt enable
0x40000C0C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x40000C0C C FIELD 02w01 CH1IE: Channel 1 capture/compare interrupt enable
0x40000C0C C FIELD 03w01 CH2IE: Channel 2 capture/compare interrupt enable
0x40000C0C C FIELD 04w01 CH3IE: Channel 3 capture/compare interrupt enable
0x40000C0C C FIELD 06w01 TRGIE: Trigger interrupt enable
0x40000C0C C FIELD 08w01 UPDEN: Update DMA request enable
0x40000C0C C FIELD 09w01 CH0DEN: Channel 0 capture/compare DMA request enable
0x40000C0C C FIELD 10w01 CH1DEN: Channel 1 capture/compare DMA request enable
0x40000C0C C FIELD 11w01 CH2DEN: Channel 2 capture/compare DMA request enable
0x40000C0C C FIELD 12w01 CH3DEN: Channel 3 capture/compare DMA request enable
0x40000C0C C FIELD 14w01 TRGDEN: Trigger DMA request enable
0x40000C10 B REGISTER INTF (rw): interrupt flag register
0x40000C10 C FIELD 00w01 UPIF: Update interrupt flag
0x40000C10 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40000C10 C FIELD 02w01 CH1IF: Channel 1 capture/compare interrupt flag
0x40000C10 C FIELD 03w01 CH2IF: Channel 2 capture/compare interrupt enable
0x40000C10 C FIELD 04w01 CH3IF: Channel 3 capture/compare interrupt enable
0x40000C10 C FIELD 06w01 TRGIF: Trigger interrupt flag
0x40000C10 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40000C10 C FIELD 10w01 CH1OF: Channel 1 over capture flag
0x40000C10 C FIELD 11w01 CH2OF: Channel 2 over capture flag
0x40000C10 C FIELD 12w01 CH3OF: Channel 3 over capture flag
0x40000C14 B REGISTER SWEVG (wo): event generation register
0x40000C14 C FIELD 00w01 UPG: Update generation
0x40000C14 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40000C14 C FIELD 02w01 CH1G: Channel 1 capture or compare event generation
0x40000C14 C FIELD 03w01 CH2G: Channel 2 capture or compare event generation
0x40000C14 C FIELD 04w01 CH3G: Channel 3 capture or compare event generation
0x40000C14 C FIELD 06w01 TRGG: Trigger event generation
0x40000C18 B REGISTER CHCTL0_Input (rw): Channel control register 0 (input mode)
0x40000C18 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40000C18 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40000C18 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40000C18 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40000C18 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40000C18 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40000C18 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40000C18 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40000C18 C FIELD 07w01 CH0COMCEN: Channel 0 output compare clear enable
0x40000C18 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000C18 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40000C18 C FIELD 10w01 CH1COMFEN: Channel 1 output compare fast enable
0x40000C18 C FIELD 10w02 CH1CAPPSC: Channel 1 input capture prescaler
0x40000C18 C FIELD 11w01 CH1COMSEN: Channel 1 output compare shadow enable
0x40000C18 C FIELD 12w03 CH1COMCTL: Channel 1 compare output control
0x40000C18 C FIELD 12w04 CH1CAPFLT: Channel 1 input capture filter control
0x40000C18 C FIELD 15w01 CH1COMCEN: Channel 1 output compare clear enable
0x40000C1C B REGISTER CHCTL1_Input (rw): Channel control register 1 (input mode)
0x40000C1C B REGISTER CHCTL1_Output (rw): Channel control register 1 (output mode)
0x40000C1C C FIELD 00w02 CH2MS: Channel 2 I/O mode selection
0x40000C1C C FIELD 00w02 CH2MS: Channel 2 mode selection
0x40000C1C C FIELD 02w01 CH2COMFEN: Channel 2 output compare fast enable
0x40000C1C C FIELD 02w02 CH2CAPPSC: Channel 2 input capture prescaler
0x40000C1C C FIELD 03w01 CH2COMSEN: Channel 2 compare output shadow enable
0x40000C1C C FIELD 04w03 CH2COMCTL: Channel 2 compare output control
0x40000C1C C FIELD 04w04 CH2CAPFLT: Channel 2 input capture filter control
0x40000C1C C FIELD 07w01 CH2COMCEN: Channel 2 output compare clear enable
0x40000C1C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x40000C1C C FIELD 08w02 CH3MS: Channel 3 mode selection
0x40000C1C C FIELD 10w01 CH3COMFEN: Channel 3 output compare fast enable
0x40000C1C C FIELD 10w02 CH3CAPPSC: Channel 3 input capture prescaler
0x40000C1C C FIELD 11w01 CH3COMSEN: Channel 3 output compare shadow enable
0x40000C1C C FIELD 12w03 CH3COMCTL: Channel 3 compare output control
0x40000C1C C FIELD 12w04 CH3CAPFLT: Channel 3 input capture filter control
0x40000C1C C FIELD 15w01 CH3COMCEN: Channel 3 output compare clear enable
0x40000C20 B REGISTER CHCTL2 (rw): Channel control register 2
0x40000C20 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40000C20 C FIELD 01w01 CH0P: Channel 0 capture/compare function polarity
0x40000C20 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40000C20 C FIELD 04w01 CH1EN: Channel 1 capture/compare function enable
0x40000C20 C FIELD 05w01 CH1P: Channel 1 capture/compare function polarity
0x40000C20 C FIELD 07w01 CH1NP: Channel 1 complementary output polarity
0x40000C20 C FIELD 08w01 CH2EN: Channel 2 capture/compare function enable
0x40000C20 C FIELD 09w01 CH2P: Channel 2 capture/compare function polarity
0x40000C20 C FIELD 11w01 CH2NP: Channel 2 complementary output polarity
0x40000C20 C FIELD 12w01 CH3EN: Channel 3 capture/compare function enable
0x40000C20 C FIELD 13w01 CH3P: Channel 3 capture/compare function polarity
0x40000C20 C FIELD 15w01 CH3NP: Channel 3 complementary output polarity
0x40000C24 B REGISTER CNT (rw): Counter register
0x40000C24 C FIELD 00w16 CNT: counter value
0x40000C28 B REGISTER PSC (rw): Prescaler register
0x40000C28 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x40000C2C B REGISTER CAR (rw): Counter auto reload register
0x40000C2C C FIELD 00w16 CAR: Counter auto reload value
0x40000C34 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40000C34 C FIELD 00w16 CH0VAL: Capture or compare value of channel 0
0x40000C38 B REGISTER CH1CV (rw): Channel 1 capture/compare value register
0x40000C38 C FIELD 00w16 CH1VAL: Capture or compare value of channel1
0x40000C3C B REGISTER CH2CV (rw): Channel 2 capture/compare value register
0x40000C3C C FIELD 00w16 CH2VAL: Capture or compare value of channel 2
0x40000C40 B REGISTER CH3CV (rw): Channel 3 capture/compare value register
0x40000C40 C FIELD 00w16 CH3VAL: Capture or compare value of channel 3
0x40000C48 B REGISTER DMACFG (rw): DMA configuration register
0x40000C48 C FIELD 00w05 DMATA: DMA transfer access start address
0x40000C48 C FIELD 08w05 DMATC: DMA transfer count
0x40000C4C B REGISTER DMATB (rw): DMA transfer buffer register
0x40000C4C C FIELD 00w16 DMATB: DMA transfer buffer
0x40000CFC B REGISTER CFG (rw): Configuration
0x40000CFC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40001000 A PERIPHERAL TIMER5
0x40001000 B REGISTER CTL0 (rw): control register 0
0x40001000 C FIELD 00w01 CEN: Counter enable
0x40001000 C FIELD 01w01 UPDIS: Update disable
0x40001000 C FIELD 02w01 UPS: Update source
0x40001000 C FIELD 03w01 SPM: Single pulse mode
0x40001000 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40001004 B REGISTER CTL1 (rw): control register 1
0x40001004 C FIELD 04w03 MMC: Master mode control
0x4000100C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000100C C FIELD 00w01 UPIE: Update interrupt enable
0x4000100C C FIELD 08w01 UPDEN: Update DMA request enable
0x40001010 B REGISTER INTF (rw): Interrupt flag register
0x40001010 C FIELD 00w01 UPIF: Update interrupt flag
0x40001014 B REGISTER SWEVG (wo): event generation register
0x40001014 C FIELD 00w01 UPG: Update generation
0x40001024 B REGISTER CNT (rw): Counter register
0x40001024 C FIELD 00w16 CNT: Low counter value
0x40001028 B REGISTER PSC (rw): Prescaler register
0x40001028 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000102C B REGISTER CAR (rw): Counter auto reload register
0x4000102C C FIELD 00w16 CAR: Counter auto reload value
0x40001400 A PERIPHERAL TIMER6
0x40001400 B REGISTER CTL0 (rw): control register 0
0x40001400 C FIELD 00w01 CEN: Counter enable
0x40001400 C FIELD 01w01 UPDIS: Update disable
0x40001400 C FIELD 02w01 UPS: Update source
0x40001400 C FIELD 03w01 SPM: Single pulse mode
0x40001400 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40001404 B REGISTER CTL1 (rw): control register 1
0x40001404 C FIELD 04w03 MMC: Master mode control
0x4000140C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000140C C FIELD 00w01 UPIE: Update interrupt enable
0x4000140C C FIELD 08w01 UPDEN: Update DMA request enable
0x40001410 B REGISTER INTF (rw): Interrupt flag register
0x40001410 C FIELD 00w01 UPIF: Update interrupt flag
0x40001414 B REGISTER SWEVG (wo): event generation register
0x40001414 C FIELD 00w01 UPG: Update generation
0x40001424 B REGISTER CNT (rw): Counter register
0x40001424 C FIELD 00w16 CNT: Low counter value
0x40001428 B REGISTER PSC (rw): Prescaler register
0x40001428 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000142C B REGISTER CAR (rw): Counter auto reload register
0x4000142C C FIELD 00w16 CAR: Counter auto reload value
0x40001800 A PERIPHERAL TIMER11
0x40001800 B REGISTER CTL0 (rw): control register 0
0x40001800 C FIELD 00w01 CEN: Counter enable
0x40001800 C FIELD 01w01 UPDIS: Update disable
0x40001800 C FIELD 02w01 UPS: Update source
0x40001800 C FIELD 03w01 SPM: Single pulse mode
0x40001800 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40001800 C FIELD 08w02 CKDIV: Clock division
0x40001808 B REGISTER SMCFG (rw): slave mode configuration register
0x40001808 C FIELD 00w03 SMC: Slave mode control
0x40001808 C FIELD 04w03 TRGS: Trigger selection
0x40001808 C FIELD 07w01 MSM: Master-slave mode
0x4000180C B REGISTER DMAINTEN (rw): DMA and interrupt enable register
0x4000180C C FIELD 00w01 UPIE: Update interrupt enable
0x4000180C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x4000180C C FIELD 02w01 CH1IE: Channel 1 capture/compare interrupt enable
0x4000180C C FIELD 06w01 TRGIE: Trigger interrupt enable
0x40001810 B REGISTER INTF (rw): interrupt flag register
0x40001810 C FIELD 00w01 UPIF: Update interrupt flag
0x40001810 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40001810 C FIELD 02w01 CH1IF: Channel 1 capture/compare interrupt flag
0x40001810 C FIELD 06w01 TRGIF: Trigger interrupt flag
0x40001810 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40001810 C FIELD 10w01 CH1OF: Channel 1 over capture flag
0x40001814 B REGISTER SWEVG (wo): event generation register
0x40001814 C FIELD 00w01 UPG: Update generation
0x40001814 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40001814 C FIELD 02w01 CH1G: Channel 1 capture or compare event generation
0x40001814 C FIELD 06w01 TRGG: Trigger event generation
0x40001818 B REGISTER CHCTL0_Input (rw): Channel control register 0 (input mode)
0x40001818 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40001818 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40001818 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40001818 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40001818 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40001818 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40001818 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40001818 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40001818 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40001818 C FIELD 08w02 CH1MS: Channel 1 mode selection
0x40001818 C FIELD 10w01 CH1COMFEN: Channel 1 output compare fast enable
0x40001818 C FIELD 10w02 CH1CAPPSC: Channel 1 input capture prescaler
0x40001818 C FIELD 11w01 CH1COMSEN: Channel 1 output compare shadow enable
0x40001818 C FIELD 12w03 CH1COMCTL: Channel 1 compare output control
0x40001818 C FIELD 12w04 CH1CAPFLT: Channel 1 input capture filter control
0x40001820 B REGISTER CHCTL2 (rw): Channel control register 2
0x40001820 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40001820 C FIELD 01w01 CH0P: Channel 0 capture/compare function polarity
0x40001820 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40001820 C FIELD 04w01 CH1EN: Channel 1 capture/compare function enable
0x40001820 C FIELD 05w01 CH1P: Channel 1 capture/compare function polarity
0x40001820 C FIELD 07w01 CH1NP: Channel 1 complementary output polarity
0x40001824 B REGISTER CNT (rw): Counter register
0x40001824 C FIELD 00w16 CNT: current counter value
0x40001828 B REGISTER PSC (rw): Prescaler register
0x40001828 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000182C B REGISTER CAR (rw): Counter auto reload register
0x4000182C C FIELD 00w16 CAR: Counter auto reload value
0x40001834 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40001834 C FIELD 00w16 CH0VAL: Capture or compare value of channel0
0x40001838 B REGISTER CH1CV (rw): Channel 1 capture/compare value register
0x40001838 C FIELD 00w16 CH1VAL: Capture or compare value of channel1
0x400018FC B REGISTER CFG (rw): configuration register
0x400018FC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40001C00 A PERIPHERAL TIMER12
0x40001C00 B REGISTER CTL0 (rw): control register 0
0x40001C00 C FIELD 00w01 CEN: Counter enable
0x40001C00 C FIELD 01w01 UPDIS: Update disable
0x40001C00 C FIELD 02w01 UPS: Update source
0x40001C00 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40001C00 C FIELD 08w02 CKDIV: Clock division
0x40001C04 B REGISTER CTL1 (rw): control register 1
0x40001C04 C FIELD 04w03 MMC: Master mode control
0x40001C0C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x40001C0C C FIELD 00w01 UPIE: Update interrupt enable
0x40001C0C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x40001C10 B REGISTER INTF (rw): interrupt flag register
0x40001C10 C FIELD 00w01 UPIF: Update interrupt flag
0x40001C10 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40001C10 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40001C14 B REGISTER SWEVG (wo): event generation register
0x40001C14 C FIELD 00w01 UPG: Update generation
0x40001C14 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40001C18 B REGISTER CHCTL0_Input (rw): Channel control register 0 ( (input mode)
0x40001C18 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40001C18 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40001C18 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40001C18 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40001C18 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40001C18 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40001C18 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40001C18 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40001C20 B REGISTER CHCTL2 (rw): Channel control register 2
0x40001C20 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40001C20 C FIELD 01w01 CH0P: Channel 0 capture/compare polarity
0x40001C20 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40001C24 B REGISTER CNT (rw): Counter register
0x40001C24 C FIELD 00w16 CNT: current counter value
0x40001C28 B REGISTER PSC (rw): Prescaler register
0x40001C28 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x40001C2C B REGISTER CAR (rw): Counter auto reload register
0x40001C2C C FIELD 00w16 CAR: Counter auto reload value
0x40001C34 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40001C34 C FIELD 00w16 CH0VAL: Capture or compare value of channel 0
0x40001CFC B REGISTER CFG (rw): configuration register
0x40001CFC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40002000 A PERIPHERAL TIMER13
0x40002000 B REGISTER CTL0 (rw): control register 0
0x40002000 C FIELD 00w01 CEN: Counter enable
0x40002000 C FIELD 01w01 UPDIS: Update disable
0x40002000 C FIELD 02w01 UPS: Update source
0x40002000 C FIELD 07w01 ARSE: Auto-reload shadow enable
0x40002000 C FIELD 08w02 CKDIV: Clock division
0x40002004 B REGISTER CTL1 (rw): control register 1
0x40002004 C FIELD 04w03 MMC: Master mode control
0x4000200C B REGISTER DMAINTEN (rw): DMA/Interrupt enable register
0x4000200C C FIELD 00w01 UPIE: Update interrupt enable
0x4000200C C FIELD 01w01 CH0IE: Channel 0 capture/compare interrupt enable
0x40002010 B REGISTER INTF (rw): interrupt flag register
0x40002010 C FIELD 00w01 UPIF: Update interrupt flag
0x40002010 C FIELD 01w01 CH0IF: Channel 0 capture/compare interrupt flag
0x40002010 C FIELD 09w01 CH0OF: Channel 0 over capture flag
0x40002014 B REGISTER SWEVG (wo): event generation register
0x40002014 C FIELD 00w01 UPG: Update generation
0x40002014 C FIELD 01w01 CH0G: Channel 0 capture or compare event generation
0x40002018 B REGISTER CHCTL0_Input (rw): Channel control register 0 ( (input mode)
0x40002018 B REGISTER CHCTL0_Output (rw): Channel control register 0 (output mode)
0x40002018 C FIELD 00w02 CH0MS: Channel 0 I/O mode selection
0x40002018 C FIELD 00w02 CH0MS: Channel 0 mode selection
0x40002018 C FIELD 02w01 CH0COMFEN: Channel 0 output compare fast enable
0x40002018 C FIELD 02w02 CH0CAPPSC: Channel 0 input capture prescaler
0x40002018 C FIELD 03w01 CH0COMSEN: Channel 0 compare output shadow enable
0x40002018 C FIELD 04w03 CH0COMCTL: Channel 0 compare output control
0x40002018 C FIELD 04w04 CH0CAPFLT: Channel 0 input capture filter control
0x40002020 B REGISTER CHCTL2 (rw): Channel control register 2
0x40002020 C FIELD 00w01 CH0EN: Channel 0 capture/compare function enable
0x40002020 C FIELD 01w01 CH0P: Channel 0 capture/compare polarity
0x40002020 C FIELD 03w01 CH0NP: Channel 0 complementary output polarity
0x40002024 B REGISTER CNT (rw): Counter register
0x40002024 C FIELD 00w16 CNT: current counter value
0x40002028 B REGISTER PSC (rw): Prescaler register
0x40002028 C FIELD 00w16 PSC: Prescaler value of the counter clock
0x4000202C B REGISTER CAR (rw): Counter auto reload register
0x4000202C C FIELD 00w16 CAR: Counter auto reload value
0x40002034 B REGISTER CH0CV (rw): Channel 0 capture/compare value register
0x40002034 C FIELD 00w16 CH0VAL: Capture or compare value of channel 0
0x400020FC B REGISTER CFG (rw): configuration register
0x400020FC C FIELD 01w01 CHVSEL: Write CHxVAL register selection
0x40002800 A PERIPHERAL RTC
0x40002800 B REGISTER INTEN (rw): RTC interrupt enable register
0x40002800 C FIELD 00w01 SCIE: Second interrupt
0x40002800 C FIELD 01w01 ALRMIE: Alarm interrupt enable
0x40002800 C FIELD 02w01 OVIE: Overflow interrupt enable
0x40002804 B REGISTER CTL: control register
0x40002804 C FIELD 00w01 SCIF (rw): Sencond interrupt flag
0x40002804 C FIELD 01w01 ALRMIF (rw): Alarm interrupt flag
0x40002804 C FIELD 02w01 OVIF (rw): Overflow interrupt flag
0x40002804 C FIELD 03w01 RSYNF (rw): Registers synchronized flag
0x40002804 C FIELD 04w01 CMF (rw): Configuration mode flag
0x40002804 C FIELD 05w01 LWOFF (ro): Last write operation finished flag
0x40002808 B REGISTER PSCH: RTC prescaler high register
0x40002808 C FIELD 00w04 PSC (wo): RTC prescaler value high
0x4000280C B REGISTER PSCL: RTC prescaler low register
0x4000280C C FIELD 00w16 PSC (wo): RTC prescaler value low
0x40002810 B REGISTER DIVH (ro): RTC divider high register
0x40002810 C FIELD 00w04 DIV: RTC divider value high
0x40002814 B REGISTER DIVL (ro): RTC divider low register
0x40002814 C FIELD 00w16 DIV: RTC divider value low
0x40002818 B REGISTER CNTH (rw): RTC counter high register
0x40002818 C FIELD 00w16 CNT: RTC counter value high
0x4000281C B REGISTER CNTL (rw): RTC counter low register
0x4000281C C FIELD 00w16 CNT: RTC conuter value low
0x40002820 B REGISTER ALRMH (wo): Alarm high register
0x40002820 C FIELD 00w16 ALRM: Alarm value high
0x40002824 B REGISTER ALRML (wo): RTC alarm low register
0x40002824 C FIELD 00w16 ALRM: alarm value low
0x40002C00 A PERIPHERAL WWDGT
0x40002C00 B REGISTER CTL (rw): Control register
0x40002C00 C FIELD 00w07 CNT: 7-bit counter
0x40002C00 C FIELD 07w01 WDGTEN: Activation bit
0x40002C04 B REGISTER CFG (rw): Configuration register
0x40002C04 C FIELD 00w07 WIN: 7-bit window value
0x40002C04 C FIELD 07w02 PSC: Prescaler
0x40002C04 C FIELD 09w01 EWIE: Early wakeup interrupt
0x40002C08 B REGISTER STAT (rw): Status register
0x40002C08 C FIELD 00w01 EWIF: Early wakeup interrupt flag
0x40003000 A PERIPHERAL FWDGT
0x40003000 B REGISTER CTL (wo): Control register
0x40003000 C FIELD 00w16 CMD: Key value
0x40003004 B REGISTER PSC (rw): Prescaler register
0x40003004 C FIELD 00w03 PSC: Free watchdog timer prescaler selection
0x40003008 B REGISTER RLD (rw): Reload register
0x40003008 C FIELD 00w12 RLD: Free watchdog timer counter reload value
0x4000300C B REGISTER STAT (ro): Status register
0x4000300C C FIELD 00w01 PUD: Free watchdog timer prescaler value update
0x4000300C C FIELD 01w01 RUD: Free watchdog timer counter reload value update
0x40003800 A PERIPHERAL SPI1
0x40003800 B REGISTER CTL0 (rw): control register 0
0x40003800 C FIELD 00w01 CKPH: Clock Phase Selection
0x40003800 C FIELD 01w01 CKPL: Clock polarity Selection
0x40003800 C FIELD 02w01 MSTMOD: Master Mode Enable
0x40003800 C FIELD 03w03 PSC: Master Clock Prescaler Selection
0x40003800 C FIELD 06w01 SPIEN: SPI enable
0x40003800 C FIELD 07w01 LF: LSB First Mode
0x40003800 C FIELD 08w01 SWNSS: NSS Pin Selection In NSS Software Mode
0x40003800 C FIELD 09w01 SWNSSEN: NSS Software Mode Selection
0x40003800 C FIELD 10w01 RO: Receive only
0x40003800 C FIELD 11w01 FF16: Data frame format
0x40003800 C FIELD 12w01 CRCNT: CRC Next Transfer
0x40003800 C FIELD 13w01 CRCEN: CRC Calculation Enable
0x40003800 C FIELD 14w01 BDOEN: Bidirectional Transmit output enable
0x40003800 C FIELD 15w01 BDEN: Bidirectional enable
0x40003804 B REGISTER CTL1 (rw): control register 1
0x40003804 C FIELD 00w01 DMAREN: Rx buffer DMA enable
0x40003804 C FIELD 01w01 DMATEN: Transmit Buffer DMA Enable
0x40003804 C FIELD 02w01 NSSDRV: Drive NSS Output
0x40003804 C FIELD 03w01 NSSP: SPI NSS pulse mode Enable
0x40003804 C FIELD 04w01 TMOD: SPI TI Mode Enable
0x40003804 C FIELD 05w01 ERRIE: Error interrupt enable
0x40003804 C FIELD 06w01 RBNEIE: RX buffer not empty interrupt enable
0x40003804 C FIELD 07w01 TBEIE: Tx buffer empty interrupt enable
0x40003808 B REGISTER STAT: status register
0x40003808 C FIELD 00w01 RBNE (ro): Receive Buffer Not Empty
0x40003808 C FIELD 01w01 TBE (ro): Transmit Buffer Empty
0x40003808 C FIELD 02w01 I2SCH (ro): I2S channel side
0x40003808 C FIELD 03w01 TXURERR (ro): Transmission underrun error bit
0x40003808 C FIELD 04w01 CRCERR (rw): SPI CRC Error Bit
0x40003808 C FIELD 05w01 CONFERR (ro): SPI Configuration error
0x40003808 C FIELD 06w01 RXORERR (ro): Reception Overrun Error Bit
0x40003808 C FIELD 07w01 TRANS (ro): Transmitting On-going Bit
0x40003808 C FIELD 08w01 FERR (rw): Format Error
0x4000380C B REGISTER DATA (rw): data register
0x4000380C C FIELD 00w16 DATA: Data transfer register
0x40003810 B REGISTER CRCPOLY (rw): CRC polynomial register
0x40003810 C FIELD 00w16 CRCPOLY: CRC polynomial register
0x40003814 B REGISTER RCRC (ro): RX CRC register
0x40003814 C FIELD 00w16 RCRC: RX CRC register
0x40003818 B REGISTER TCRC (ro): TX CRC register
0x40003818 C FIELD 00w16 TCRC: Tx CRC register
0x4000381C B REGISTER I2SCTL (rw): I2S control register
0x4000381C C FIELD 00w01 CHLEN: Channel length (number of bits per audio channel)
0x4000381C C FIELD 01w02 DTLEN: Data length
0x4000381C C FIELD 03w01 CKPL: Idle state clock polarity
0x4000381C C FIELD 04w02 I2SSTD: I2S standard selection
0x4000381C C FIELD 07w01 PCMSMOD: PCM frame synchronization mode
0x4000381C C FIELD 08w02 I2SOPMOD: I2S operation mode
0x4000381C C FIELD 10w01 I2SEN: I2S Enable
0x4000381C C FIELD 11w01 I2SSEL: I2S mode selection
0x40003820 B REGISTER I2SPSC (rw): I2S prescaler register
0x40003820 C FIELD 00w08 DIV: Dividing factor for the prescaler
0x40003820 C FIELD 08w01 OF: Odd factor for the prescaler
0x40003820 C FIELD 09w01 MCKOEN: I2S_MCK output enable
0x40003C00 A PERIPHERAL SPI2
0x40003C00 B REGISTER CTL0 (rw): control register 0
0x40003C00 C FIELD 00w01 CKPH: Clock Phase Selection
0x40003C00 C FIELD 01w01 CKPL: Clock polarity Selection
0x40003C00 C FIELD 02w01 MSTMOD: Master Mode Enable
0x40003C00 C FIELD 03w03 PSC: Master Clock Prescaler Selection
0x40003C00 C FIELD 06w01 SPIEN: SPI enable
0x40003C00 C FIELD 07w01 LF: LSB First Mode
0x40003C00 C FIELD 08w01 SWNSS: NSS Pin Selection In NSS Software Mode
0x40003C00 C FIELD 09w01 SWNSSEN: NSS Software Mode Selection
0x40003C00 C FIELD 10w01 RO: Receive only
0x40003C00 C FIELD 11w01 FF16: Data frame format
0x40003C00 C FIELD 12w01 CRCNT: CRC Next Transfer
0x40003C00 C FIELD 13w01 CRCEN: CRC Calculation Enable
0x40003C00 C FIELD 14w01 BDOEN: Bidirectional Transmit output enable
0x40003C00 C FIELD 15w01 BDEN: Bidirectional enable
0x40003C04 B REGISTER CTL1 (rw): control register 1
0x40003C04 C FIELD 00w01 DMAREN: Rx buffer DMA enable
0x40003C04 C FIELD 01w01 DMATEN: Transmit Buffer DMA Enable
0x40003C04 C FIELD 02w01 NSSDRV: Drive NSS Output
0x40003C04 C FIELD 03w01 NSSP: SPI NSS pulse mode Enable
0x40003C04 C FIELD 04w01 TMOD: SPI TI Mode Enable
0x40003C04 C FIELD 05w01 ERRIE: Error interrupt enable
0x40003C04 C FIELD 06w01 RBNEIE: RX buffer not empty interrupt enable
0x40003C04 C FIELD 07w01 TBEIE: Tx buffer empty interrupt enable
0x40003C08 B REGISTER STAT: status register
0x40003C08 C FIELD 00w01 RBNE (ro): Receive Buffer Not Empty
0x40003C08 C FIELD 01w01 TBE (ro): Transmit Buffer Empty
0x40003C08 C FIELD 02w01 I2SCH (ro): I2S channel side
0x40003C08 C FIELD 03w01 TXURERR (ro): Transmission underrun error bit
0x40003C08 C FIELD 04w01 CRCERR (rw): SPI CRC Error Bit
0x40003C08 C FIELD 05w01 CONFERR (ro): SPI Configuration error
0x40003C08 C FIELD 06w01 RXORERR (ro): Reception Overrun Error Bit
0x40003C08 C FIELD 07w01 TRANS (ro): Transmitting On-going Bit
0x40003C08 C FIELD 08w01 FERR (rw): Format Error
0x40003C0C B REGISTER DATA (rw): data register
0x40003C0C C FIELD 00w16 DATA: Data transfer register
0x40003C10 B REGISTER CRCPOLY (rw): CRC polynomial register
0x40003C10 C FIELD 00w16 CRCPOLY: CRC polynomial register
0x40003C14 B REGISTER RCRC (ro): RX CRC register
0x40003C14 C FIELD 00w16 RCRC: RX CRC register
0x40003C18 B REGISTER TCRC (ro): TX CRC register
0x40003C18 C FIELD 00w16 TCRC: Tx CRC register
0x40003C1C B REGISTER I2SCTL (rw): I2S control register
0x40003C1C C FIELD 00w01 CHLEN: Channel length (number of bits per audio channel)
0x40003C1C C FIELD 01w02 DTLEN: Data length
0x40003C1C C FIELD 03w01 CKPL: Idle state clock polarity
0x40003C1C C FIELD 04w02 I2SSTD: I2S standard selection
0x40003C1C C FIELD 07w01 PCMSMOD: PCM frame synchronization mode
0x40003C1C C FIELD 08w02 I2SOPMOD: I2S operation mode
0x40003C1C C FIELD 10w01 I2SEN: I2S Enable
0x40003C1C C FIELD 11w01 I2SSEL: I2S mode selection
0x40003C20 B REGISTER I2SPSC (rw): I2S prescaler register
0x40003C20 C FIELD 00w08 DIV: Dividing factor for the prescaler
0x40003C20 C FIELD 08w01 OF: Odd factor for the prescaler
0x40003C20 C FIELD 09w01 MCKOEN: I2S_MCK output enable
0x40003C80 B REGISTER QCTL (rw): Quad-SPI mode control register
0x40003C80 C FIELD 00w01 QMOD: Quad-SPI mode enable
0x40003C80 C FIELD 01w01 QRD: Quad-SPI mode read select
0x40003C80 C FIELD 02w01 IO23_DRV: Drive IO2 and IO3 enable
0x40004400 A PERIPHERAL USART1
0x40004400 B REGISTER STAT0 (ro): Status register 0
0x40004400 C FIELD 00w01 PERR: Parity error flag
0x40004400 C FIELD 01w01 FERR: Frame error flag
0x40004400 C FIELD 02w01 NERR: Noise error flag
0x40004400 C FIELD 03w01 ORERR: Overrun error
0x40004400 C FIELD 04w01 IDLEF: IDLE frame detected flag
0x40004400 C FIELD 05w01 RBNE: Read data buffer not empty
0x40004400 C FIELD 06w01 TC: Transmission complete
0x40004400 C FIELD 07w01 TBE: Transmit data buffer empty
0x40004400 C FIELD 08w01 LBDF: LIN break detection flag
0x40004400 C FIELD 09w01 CTSF: CTS change flag
0x40004404 B REGISTER DATA (rw): Data register
0x40004404 C FIELD 00w09 DATA: Transmit or read data value
0x40004408 B REGISTER BAUD (rw): Baud rate register
0x40004408 C FIELD 00w04 FRADIV: Fraction part of baud-rate divider
0x40004408 C FIELD 04w12 INTDIV: Integer part of baud-rate divider
0x4000440C B REGISTER CTL0 (rw): Control register 0
0x4000440C C FIELD 00w01 SBKCMD: Send break command
0x4000440C C FIELD 01w01 RWU: Receiver wakeup from mute mode
0x4000440C C FIELD 02w01 REN: Receiver enable
0x4000440C C FIELD 03w01 TEN: Transmitter enable
0x4000440C C FIELD 04w01 IDLEIE: IDLE line detected interrupt enable
0x4000440C C FIELD 05w01 RBNEIE: Read data buffer not empty interrupt and overrun error interrupt enable
0x4000440C C FIELD 06w01 TCIE: Transmission complete interrupt enable
0x4000440C C FIELD 07w01 TBEIE: Transmitter buffer empty interrupt enable
0x4000440C C FIELD 08w01 PERRIE: Parity error interrupt enable
0x4000440C C FIELD 09w01 PM: Parity mode
0x4000440C C FIELD 10w01 PCEN: Parity check function enable
0x4000440C C FIELD 11w01 WM: Wakeup method in mute mode
0x4000440C C FIELD 12w01 WL: Word length
0x4000440C C FIELD 13w01 UEN: USART enable
0x4000440C C FIELD 15w01 OVSMOD: Oversampe mode
0x40004410 B REGISTER CTL1 (rw): Control register 1
0x40004410 C FIELD 00w04 ADDR: Address of the USART
0x40004410 C FIELD 05w01 LBLEN: LIN break frame length
0x40004410 C FIELD 06w01 LBDIE: LIN break detection interrupt enable
0x40004410 C FIELD 08w01 CLEN: CK Length
0x40004410 C FIELD 09w01 CPH: Clock phase
0x40004410 C FIELD 10w01 CPL: Clock polarity
0x40004410 C FIELD 11w01 CKEN: CK pin enable
0x40004410 C FIELD 12w02 STB: STOP bits length
0x40004410 C FIELD 14w01 LMEN: LIN mode enable
0x40004414 B REGISTER CTL2 (rw): Control register 2
0x40004414 C FIELD 00w01 ERRIE: Error interrupt enable
0x40004414 C FIELD 01w01 IREN: IrDA mode enable
0x40004414 C FIELD 02w01 IRLP: IrDA low-power
0x40004414 C FIELD 03w01 HDEN: Half-duplex selection
0x40004414 C FIELD 04w01 NKEN: Smartcard NACK enable
0x40004414 C FIELD 05w01 SCEN: Smartcard mode enable
0x40004414 C FIELD 06w01 DENR: DMA request enable for reception
0x40004414 C FIELD 07w01 DENT: DMA request enable for transmission
0x40004414 C FIELD 08w01 RTSEN: RTS enable
0x40004414 C FIELD 09w01 CTSEN: CTS enable
0x40004414 C FIELD 10w01 CTSIE: CTS interrupt enable
0x40004414 C FIELD 11w01 OSB: One sample bit method
0x40004418 B REGISTER GP (rw): Guard time and prescaler register
0x40004418 C FIELD 00w08 PSC: Prescaler value
0x40004418 C FIELD 08w08 GUAT: Guard time value in Smartcard mode
0x40004480 B REGISTER CTL3 (rw): Control register 3
0x40004480 C FIELD 00w01 RTEN: Receiver timeout enable
0x40004480 C FIELD 01w03 SCRTNUM: Smartcard auto-retry number
0x40004480 C FIELD 04w01 RTIE: Interrupt enable bit of receive timeout event
0x40004480 C FIELD 05w01 EBIE: Interrupt enable bit of end of block event
0x40004480 C FIELD 08w01 RINV: RX pin level inversion
0x40004480 C FIELD 09w01 TINV: TX pin level inversion
0x40004480 C FIELD 10w01 DINV: Data bit level inversion
0x40004480 C FIELD 11w01 MSBF: Most significant bit first
0x40004484 B REGISTER RT (rw): Receiver timeout register
0x40004484 C FIELD 00w24 RT: Receiver timeout threshold
0x40004484 C FIELD 24w08 BL: Block Length
0x40004488 B REGISTER STAT1: Status register 1
0x40004488 C FIELD 11w01 RTF (wo): Receiver timeout flag
0x40004488 C FIELD 12w01 EBF (wo): End of block flag
0x40004488 C FIELD 16w01 BSY (ro): Busy flag
0x400044D0 B REGISTER GDCTL: GD control register
0x400044D0 C FIELD 01w01 CDEN (rw): Collision detection enable
0x400044D0 C FIELD 08w01 CD (wo): Collision detected status
0x400044D0 C FIELD 16w01 CDIE (rw): Collision detected interrupt enable
0x40004800 A PERIPHERAL USART2
0x40004800 B REGISTER STAT0 (ro): Status register 0
0x40004800 C FIELD 00w01 PERR: Parity error flag
0x40004800 C FIELD 01w01 FERR: Frame error flag
0x40004800 C FIELD 02w01 NERR: Noise error flag
0x40004800 C FIELD 03w01 ORERR: Overrun error
0x40004800 C FIELD 04w01 IDLEF: IDLE frame detected flag
0x40004800 C FIELD 05w01 RBNE: Read data buffer not empty
0x40004800 C FIELD 06w01 TC: Transmission complete
0x40004800 C FIELD 07w01 TBE: Transmit data buffer empty
0x40004800 C FIELD 08w01 LBDF: LIN break detection flag
0x40004800 C FIELD 09w01 CTSF: CTS change flag
0x40004804 B REGISTER DATA (rw): Data register
0x40004804 C FIELD 00w09 DATA: Transmit or read data value
0x40004808 B REGISTER BAUD (rw): Baud rate register
0x40004808 C FIELD 00w04 FRADIV: Fraction part of baud-rate divider
0x40004808 C FIELD 04w12 INTDIV: Integer part of baud-rate divider
0x4000480C B REGISTER CTL0 (rw): Control register 0
0x4000480C C FIELD 00w01 SBKCMD: Send break command
0x4000480C C FIELD 01w01 RWU: Receiver wakeup from mute mode
0x4000480C C FIELD 02w01 REN: Receiver enable
0x4000480C C FIELD 03w01 TEN: Transmitter enable
0x4000480C C FIELD 04w01 IDLEIE: IDLE line detected interrupt enable
0x4000480C C FIELD 05w01 RBNEIE: Read data buffer not empty interrupt and overrun error interrupt enable
0x4000480C C FIELD 06w01 TCIE: Transmission complete interrupt enable
0x4000480C C FIELD 07w01 TBEIE: Transmitter buffer empty interrupt enable
0x4000480C C FIELD 08w01 PERRIE: Parity error interrupt enable
0x4000480C C FIELD 09w01 PM: Parity mode
0x4000480C C FIELD 10w01 PCEN: Parity check function enable
0x4000480C C FIELD 11w01 WM: Wakeup method in mute mode
0x4000480C C FIELD 12w01 WL: Word length
0x4000480C C FIELD 13w01 UEN: USART enable
0x4000480C C FIELD 15w01 OVSMOD: Oversampe mode
0x40004810 B REGISTER CTL1 (rw): Control register 1
0x40004810 C FIELD 00w04 ADDR: Address of the USART
0x40004810 C FIELD 05w01 LBLEN: LIN break frame length
0x40004810 C FIELD 06w01 LBDIE: LIN break detection interrupt enable
0x40004810 C FIELD 08w01 CLEN: CK Length
0x40004810 C FIELD 09w01 CPH: Clock phase
0x40004810 C FIELD 10w01 CPL: Clock polarity
0x40004810 C FIELD 11w01 CKEN: CK pin enable
0x40004810 C FIELD 12w02 STB: STOP bits length
0x40004810 C FIELD 14w01 LMEN: LIN mode enable
0x40004814 B REGISTER CTL2 (rw): Control register 2
0x40004814 C FIELD 00w01 ERRIE: Error interrupt enable
0x40004814 C FIELD 01w01 IREN: IrDA mode enable
0x40004814 C FIELD 02w01 IRLP: IrDA low-power
0x40004814 C FIELD 03w01 HDEN: Half-duplex selection
0x40004814 C FIELD 04w01 NKEN: Smartcard NACK enable
0x40004814 C FIELD 05w01 SCEN: Smartcard mode enable
0x40004814 C FIELD 06w01 DENR: DMA request enable for reception
0x40004814 C FIELD 07w01 DENT: DMA request enable for transmission
0x40004814 C FIELD 08w01 RTSEN: RTS enable
0x40004814 C FIELD 09w01 CTSEN: CTS enable
0x40004814 C FIELD 10w01 CTSIE: CTS interrupt enable
0x40004814 C FIELD 11w01 OSB: One sample bit method
0x40004818 B REGISTER GP (rw): Guard time and prescaler register
0x40004818 C FIELD 00w08 PSC: Prescaler value
0x40004818 C FIELD 08w08 GUAT: Guard time value in Smartcard mode
0x40004880 B REGISTER CTL3 (rw): Control register 3
0x40004880 C FIELD 00w01 RTEN: Receiver timeout enable
0x40004880 C FIELD 01w03 SCRTNUM: Smartcard auto-retry number
0x40004880 C FIELD 04w01 RTIE: Interrupt enable bit of receive timeout event
0x40004880 C FIELD 05w01 EBIE: Interrupt enable bit of end of block event
0x40004880 C FIELD 08w01 RINV: RX pin level inversion
0x40004880 C FIELD 09w01 TINV: TX pin level inversion
0x40004880 C FIELD 10w01 DINV: Data bit level inversion
0x40004880 C FIELD 11w01 MSBF: Most significant bit first
0x40004884 B REGISTER RT (rw): Receiver timeout register
0x40004884 C FIELD 00w24 RT: Receiver timeout threshold
0x40004884 C FIELD 24w08 BL: Block Length
0x40004888 B REGISTER STAT1: Status register 1
0x40004888 C FIELD 11w01 RTF (wo): Receiver timeout flag