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Merge tag 'drm-msm-fixes-2025-02-20' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.14-rc4 Display: * More catalog fixes: - to skip watchdog programming through top block if its not present - fix the setting of WB mask to ensure the WB input control is programmed correctly through ping-pong - drop lm_pair for sm6150 as that chipset does not have any 3dmerge block * Fix the mode validation logic for DP/eDP to account for widebus (2ppc) to allow high clock resolutions * Fix to disable dither during encoder disable as otherwise this was causing kms_writeback failure due to resource sharing between * WB and DSI paths as DSI uses dither but WB does not * Fixes for virtual planes, namely to drop extraneous return and fix uninitialized variables * Fix to avoid spill-over of DSC encoder block bits when programming the bits-per-component * Fixes in the DSI PHY to protect against concurrent access of PHY_CMN_CLK_CFG regs between clock and display drivers Core/GPU: * Fix non-blocking fence wait incorrectly rounding up to 1 jiffy timeout * Only print GMU fw version once, instead of each time the GPU resumes Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGtt2AODBXdod8ULXcAygf_qYvwRDVeUVtODx=2jErp6cA@mail.gmail.com
2 parents 930293b + 73f69c6 commit 9a1cd7d

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15 files changed

+75
-49
lines changed

15 files changed

+75
-49
lines changed

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -813,10 +813,10 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
813813
}
814814

815815
ver = gmu_read(gmu, REG_A6XX_GMU_CORE_FW_VERSION);
816-
DRM_INFO("Loaded GMU firmware v%u.%u.%u\n",
817-
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver),
818-
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver),
819-
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver));
816+
DRM_INFO_ONCE("Loaded GMU firmware v%u.%u.%u\n",
817+
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver),
818+
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver),
819+
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver));
820820

821821
return 0;
822822
}

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
297297
{
298298
.name = "wb_2", .id = WB_2,
299299
.base = 0x65000, .len = 0x2c8,
300-
.features = WB_SDM845_MASK,
300+
.features = WB_SM8250_MASK,
301301
.format_list = wb2_formats_rgb,
302302
.num_formats = ARRAY_SIZE(wb2_formats_rgb),
303303
.clk_ctrl = DPU_CLK_CTRL_WB2,

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
304304
{
305305
.name = "wb_2", .id = WB_2,
306306
.base = 0x65000, .len = 0x2c8,
307-
.features = WB_SDM845_MASK,
307+
.features = WB_SM8250_MASK,
308308
.format_list = wb2_formats_rgb,
309309
.num_formats = ARRAY_SIZE(wb2_formats_rgb),
310310
.clk_ctrl = DPU_CLK_CTRL_WB2,

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,14 +116,12 @@ static const struct dpu_lm_cfg sm6150_lm[] = {
116116
.sblk = &sdm845_lm_sblk,
117117
.pingpong = PINGPONG_0,
118118
.dspp = DSPP_0,
119-
.lm_pair = LM_1,
120119
}, {
121120
.name = "lm_1", .id = LM_1,
122121
.base = 0x45000, .len = 0x320,
123122
.features = MIXER_QCM2290_MASK,
124123
.sblk = &sdm845_lm_sblk,
125124
.pingpong = PINGPONG_1,
126-
.lm_pair = LM_0,
127125
}, {
128126
.name = "lm_2", .id = LM_2,
129127
.base = 0x46000, .len = 0x320,

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
144144
{
145145
.name = "wb_2", .id = WB_2,
146146
.base = 0x65000, .len = 0x2c8,
147-
.features = WB_SDM845_MASK,
147+
.features = WB_SM8250_MASK,
148148
.format_list = wb2_formats_rgb,
149149
.num_formats = ARRAY_SIZE(wb2_formats_rgb),
150150
.clk_ctrl = DPU_CLK_CTRL_WB2,

‎drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1228,8 +1228,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
12281228
done:
12291229
kfree(states);
12301230
return ret;
1231-
1232-
return 0;
12331231
}
12341232

12351233
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2281,6 +2281,9 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
22812281
}
22822282
}
22832283

2284+
if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2285+
phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2286+
22842287
/* reset the merge 3D HW block */
22852288
if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
22862289
phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
5252
u32 slice_last_group_size;
5353
u32 det_thresh_flatness;
5454
bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
55+
bool input_10_bits = dsc->bits_per_component == 10;
5556

5657
DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
5758

@@ -68,7 +69,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
6869
data |= (dsc->line_buf_depth << 3);
6970
data |= (dsc->simple_422 << 2);
7071
data |= (dsc->convert_rgb << 1);
71-
data |= dsc->bits_per_component;
72+
data |= input_10_bits;
7273

7374
DPU_REG_WRITE(c, DSC_ENC, data);
7475

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
272272

273273
if (cap & BIT(DPU_MDP_VSYNC_SEL))
274274
ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
275-
else
275+
else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
276276
ops->setup_vsync_source = dpu_hw_setup_wd_timer;
277277

278278
ops->get_safe_status = dpu_hw_get_safe_status;

‎drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1164,7 +1164,6 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state,
11641164
unsigned int num_planes)
11651165
{
11661166
unsigned int i;
1167-
int ret;
11681167

11691168
for (i = 0; i < num_planes; i++) {
11701169
struct drm_plane_state *plane_state = states[i];
@@ -1173,13 +1172,13 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state,
11731172
!plane_state->visible)
11741173
continue;
11751174

1176-
ret = dpu_plane_virtual_assign_resources(crtc, global_state,
1175+
int ret = dpu_plane_virtual_assign_resources(crtc, global_state,
11771176
state, plane_state);
11781177
if (ret)
1179-
break;
1178+
return ret;
11801179
}
11811180

1182-
return ret;
1181+
return 0;
11831182
}
11841183

11851184
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)

‎drivers/gpu/drm/msm/dp/dp_display.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -930,16 +930,17 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge,
930930
return -EINVAL;
931931
}
932932

933-
if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
934-
return MODE_CLOCK_HIGH;
935-
936933
msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display);
937934
link_info = &msm_dp_display->panel->link_info;
938935

939-
if (drm_mode_is_420_only(&dp->connector->display_info, mode) &&
940-
msm_dp_display->panel->vsc_sdp_supported)
936+
if ((drm_mode_is_420_only(&dp->connector->display_info, mode) &&
937+
msm_dp_display->panel->vsc_sdp_supported) ||
938+
msm_dp_wide_bus_available(dp))
941939
mode_pclk_khz /= 2;
942940

941+
if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
942+
return MODE_CLOCK_HIGH;
943+
943944
mode_bpp = dp->connector->display_info.bpc * num_components;
944945
if (!mode_bpp)
945946
mode_bpp = default_bpp;

‎drivers/gpu/drm/msm/dp/dp_drm.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -257,7 +257,10 @@ static enum drm_mode_status msm_edp_bridge_mode_valid(struct drm_bridge *bridge,
257257
return -EINVAL;
258258
}
259259

260-
if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
260+
if (msm_dp_wide_bus_available(dp))
261+
mode_pclk_khz /= 2;
262+
263+
if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
261264
return MODE_CLOCK_HIGH;
262265

263266
/*

‎drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

Lines changed: 36 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,9 @@ struct dsi_pll_7nm {
8383
/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
8484
spinlock_t postdiv_lock;
8585

86+
/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */
87+
spinlock_t pclk_mux_lock;
88+
8689
struct pll_7nm_cached_state cached_state;
8790

8891
struct dsi_pll_7nm *slave;
@@ -372,22 +375,41 @@ static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
372375
ndelay(250);
373376
}
374377

375-
static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
378+
static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)
376379
{
380+
unsigned long flags;
381+
382+
spin_lock_irqsave(&pll->postdiv_lock, flags);
383+
writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
384+
spin_unlock_irqrestore(&pll->postdiv_lock, flags);
385+
}
386+
387+
static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
388+
u32 val)
389+
{
390+
unsigned long flags;
377391
u32 data;
378392

393+
spin_lock_irqsave(&pll->pclk_mux_lock, flags);
379394
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
380-
writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
395+
data &= ~mask;
396+
data |= val & mask;
397+
398+
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
399+
spin_unlock_irqrestore(&pll->pclk_mux_lock, flags);
400+
}
401+
402+
static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
403+
{
404+
dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0);
381405
}
382406

383407
static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
384408
{
385-
u32 data;
409+
u32 cfg_1 = DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN_SEL;
386410

387411
writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
388-
389-
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
390-
writel(data | BIT(5) | BIT(4), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
412+
dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1);
391413
}
392414

393415
static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
@@ -565,7 +587,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
565587
{
566588
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
567589
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
568-
void __iomem *phy_base = pll_7nm->phy->base;
569590
u32 val;
570591
int ret;
571592

@@ -574,13 +595,10 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
574595
val |= cached->pll_out_div;
575596
writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
576597

577-
writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
578-
phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
579-
580-
val = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
581-
val &= ~0x3;
582-
val |= cached->pll_mux;
583-
writel(val, phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
598+
dsi_pll_cmn_clk_cfg0_write(pll_7nm,
599+
DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) |
600+
DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div));
601+
dsi_pll_cmn_clk_cfg1_update(pll_7nm, 0x3, cached->pll_mux);
584602

585603
ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
586604
pll_7nm->vco_current_rate,
@@ -599,7 +617,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
599617
static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
600618
{
601619
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
602-
void __iomem *base = phy->base;
603620
u32 data = 0x0; /* internal PLL */
604621

605622
DBG("DSI PLL%d", pll_7nm->phy->id);
@@ -618,7 +635,8 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
618635
}
619636

620637
/* set PLL src */
621-
writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
638+
dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK,
639+
DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL(data));
622640

623641
return 0;
624642
}
@@ -733,7 +751,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
733751
pll_by_2_bit,
734752
}), 2, 0, pll_7nm->phy->base +
735753
REG_DSI_7nm_PHY_CMN_CLK_CFG1,
736-
0, 1, 0, NULL);
754+
0, 1, 0, &pll_7nm->pclk_mux_lock);
737755
if (IS_ERR(hw)) {
738756
ret = PTR_ERR(hw);
739757
goto fail;
@@ -778,6 +796,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
778796
pll_7nm_list[phy->id] = pll_7nm;
779797

780798
spin_lock_init(&pll_7nm->postdiv_lock);
799+
spin_lock_init(&pll_7nm->pclk_mux_lock);
781800

782801
pll_7nm->phy = phy;
783802

‎drivers/gpu/drm/msm/msm_drv.h

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -537,15 +537,12 @@ static inline int align_pitch(int width, int bpp)
537537
static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
538538
{
539539
ktime_t now = ktime_get();
540-
s64 remaining_jiffies;
541540

542-
if (ktime_compare(*timeout, now) < 0) {
543-
remaining_jiffies = 0;
544-
} else {
545-
ktime_t rem = ktime_sub(*timeout, now);
546-
remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
547-
}
541+
if (ktime_compare(*timeout, now) <= 0)
542+
return 0;
548543

544+
ktime_t rem = ktime_sub(*timeout, now);
545+
s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
549546
return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
550547
}
551548

‎drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,15 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
99
<reg32 offset="0x00004" name="REVISION_ID1"/>
1010
<reg32 offset="0x00008" name="REVISION_ID2"/>
1111
<reg32 offset="0x0000c" name="REVISION_ID3"/>
12-
<reg32 offset="0x00010" name="CLK_CFG0"/>
13-
<reg32 offset="0x00014" name="CLK_CFG1"/>
12+
<reg32 offset="0x00010" name="CLK_CFG0">
13+
<bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>
14+
<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
15+
</reg32>
16+
<reg32 offset="0x00014" name="CLK_CFG1">
17+
<bitfield name="CLK_EN" pos="5" type="boolean"/>
18+
<bitfield name="CLK_EN_SEL" pos="4" type="boolean"/>
19+
<bitfield name="BITCLK_SEL" low="2" high="3" type="uint"/>
20+
</reg32>
1421
<reg32 offset="0x00018" name="GLBL_CTRL"/>
1522
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
1623
<reg32 offset="0x00020" name="VREG_CTRL_0"/>

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