Skip to content

Commit 2574243

Browse files
RRozakrw1nkler
authored andcommitted
modules/zstd: Add RawLiteralsDecoder
Internal-tag: [#56124] Signed-off-by: Ryszard Rozak <[email protected]>
1 parent ccc946e commit 2574243

File tree

2 files changed

+152
-0
lines changed

2 files changed

+152
-0
lines changed

xls/modules/zstd/BUILD

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1008,3 +1008,76 @@ place_and_route(
10081008
synthesized_rtl = ":rle_literals_dec_synth_asap7",
10091009
target_die_utilization_percentage = "10",
10101010
)
1011+
1012+
xls_dslx_library(
1013+
name = "raw_literals_dec_dslx",
1014+
srcs = ["raw_literals_dec.x"],
1015+
deps = [
1016+
":common_dslx",
1017+
],
1018+
)
1019+
1020+
xls_dslx_test(
1021+
name = "raw_literals_dec_dslx_test",
1022+
library = ":raw_literals_dec_dslx",
1023+
)
1024+
1025+
xls_dslx_verilog(
1026+
name = "raw_literals_dec_verilog",
1027+
codegen_args = {
1028+
"module_name": "RawLiteralsDecoder",
1029+
"delay_model": "asap7",
1030+
"pipeline_stages": "1",
1031+
"reset": "rst",
1032+
"use_system_verilog": "false",
1033+
},
1034+
dslx_top = "RawLiteralsDecoder",
1035+
library = ":raw_literals_dec_dslx",
1036+
verilog_file = "raw_literals_dec.v",
1037+
)
1038+
1039+
xls_benchmark_ir(
1040+
name = "raw_literals_dec_opt_ir_benchmark",
1041+
src = ":raw_literals_dec_verilog.opt.ir",
1042+
benchmark_ir_args = {
1043+
"pipeline_stages": "10",
1044+
"delay_model": "asap7",
1045+
},
1046+
)
1047+
1048+
xls_benchmark_verilog(
1049+
name = "raw_literals_dec_verilog_benchmark",
1050+
verilog_target = "raw_literals_dec_verilog",
1051+
)
1052+
1053+
verilog_library(
1054+
name = "raw_literals_dec_lib",
1055+
srcs = [
1056+
":raw_literals_dec.v",
1057+
],
1058+
)
1059+
1060+
synthesize_rtl(
1061+
name = "raw_literals_dec_asap7",
1062+
standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
1063+
top_module = "RawLiteralsDecoder",
1064+
deps = [
1065+
":raw_literals_dec_lib",
1066+
],
1067+
)
1068+
1069+
benchmark_synth(
1070+
name = "raw_literals_dec_benchmark_synth",
1071+
synth_target = ":raw_literals_dec_asap7",
1072+
)
1073+
1074+
place_and_route(
1075+
name = "raw_literals_dec_place_and_route",
1076+
clock_period = "750",
1077+
core_padding_microns = 2,
1078+
min_pin_distance = "0.09",
1079+
placement_density = "0.30",
1080+
stop_after_step = "global_routing",
1081+
synthesized_rtl = ":raw_literals_dec_asap7",
1082+
target_die_utilization_percentage = "10",
1083+
)

xls/modules/zstd/raw_literals_dec.x

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
// Copyright 2024 The XLS Authors
2+
//
3+
// Licensed under the Apache License, Version 2.0 (the "License");
4+
// you may not use this file except in compliance with the License.
5+
// You may obtain a copy of the License at
6+
//
7+
// http://www.apache.org/licenses/LICENSE-2.0
8+
//
9+
// Unless required by applicable law or agreed to in writing, software
10+
// distributed under the License is distributed on an "AS IS" BASIS,
11+
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+
// See the License for the specific language governing permissions and
13+
// limitations under the License.
14+
15+
// The proc should just pass incoming data as literals to LiteralsBuffer.
16+
// Packets of 0 length are not passed further and a warning is log instead.
17+
18+
import xls.modules.zstd.common;
19+
20+
type LiteralsData = common::LiteralsData;
21+
type LitData = common::LitData;
22+
type LitLength = common::LitLength;
23+
24+
proc RawLiteralsDecoder {
25+
dispatcher_r: chan<LiteralsData> in;
26+
buffer_s: chan<LiteralsData> out;
27+
28+
config(dispatcher_r: chan<LiteralsData> in, buffer_s: chan<LiteralsData> out) {
29+
(dispatcher_r, buffer_s)
30+
}
31+
32+
init { }
33+
34+
next(tok: token, state: ()) {
35+
let (tok, resp) = recv(tok, dispatcher_r);
36+
let do_send = if resp.length == LitLength:0 {
37+
trace_fmt!("[WARNING] Packet of 0 length received by RawLiteralsDecoder");
38+
false
39+
} else {
40+
true
41+
};
42+
let tok = send_if(tok, buffer_s, do_send, resp);
43+
}
44+
}
45+
46+
#[test_proc]
47+
proc RawLiteralsDecoderTest {
48+
terminator: chan<bool> out;
49+
dispatcher_s: chan<LiteralsData> out;
50+
buffer_r: chan<LiteralsData> in;
51+
52+
config(terminator: chan<bool> out) {
53+
let (dispatcher_s, dispatcher_r) = chan<LiteralsData>("dispatcher");
54+
let (buffer_s, buffer_r) = chan<LiteralsData>("buffer");
55+
56+
spawn RawLiteralsDecoder(dispatcher_r, buffer_s);
57+
58+
(terminator, dispatcher_s, buffer_r)
59+
}
60+
61+
init { }
62+
63+
next(tok: token, state: ()) {
64+
let data = LiteralsData { data: LitData:0x11_22_33_44_55_66, length: LitLength:6, last: true };
65+
let tok = send(tok, dispatcher_s, data);
66+
let (tok, resp) = recv(tok, buffer_r);
67+
assert_eq(resp, data);
68+
69+
let empty_data = LiteralsData { data: LitData:0, length: LitLength:0, last: true };
70+
let tok = send(tok, dispatcher_s, empty_data);
71+
72+
// Resend the first packet to verify that the empty packet is dropped correctly.
73+
let tok = send(tok, dispatcher_s, data);
74+
let (tok, resp) = recv(tok, buffer_r);
75+
assert_eq(resp, data);
76+
77+
let tok = send(tok, terminator, true);
78+
}
79+
}

0 commit comments

Comments
 (0)