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DSLX DMA: Implement FIFO and CSR
Internal-tag: [#52450] Signed-off-by: Michal Czyz <[email protected]>
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‎xls/examples/ram.x

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@@ -657,7 +657,7 @@ proc RamModel2RW<DATA_WIDTH:u32, SIZE:u32, WORD_PARTITION_SIZE:u32={u32:0},
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state
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};
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let state = if valid1 && request1.we {
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update(state, request0.addr, request0.data)
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update(state, request1.addr, request1.data)
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} else {
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state
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};
@@ -681,6 +681,9 @@ proc RamModel2RW<DATA_WIDTH:u32, SIZE:u32, WORD_PARTITION_SIZE:u32={u32:0},
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let resp1_tok = send_if(tok1, resp_chan1, valid1 && request1.re, response1);
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let wr_comp0_tok = send_if(tok0, wr_comp_chan0, valid0 && request0.we, ());
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let wr_comp1_tok = send_if(tok1, wr_comp_chan1, valid1 && request1.we, ());
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trace_fmt!("RAM State = {}", state);
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// trace_fmt!("RAM req0 = {}", request0);
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// trace_fmt!("RAM req1 = {}", request1);
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state
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}
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}

‎xls/modules/axi4/dma/BUILD

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@@ -0,0 +1,213 @@
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# Copyright 2023 The XLS Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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load(
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"//xls/build_rules:xls_build_defs.bzl",
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"xls_benchmark_ir",
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"xls_dslx_ir",
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"xls_dslx_library",
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"xls_dslx_test",
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"xls_ir_opt_ir",
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"xls_ir_verilog",
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)
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package(
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default_applicable_licenses = ["//:license"],
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default_visibility = ["//xls:xls_users"],
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licenses = ["notice"],
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)
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# Common
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xls_dslx_library(
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name = 'dma_common',
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srcs = [
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'config.x',
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'axi_pkg.x',
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]
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)
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xls_dslx_test(
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name = "test_common",
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library = "dma_common",
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)
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# CSR
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xls_dslx_library(
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name = 'csr',
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srcs = [
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'csr.x'
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],
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deps = [
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':dma_common',
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]
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)
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xls_dslx_test(
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name = "test_csr",
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library = "csr",
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)
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xls_dslx_ir(
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name = "ir_csr_8_32_14",
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dslx_top = "csr_8_32_14",
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ir_file = "csr_8_32_14.ir",
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library = "csr",
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)
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xls_ir_opt_ir(
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name = "opt_ir_csr_8_32_14",
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src = "csr_8_32_14.ir",
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top = "__csr__csr_8_32_14__CSR_0__8_32_14_next"
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)
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xls_ir_verilog(
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name = "verilog_csr_8_32_14",
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src = ":opt_ir_csr_8_32_14.opt.ir",
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codegen_args = {
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"module_name": "csr_8_32_14",
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"delay_model": "unit",
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"pipeline_stages": "2",
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"reset": "rst",
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"use_system_verilog": "false",
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},
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verilog_file = "csr_8_32_14.v",
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)
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# AXI CSR
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xls_dslx_library(
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name = 'axi_csr',
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srcs = [
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'axi_csr.x'
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],
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deps = [
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':dma_common',
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':csr'
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]
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)
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xls_dslx_test(
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name = "test_axi_csr",
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library = "axi_csr",
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)
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xls_dslx_ir(
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name = "axi_csr_8_32_14_ir",
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dslx_top = "axi_csr_8_32_14",
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ir_file = "axi_csr_8_32_14.ir",
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library = "axi_csr",
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)
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xls_ir_opt_ir(
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name = "axi_csr_8_32_14_opt_ir",
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src = "axi_csr_8_32_14.ir",
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top = "__axi_csr__axi_csr_8_32_14__axi_csr_0__8_32_4_14_4_next"
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)
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xls_ir_verilog(
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name = "axi_csr_verilog",
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src = ":axi_csr_8_32_14_opt_ir.opt.ir",
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codegen_args = {
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"module_name": "axi_csr",
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"delay_model": "unit",
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"pipeline_stages": "4",
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"reset": "rst",
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"use_system_verilog": "false",
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},
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verilog_file = "axi_csr.v",
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)
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# FIFO
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xls_dslx_library(
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name = 'fifo',
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srcs = [
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'fifo.x'
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],
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deps = [
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':dma_common',
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'//xls/examples:ram_dslx'
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]
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)
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xls_dslx_test(
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name = "test_fifo",
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library = "fifo",
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)
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xls_dslx_ir(
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name = "fifo_ir",
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dslx_top = "fifo_synth",
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ir_file = "fifo_ir.ir",
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library = "fifo",
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)
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xls_ir_opt_ir(
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name = "fifo_ir_opt",
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src = "fifo_ir.ir",
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# FIXME: Top level is not correctly generated in verilog
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top = "__xls_examples_ram__fifo_synth__FIFO__FifoRAM__RamModel2RW_0__4_8_0_0_16_0_next"
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)
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xls_ir_verilog(
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name = "fifo_verilog",
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src = ":fifo_ir_opt.opt.ir",
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codegen_args = {
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"module_name": "fifo",
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"delay_model": "unit",
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"pipeline_stages": "3",
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"worst_case_throughput": "2",
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"reset": "rst",
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"use_system_verilog": "false",
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# TODO: setup configuration for RAM macro generation
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# https://google.github.io/xls/codegen_options/#rams-experimental
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# https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/xls/codegen/ram_configuration.h#L99
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# https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/docs_src/tutorials/xlscc_memory.md?plain=1#L140
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},
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verilog_file = "fifo.v",
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)
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# LibA
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xls_dslx_library(
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name = 'libA',
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srcs = [
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'libA.x'
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]
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)
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xls_dslx_library(
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name = 'libB',
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srcs = [
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'libB.x'
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],
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deps = [
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'libA'
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]
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)
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xls_dslx_ir(
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name = "libB_ir",
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dslx_top = "procWrapperA",
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ir_file = "procWrapperA.ir",
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library = "libB",
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)
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xls_dslx_test(
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name = "test_libA",
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library = "libA",
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)
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xls_dslx_test(
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name = "test_libB",
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library = "libB",
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)

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