diff --git a/xls/codegen/block_generator.cc b/xls/codegen/block_generator.cc
index d990187cfa..a98cc502c2 100644
--- a/xls/codegen/block_generator.cc
+++ b/xls/codegen/block_generator.cc
@@ -527,13 +527,63 @@ class BlockGenerator {
     return false;
   }
 
+  // Returns whether the given operand appears multiple times in the emitted
+  // verilog expression/statement(s) for the given node.
+  bool OperandAppearsMultipleTimesInExpression(Node* n, int64_t operand_no) {
+    switch (n->op()) {
+      case Op::kArraySlice:
+      case Op::kArrayUpdate:
+      case Op::kArrayConcat:
+        return true;
+      // Select operations have multiple comparisons to the selector. Priority
+      // select is emitted as a separate function and doesn't have this
+      // property.
+      case Op::kSel:
+        return n->As<Select>()->cases().size() > 2 &&
+               operand_no == Select::kSelectorOperand;
+      case Op::kOneHotSel:
+        return operand_no == OneHotSelect::kSelectorOperand;
+      case Op::kEncode:
+      case Op::kReverse:
+        return true;
+      case Op::kEq:
+      case Op::kNe:
+        return !n->GetType()->IsBits();
+      case Op::kAssert:
+        return true;
+      default:
+        return false;
+    }
+  }
+
+  // Returns whether the expression for the given node will be duplicated if
+  // inlined into its uses.
+  bool InlinedExpressionWillBeDuplicated(Node* n) {
+    if (n->users().size() == 0) {
+      return false;
+    } else if (n->users().size() > 1) {
+      return true;
+    }
+    Node* user = n->users().front();
+    std::optional<int64_t> operand_no;
+    for (int64_t i = 0; i < user->operand_count(); i++) {
+      if (user->operand(i) == n) {
+        if (operand_no.has_value()) {
+          return true;
+        }
+        operand_no = i;
+      }
+    }
+    return OperandAppearsMultipleTimesInExpression(user, operand_no.value());
+  }
+
   // Returns true if the given node should be emitted as an assignment
   // for readability purposes. This is a soft constraint / suggestion.
   bool ShouldEmitAsAssignment(Node* const n, int64_t inline_depth) {
-    return (
-        n->HasAssignedName() ||
-        (n->users().size() > 1 && !ShouldInlineExpressionIntoMultipleUses(n)) ||
-        inline_depth > options_.max_inline_depth());
+    return (n->HasAssignedName() ||
+            (InlinedExpressionWillBeDuplicated(n) &&
+             !ShouldInlineExpressionIntoMultipleUses(n)) ||
+            inline_depth > options_.max_inline_depth());
   }
 
   // Name of the node if it gets emitted as a separate assignment.
@@ -906,8 +956,8 @@ class BlockGenerator {
   // Emit each instantiation in the block into the separate instantiation module
   // section.
   absl::Status EmitInstantiations() {
-    // Since instantiations are emitted at the end, and not the pipeline stages
-    // they are in, separate with headline to reduce confusion.
+    // Since instantiations are emitted at the end, and not the pipeline
+    // stages they are in, separate with headline to reduce confusion.
     if (!block_->GetInstantiations().empty()) {
       mb_.declaration_section()->Add<BlankLine>(SourceInfo());
       mb_.instantiation_section()->Add<Comment>(SourceInfo(),
diff --git a/xls/codegen/module_builder.cc b/xls/codegen/module_builder.cc
index 504492751c..679bd0c8ff 100644
--- a/xls/codegen/module_builder.cc
+++ b/xls/codegen/module_builder.cc
@@ -645,186 +645,103 @@ absl::StatusOr<Expression*> ModuleBuilder::EmitAsInlineExpression(
   return NodeToExpression(node, inputs, file_, options_);
 }
 
-absl::Status ModuleBuilder::EmitArrayCopyAndUpdateViaGenerate1D(
+absl::Status ModuleBuilder::EmitArrayCopyAndUpdateViaGenerate(
     std::string_view op_name, IndexableExpression* lhs,
-    IndexableExpression* rhs, Expression* update_value, IndexType index_type,
-    Type* xls_type) {
-  ArrayType* array_type = xls_type->AsArrayOrDie();
-
-  // Create names derived from the unique operation name to ensure the derived
-  // names are unique. We namespace via double underscore in an attempt to
-  // reserve the suffixes and avoid collisions.
-  std::string genvar_name =
-      SanitizeAndUniquifyName(absl::StrCat(op_name, "__index"));
-  std::string generate_loop_name =
-      SanitizeAndUniquifyName(absl::StrCat(op_name, "__gen"));
-
-  XLS_ASSIGN_OR_RETURN(auto* genvar,
-                       module_->AddGenvar(genvar_name, SourceInfo()));
-
-  GenerateLoop* generate_loop = module_->Add<GenerateLoop>(
-      SourceInfo(), genvar, file_->PlainLiteral(0, SourceInfo()),
-      file_->PlainLiteral(array_type->size(), SourceInfo()),
-      generate_loop_name);
-
-  // In the body there is a conditional where we choose to either assign the rhs
-  // index directly or the updated value.
-  Expression* index_is_match =
-      file_->Equals(index_type.expression, genvar, SourceInfo());
-  Expression* rhs_at_index = file_->Index(rhs, genvar, SourceInfo());
-  generate_loop->AddBodyNode(file_->Make<ContinuousAssignment>(
-      SourceInfo(), file_->Make<Index>(SourceInfo(), lhs, genvar),
-      file_->Ternary(index_is_match, update_value, rhs_at_index,
-                     SourceInfo())));
-  return absl::OkStatus();
-}
-
-// Emits a copy and update of an array as a sequence of assignments.
-// Specifically, 'rhs' is copied to 'lhs' with the element at the indices
-// 'indices' replaced with 'update_value'.  Examples of emitted verilog:
-//
-//   // lhs: bits[32][3] = array_update(rhs, value, indices=[1]):
-//   assign lhs[0] = rhs[0];
-//   assign lhs[1] = value;
-//   assign lhs[2] = rhs[1];
-//
-//   // lhs: bits[32][3] = array_update(rhs, value, indices=[x]):
-//   assign lhs[0] = x == 0 ? value : rhs[0];
-//   assign lhs[1] = x == 1 ? value : rhs[1];
-//   assign lhs[2] = x == 2 ? value : rhs[2];
-//
-//   // lhs: bits[32][3][2] = array_update(rhs, value, indices=[x, 1]):
-//   assign lhs[0][0] = rhs[0][0];
-//   assign lhs[0][1] = x == 0 ? value : rhs[0][1];
-//   assign lhs[0][2] = rhs[0][2];
-//   assign lhs[1][0] = rhs[1][0];
-//   assign lhs[1][1] = x == 1 ? value : rhs[0][1];
-//   assign lhs[1][2] = rhs[0][2];
-//
-//   // lhs: bits[32][3][2] = array_update(rhs, value, indices=[x, y]):
-//   assign lhs[0][0] = (x == 0 && y == 0) ? value : rhs[0][0];
-//   assign lhs[0][1] = (x == 0 && y == 1) ? value : rhs[0][1];
-//   assign lhs[0][2] = (x == 0 && y == 2) ? value : rhs[0][2];
-//   assign lhs[1][0] = (x == 1 && y == 0) ? value : rhs[1][0];
-//   assign lhs[1][1] = (x == 1 && y == 1) ? value : rhs[1][1];
-//   assign lhs[1][2] = (x == 1 && y == 2) ? value : rhs[1][2];
-//
-//   // lhs: bits[32][3][2] = array_update(rhs, value, indices=[x]):
-//   assign lhs[0][0] = x == 0 ? value[0] : rhs[0][0];
-//   assign lhs[0][1] = x == 0 ? value[1] : rhs[0][1];
-//   assign lhs[0][2] = x == 0 ? value[2] : rhs[0][2];
-//   assign lhs[1][0] = x == 1 ? value[0] : rhs[1][0];
-//   assign lhs[1][1] = x == 1 ? value[1] : rhs[1][1];
-//   assign lhs[1][2] = x == 1 ? value[2] : rhs[1][2];
-//
-// EmitArrayCopyAndUpdate recursively constructs the assignments. 'index_match'
-// is the index match expression (or explicit true/false value) used in ternary
-// expression to select element(s) from the update value or the rhs.
-absl::Status ModuleBuilder::EmitArrayCopyAndUpdate(
-    IndexableExpression* lhs, IndexableExpression* rhs,
-    Expression* update_value,
-    absl::Span<const ModuleBuilder::IndexType> indices, IndexMatch index_match,
-    Type* xls_type) {
-  auto is_statically_true = [](const IndexMatch& im) {
-    return std::holds_alternative<bool>(im) && std::get<bool>(im);
-  };
-  auto is_statically_false = [](const IndexMatch& im) {
-    return std::holds_alternative<bool>(im) && !std::get<bool>(im);
-  };
-  auto combine_index_matches = [&](const IndexMatch& a,
-                                   const IndexMatch& b) -> IndexMatch {
-    if (is_statically_false(a) || is_statically_false(b)) {
-      return false;
+    IndexableExpression* rhs, Expression* update_value,
+    absl::Span<const ModuleBuilder::IndexType> indices, Type* xls_type) {
+  std::vector<GenerateLoopIterationSpec> iteration_specs;
+  // Genvars for the index space of `indices`.
+  std::vector<LogicRef*> index_genvars;
+  // Genvars for the index space of the updated value. This will be non-empty
+  // only if the update value is an array.
+  std::vector<LogicRef*> update_genvars;
+
+  // Create the iteration space for `indices`.
+  Type* iter_type = xls_type;
+  for (int64_t dim_index = 0; dim_index < indices.size(); ++dim_index) {
+    ArrayType* current_array = iter_type->AsArrayOrDie();
+    int64_t dim_size = current_array->size();
+
+    std::string genvar_name =
+        SanitizeAndUniquifyName(absl::StrCat(op_name, "__index_", dim_index));
+    XLS_ASSIGN_OR_RETURN(LogicRef * genvar,
+                         module_->AddGenvar(genvar_name, SourceInfo()));
+    index_genvars.push_back(genvar);
+    iteration_specs.push_back(GenerateLoopIterationSpec{
+        genvar, file_->PlainLiteral(0, SourceInfo()),
+        file_->PlainLiteral(dim_size, SourceInfo()),
+        std::optional<std::string>(SanitizeAndUniquifyName(
+            absl::StrCat(op_name, "__gen_", dim_index)))});
+
+    iter_type = current_array->element_type();
+  }
+
+  // Create the iteration space for the update value.
+  Type* update_leaf_type = iter_type;
+  int64_t update_dim = 0;
+  while (update_leaf_type->IsArray()) {
+    ArrayType* current_array = update_leaf_type->AsArrayOrDie();
+    int64_t dim_size = current_array->size();
+
+    std::string genvar_name =
+        SanitizeAndUniquifyName(absl::StrCat(op_name, "__update_", update_dim));
+    XLS_ASSIGN_OR_RETURN(LogicRef * genvar,
+                         module_->AddGenvar(genvar_name, SourceInfo()));
+    update_genvars.push_back(genvar);
+    iteration_specs.push_back(GenerateLoopIterationSpec{
+        genvar, file_->PlainLiteral(0, SourceInfo()),
+        file_->PlainLiteral(dim_size, SourceInfo()),
+        std::optional<std::string>(SanitizeAndUniquifyName(
+            absl::StrCat(op_name, "__gen_up_", update_dim)))});
+
+    update_leaf_type = current_array->element_type();
+    ++update_dim;
+  }
+
+  GenerateLoop* generate_loop =
+      module_->Add<GenerateLoop>(SourceInfo(), iteration_specs);
+
+  // Build the index match condition.
+  Expression* indices_match = nullptr;
+  for (int64_t i = 0; i < indices.size(); ++i) {
+    Expression* eq =
+        file_->Equals(indices[i].expression, index_genvars[i], SourceInfo());
+    indices_match = (indices_match == nullptr)
+                        ? eq
+                        : file_->LogicalAnd(indices_match, eq, SourceInfo());
+  }
+
+  // Build lhs and rhs indexed by all loop genvars (index + update dims).
+  IndexableExpression* lhs_indexed = lhs;
+  IndexableExpression* rhs_indexed = rhs;
+  for (LogicRef* v : index_genvars) {
+    lhs_indexed = file_->Index(lhs_indexed, v, SourceInfo());
+    rhs_indexed = file_->Index(rhs_indexed, v, SourceInfo());
+  }
+  for (LogicRef* v : update_genvars) {
+    lhs_indexed = file_->Index(lhs_indexed, v, SourceInfo());
+    rhs_indexed = file_->Index(rhs_indexed, v, SourceInfo());
+  }
+
+  // Build update_value indexed by its own loop genvars.
+  Expression* update_indexed = update_value;
+  if (!update_genvars.empty()) {
+    IndexableExpression* update_idx =
+        update_value->AsIndexableExpressionOrDie();
+    for (LogicRef* v : update_genvars) {
+      update_idx = file_->Index(update_idx, v, SourceInfo());
     }
-    if (is_statically_true(a)) {
-      return b;
-    }
-    if (is_statically_true(b)) {
-      return a;
-    }
-    return file_->LogicalAnd(std::get<Expression*>(a), std::get<Expression*>(b),
-                             SourceInfo());
-  };
-
-  if (indices.empty()) {
-    if (is_statically_true(index_match)) {
-      // Indices definitely *do* match the subarray/element being replaced with
-      // update value. Assign from update value exclusively. E.g.:
-      //   assign lhs[i][j] = update_value[j]
-      return AddAssignment(
-          /*xls_type=*/xls_type,
-          /*lhs=*/lhs,
-          /*rhs=*/update_value,
-          /*add_assignment=*/
-          [&](Expression* lhs, Expression* rhs) {
-            assignment_section()->Add<ContinuousAssignment>(SourceInfo(), lhs,
-                                                            rhs);
-          });
-    }
-    if (is_statically_false(index_match)) {
-      // Indices definitely do *NOT* match the subarray/element being replaced
-      // with update value. Assign from rhs exclusively. E.g.:
-      //   assign lhs[i][j] = rhs[j]
-      return AddAssignment(
-          /*xls_type=*/xls_type,
-          /*lhs=*/lhs,
-          /*rhs=*/rhs,
-          /*add_assignment=*/
-          [&](Expression* lhs, Expression* rhs) {
-            assignment_section()->Add<ContinuousAssignment>(SourceInfo(), lhs,
-                                                            rhs);
-          });
-    }
-    // Indices may or may not match the subarray/element being replaced with
-    // update value. Use a ternary expression to pick from rhs or update
-    // value. E.g:
-    //   assign lhs[i][j] = (i == idx) ? update_value[j] : rhs[j]
-    auto gen_ternary = [&](absl::Span<Expression* const> inputs) {
-      return file_->Ternary(std::get<Expression*>(index_match), inputs[0],
-                            inputs[1], SourceInfo());
-    };
-
-    // Emit a continuous assignment with a ternary select. The ternary
-    // operation supports array types in SystemVerilog so sv_array_expr is
-    // true.
-    return AddAssignmentToGeneratedExpression(
-        xls_type, lhs, /*inputs=*/{update_value, rhs}, gen_ternary,
-        /*add_assignment=*/
-        [&](Expression* lhs, Expression* rhs) {
-          assignment_section()->Add<ContinuousAssignment>(SourceInfo(), lhs,
-                                                          rhs);
-        },
-        /*sv_array_expr=*/true);
-  }
-
-  // Iterate through array elements and recurse.
-  ArrayType* array_type = xls_type->AsArrayOrDie();
-  IndexType index_type = indices.front();
-  int64_t index_bit_count = index_type.xls_type->bit_count();
-  for (int64_t i = 0; i < array_type->size(); ++i) {
-    // Compute the current index match expression for this index element.
-    IndexMatch current_index_match;
-    if (index_type.expression->IsLiteral()) {
-      // Index element is a literal. The condition is statically known (true or
-      // false).
-      current_index_match = index_type.expression->IsLiteralWithValue(i);
-    } else if (Bits::MinBitCountUnsigned(i) > index_bit_count) {
-      // Index is not wide enough to hold 'i'.
-      current_index_match = false;
-    } else {
-      // Index element is a not literal. The condition is not statically known.
-      current_index_match =
-          file_->Equals(index_type.expression,
-                        file_->Literal(UBits(i, index_bit_count), SourceInfo()),
-                        SourceInfo());
-    }
-    XLS_RETURN_IF_ERROR(EmitArrayCopyAndUpdate(
-        file_->Index(lhs, i, SourceInfo()), file_->Index(rhs, i, SourceInfo()),
-        update_value, indices.subspan(1),
-        combine_index_matches(current_index_match, index_match),
-        array_type->element_type()));
+    update_indexed = update_idx;
   }
 
+  // Emit the assignment inside the generate loop body.
+  Expression* assignment_rhs =
+      indices_match == nullptr ? update_indexed
+                               : file_->Ternary(indices_match, update_indexed,
+                                                rhs_indexed, SourceInfo());
+  generate_loop->AddStatement(file_->Make<ContinuousAssignment>(
+      SourceInfo(), lhs_indexed, assignment_rhs));
+
   return absl::OkStatus();
 }
 
@@ -965,26 +882,13 @@ absl::StatusOr<LogicRef*> ModuleBuilder::EmitAsAssignment(
               IndexType{inputs[i], node->operand(i)->GetType()->AsBitsOrDie()});
         }
 
-        // We use a generate loop in the simple case where the array is 1D and
-        // the element type is bits.
-        if (index_types.size() == 1 &&
-            node->GetType()->AsArrayOrDie()->element_type()->IsBits()) {
-          XLS_RETURN_IF_ERROR(EmitArrayCopyAndUpdateViaGenerate1D(
-              /*op_name=*/node->GetName(),
-              /*lhs=*/ref,
-              /*rhs=*/inputs[0]->AsIndexableExpressionOrDie(),
-              /*update_value=*/inputs[1],
-              /*index_type=*/index_types[0],
-              /*xls_type=*/array_type));
-        } else {
-          XLS_RETURN_IF_ERROR(EmitArrayCopyAndUpdate(
-              /*lhs=*/ref,
-              /*rhs=*/inputs[0]->AsIndexableExpressionOrDie(),
-              /*update_value=*/inputs[1],
-              /*indices=*/index_types,
-              /*index_match=*/true,
-              /*xls_type=*/array_type));
-        }
+        XLS_RETURN_IF_ERROR(EmitArrayCopyAndUpdateViaGenerate(
+            /*op_name=*/node->GetName(),
+            /*lhs=*/ref,
+            /*rhs=*/inputs[0]->AsIndexableExpressionOrDie(),
+            /*update_value=*/inputs[1],
+            /*indices=*/index_types,
+            /*xls_type=*/array_type));
         break;
       }
       case Op::kArrayConcat: {
diff --git a/xls/codegen/module_builder.h b/xls/codegen/module_builder.h
index 76eaa04d4d..9c6b4921b0 100644
--- a/xls/codegen/module_builder.h
+++ b/xls/codegen/module_builder.h
@@ -298,20 +298,13 @@ class ModuleBuilder {
     Expression* expression;
     BitsType* xls_type;
   };
-  absl::Status EmitArrayCopyAndUpdate(IndexableExpression* lhs,
-                                      IndexableExpression* rhs,
-                                      Expression* update_value,
-                                      absl::Span<const IndexType> indices,
-                                      IndexMatch index_match, Type* xls_type);
 
   // Emits a copy-and-update of an array using a generate loop, which avoids
   // unnecessary bloat in the output code size.
-  absl::Status EmitArrayCopyAndUpdateViaGenerate1D(std::string_view op_name,
-                                                   IndexableExpression* lhs,
-                                                   IndexableExpression* rhs,
-                                                   Expression* update_value,
-                                                   IndexType index_type,
-                                                   Type* xls_type);
+  absl::Status EmitArrayCopyAndUpdateViaGenerate(
+      std::string_view op_name, IndexableExpression* lhs,
+      IndexableExpression* rhs, Expression* update_value,
+      absl::Span<const ModuleBuilder::IndexType> indices, Type* xls_type);
 
   // Assigns the arbitrarily-typed Value 'value' to 'lhs'. Depending upon the
   // type this may require multiple assignment statements. The function
diff --git a/xls/codegen/module_builder_test.cc b/xls/codegen/module_builder_test.cc
index 1d3a124280..4437553b05 100644
--- a/xls/codegen/module_builder_test.cc
+++ b/xls/codegen/module_builder_test.cc
@@ -17,11 +17,11 @@
 #include <cstdint>
 #include <vector>
 
-#include "gmock/gmock.h"
-#include "gtest/gtest.h"
 #include "absl/status/status.h"
 #include "absl/status/status_matchers.h"
 #include "absl/types/span.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
 #include "xls/codegen/module_signature.pb.h"
 #include "xls/codegen/vast/vast.h"
 #include "xls/common/status/matchers.h"
@@ -853,6 +853,85 @@ TEST_P(ModuleBuilderTest, ArrayUpdate1D) {
                                  file.Emit());
 }
 
+TEST_P(ModuleBuilderTest, ArrayUpdate4D) {
+  VerilogFile file = NewVerilogFile();
+  Package package(TestBaseName());
+  FunctionBuilder fb(TestBaseName(), &package);
+  // 4D array of shape [4][3][2][5] with element type u32
+  Type* u32 = package.GetBitsType(32);
+  Type* d3 = package.GetArrayType(5, u32);
+  Type* d2 = package.GetArrayType(2, d3);
+  Type* d1 = package.GetArrayType(3, d2);
+  ArrayType* array_type = package.GetArrayType(4, d1);
+
+  // Parameters: 4D array, two indices (for the first two dimensions), and a 2D
+  // value
+  BValue array = fb.Param("array", array_type);
+  BValue idx0 = fb.Param("idx0", package.GetBitsType(2));  // for dim size 4
+  BValue idx1 = fb.Param("idx1", package.GetBitsType(2));  // for dim size 3
+  BValue value = fb.Param("value", d2);                    // 2D subarray [2][5]
+
+  // Update slice array[idx0][idx1][*][*] with 2D value
+  BValue updated_array = fb.ArrayUpdate(array, value, /*indices=*/{idx0, idx1});
+  XLS_ASSERT_OK(fb.Build());
+
+  ModuleBuilder mb(TestBaseName(), &file, codegen_options());
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * array_ref,
+                           mb.AddInputPort("array", array_type));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * idx0_ref,
+                           mb.AddInputPort("idx0", package.GetBitsType(2)));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * idx1_ref,
+                           mb.AddInputPort("idx1", package.GetBitsType(2)));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * value_ref, mb.AddInputPort("value", d2));
+  // Emit with inputs ordered to match ArrayUpdate operands: array, value,
+  // indices...
+  XLS_ASSERT_OK(mb.EmitAsAssignment("updated_array", updated_array.node(),
+                                    {array_ref, value_ref, idx0_ref, idx1_ref})
+                    .status());
+
+  ExpectVerilogEqualToGoldenFile(GoldenFilePath(kTestName, kTestdataPath),
+                                 file.Emit());
+}
+
+TEST_P(ModuleBuilderTest, ArrayUpdateWithTupleWithNestedArray) {
+  VerilogFile file = NewVerilogFile();
+  Package package(TestBaseName());
+  FunctionBuilder fb(TestBaseName(), &package);
+  // Make a 1D array of tuples. Each tuple has:
+  //  - a 1D array of 4 elements of u8, and
+  //  - a single u16 scalar.
+  Type* u8 = package.GetBitsType(8);
+  Type* u16 = package.GetBitsType(16);
+  ArrayType* inner_array_type = package.GetArrayType(4, u8);
+  TupleType* tuple_type = package.GetTupleType({inner_array_type, u16});
+  ArrayType* array_type = package.GetArrayType(3, tuple_type);
+
+  // Parameters: the array, an index into the 1D array, and a tuple value to
+  // replace the array element at that index.
+  BValue array = fb.Param("array", array_type);
+  BValue idx = fb.Param("idx", package.GetBitsType(2));  // for dim size 3
+  BValue value = fb.Param("value", tuple_type);
+
+  // Update array[idx] with the tuple value.
+  BValue updated_array = fb.ArrayUpdate(array, value, /*indices=*/{idx});
+  XLS_ASSERT_OK(fb.Build());
+
+  ModuleBuilder mb(TestBaseName(), &file, codegen_options());
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * array_ref,
+                           mb.AddInputPort("array", array_type));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * idx_ref,
+                           mb.AddInputPort("idx", package.GetBitsType(2)));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * value_ref,
+                           mb.AddInputPort("value", tuple_type));
+  // Emit with inputs ordered to match ArrayUpdate operands: array, value, idx.
+  XLS_ASSERT_OK(mb.EmitAsAssignment("updated_array", updated_array.node(),
+                                    {array_ref, value_ref, idx_ref})
+                    .status());
+
+  ExpectVerilogEqualToGoldenFile(GoldenFilePath(kTestName, kTestdataPath),
+                                 file.Emit());
+}
+
 TEST_P(ModuleBuilderTest, NameCollisionsOnPorts) {
   VerilogFile file = NewVerilogFile();
   Package p(TestBaseName());
diff --git a/xls/codegen/node_expressions.cc b/xls/codegen/node_expressions.cc
index b83f6765cd..905413644a 100644
--- a/xls/codegen/node_expressions.cc
+++ b/xls/codegen/node_expressions.cc
@@ -730,7 +730,8 @@ absl::StatusOr<Expression*> NodeToExpression(
 
 bool ShouldInlineExpressionIntoMultipleUses(Node* node) {
   return node->Is<BitSlice>() || node->op() == Op::kNot ||
-         node->op() == Op::kNeg;
+         node->op() == Op::kNeg ||
+         (node->Is<xls::Literal>() && node->GetType()->IsBits());
 }
 
 absl::StatusOr<IndexableExpression*> ArrayIndexExpression(
diff --git a/xls/codegen/testdata/assertions_comb_multiple_ifdef_guards.svtxt b/xls/codegen/testdata/assertions_comb_multiple_ifdef_guards.svtxt
index 88c36ba212..78c8340950 100644
--- a/xls/codegen/testdata/assertions_comb_multiple_ifdef_guards.svtxt
+++ b/xls/codegen/testdata/assertions_comb_multiple_ifdef_guards.svtxt
@@ -4,18 +4,16 @@ module assertions_top(
 );
   wire [30:0] add_195;
   wire ult_202;
-  wire [31:0] literal_200;
   wire [30:0] add_209;
   wire ult_206;
   wire nand_211;
   wire nand_212;
   assign add_195 = y[31:1] + 31'h7fff_fffb;
   assign ult_202 = y < 32'h0000_0014;
-  assign literal_200 = 32'h0000_0004;
   assign add_209 = y[31:1] + 31'h0000_000f;
   assign ult_206 = y < 32'h0000_000a;
-  assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > literal_200);
-  assign nand_212 = ~(ult_206 & y > literal_200);
+  assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > 32'h0000_0004);
+  assign nand_212 = ~(ult_206 & y > 32'h0000_0004);
   assign out = ult_206 ? {add_209, y[0]} : y & {32{ult_202}};
   `ifdef ASSERT_ON
   `ifndef SYNTHESIS
diff --git a/xls/codegen/testdata/assertions_comb_no_ifdef_guards.svtxt b/xls/codegen/testdata/assertions_comb_no_ifdef_guards.svtxt
index 723e8b6795..b28a8872a7 100644
--- a/xls/codegen/testdata/assertions_comb_no_ifdef_guards.svtxt
+++ b/xls/codegen/testdata/assertions_comb_no_ifdef_guards.svtxt
@@ -4,18 +4,16 @@ module assertions_top(
 );
   wire [30:0] add_195;
   wire ult_202;
-  wire [31:0] literal_200;
   wire [30:0] add_209;
   wire ult_206;
   wire nand_211;
   wire nand_212;
   assign add_195 = y[31:1] + 31'h7fff_fffb;
   assign ult_202 = y < 32'h0000_0014;
-  assign literal_200 = 32'h0000_0004;
   assign add_209 = y[31:1] + 31'h0000_000f;
   assign ult_206 = y < 32'h0000_000a;
-  assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > literal_200);
-  assign nand_212 = ~(ult_206 & y > literal_200);
+  assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > 32'h0000_0004);
+  assign nand_212 = ~(ult_206 & y > 32'h0000_0004);
   assign out = ult_206 ? {add_209, y[0]} : y & {32{ult_202}};
   y_ge_than_21: assert final ($isunknown(ult_202) || ult_202) else $fatal(0, "Assertion failure via fail! @ xls/examples/assertions/assertions.x:32:14-32:37");
   __assertions__main_0___itok__assertions__main___itok__assertions__main_0___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_211) || nand_211) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
diff --git a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressions.vtxt b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressions.vtxt
index bd3d272141..fc4de36ef1 100644
--- a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressions.vtxt
+++ b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressions.vtxt
@@ -7,9 +7,7 @@ module pipelined_proc(
       bit_slice_update_w10_10b_2b = start >= 10'h00a ? to_update : {8'h00, update_value} << start | ~(10'h003 << start) & to_update;
     end
   endfunction
-  wire [1:0] literal_33;
   wire [9:0] bit_slice_update_52;
-  assign literal_33 = 2'h2;
-  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, literal_33), 10'h001, literal_33), 10'h002, literal_33), 10'h003, literal_33), 10'h004, literal_33), 10'h005, literal_33), 10'h006, literal_33), 10'h007, literal_33), 10'h008, literal_33), 10'h009, literal_33);
+  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, 2'h2), 10'h001, 2'h2), 10'h002, 2'h2), 10'h003, 2'h2), 10'h004, 2'h2), 10'h005, 2'h2), 10'h006, 2'h2), 10'h007, 2'h2), 10'h008, 2'h2), 10'h009, 2'h2);
   assign out = bit_slice_update_52;
 endmodule
diff --git a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithDefaultLimit.vtxt b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithDefaultLimit.vtxt
index 4f168849b7..c2a250a276 100644
--- a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithDefaultLimit.vtxt
+++ b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithDefaultLimit.vtxt
@@ -7,11 +7,9 @@ module pipelined_proc(
       bit_slice_update_w10_10b_2b = start >= 10'h00a ? to_update : {8'h00, update_value} << start | ~(10'h003 << start) & to_update;
     end
   endfunction
-  wire [1:0] literal_33;
   wire [9:0] bit_slice_update_42;
   wire [9:0] bit_slice_update_52;
-  assign literal_33 = 2'h2;
-  assign bit_slice_update_42 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, literal_33), 10'h001, literal_33), 10'h002, literal_33), 10'h003, literal_33), 10'h004, literal_33);
-  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_42, 10'h005, literal_33), 10'h006, literal_33), 10'h007, literal_33), 10'h008, literal_33), 10'h009, literal_33);
+  assign bit_slice_update_42 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, 2'h2), 10'h001, 2'h2), 10'h002, 2'h2), 10'h003, 2'h2), 10'h004, 2'h2);
+  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_42, 10'h005, 2'h2), 10'h006, 2'h2), 10'h007, 2'h2), 10'h008, 2'h2), 10'h009, 2'h2);
   assign out = bit_slice_update_52;
 endmodule
diff --git a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithShallowLimit.vtxt b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithShallowLimit.vtxt
index c2397ce870..7703f72181 100644
--- a/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithShallowLimit.vtxt
+++ b/xls/codegen/testdata/block_generator_test_DeeplyNestedExpressionsWithShallowLimit.vtxt
@@ -7,17 +7,15 @@ module pipelined_proc(
       bit_slice_update_w10_10b_2b = start >= 10'h00a ? to_update : {8'h00, update_value} << start | ~(10'h003 << start) & to_update;
     end
   endfunction
-  wire [1:0] literal_33;
   wire [9:0] bit_slice_update_36;
   wire [9:0] bit_slice_update_40;
   wire [9:0] bit_slice_update_44;
   wire [9:0] bit_slice_update_48;
   wire [9:0] bit_slice_update_52;
-  assign literal_33 = 2'h2;
-  assign bit_slice_update_36 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, literal_33), 10'h001, literal_33);
-  assign bit_slice_update_40 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_36, 10'h002, literal_33), 10'h003, literal_33);
-  assign bit_slice_update_44 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_40, 10'h004, literal_33), 10'h005, literal_33);
-  assign bit_slice_update_48 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_44, 10'h006, literal_33), 10'h007, literal_33);
-  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_48, 10'h008, literal_33), 10'h009, literal_33);
+  assign bit_slice_update_36 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(x, 10'h000, 2'h2), 10'h001, 2'h2);
+  assign bit_slice_update_40 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_36, 10'h002, 2'h2), 10'h003, 2'h2);
+  assign bit_slice_update_44 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_40, 10'h004, 2'h2), 10'h005, 2'h2);
+  assign bit_slice_update_48 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_44, 10'h006, 2'h2), 10'h007, 2'h2);
+  assign bit_slice_update_52 = bit_slice_update_w10_10b_2b(bit_slice_update_w10_10b_2b(bit_slice_update_48, 10'h008, 2'h2), 10'h009, 2'h2);
   assign out = bit_slice_update_52;
 endmodule
diff --git a/xls/codegen/testdata/block_generator_test_InstantiatedBlock.vtxt b/xls/codegen/testdata/block_generator_test_InstantiatedBlock.vtxt
index 73a58d2c8a..39cc25e3ae 100644
--- a/xls/codegen/testdata/block_generator_test_InstantiatedBlock.vtxt
+++ b/xls/codegen/testdata/block_generator_test_InstantiatedBlock.vtxt
@@ -15,18 +15,16 @@ module my_block(
   output wire [31:0] out
 );
   wire [31:0] instantiation_output_12;
-  wire [31:0] literal_7;
   wire [31:0] add_8;
   wire [31:0] sub_10;
 
-  assign literal_7 = 32'h0000_0001;
-  assign add_8 = x + literal_7;
-  assign sub_10 = y - literal_7;
+  assign add_8 = x + 32'h0000_0001;
+  assign sub_10 = y - 32'h0000_0001;
   // ===== Instantiations
   subtractor sub (
     .a(add_8),
     .b(sub_10),
     .result(instantiation_output_12)
   );
-  assign out = literal_7 >= 32'h0000_0020 ? 32'h0000_0000 : instantiation_output_12 << literal_7;
+  assign out = 32'h0000_0001 >= 32'h0000_0020 ? 32'h0000_0000 : instantiation_output_12 << 32'h0000_0001;
 endmodule
diff --git a/xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.vtxt b/xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.vtxt
index ad611a515a..8e311d04f7 100644
--- a/xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.vtxt
+++ b/xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.vtxt
@@ -33,7 +33,6 @@ module running_sum(
   wire p1_stage_valid;
   wire p1_all_active_inputs_valid;
   wire p1_all_active_outputs_ready;
-  wire literal_1096;
   wire p1_enable;
   wire p1_stage_done;
   wire __out_valid_buf;
@@ -76,12 +75,11 @@ module running_sum(
   assign p1_stage_valid = p1_all_active_states_valid & p0_valid;
   assign p1_all_active_inputs_valid = in_valid & loopback_active_valid;
   assign p1_all_active_outputs_ready = 1'h1;
-  assign literal_1096 = 1'h1;
   assign p1_enable = p2_stage_done | p2_not_valid;
   assign p1_stage_done = p1_stage_valid & p1_all_active_inputs_valid & p1_all_active_outputs_ready;
-  assign __out_valid_buf = p2_all_active_inputs_valid & p2_stage_valid & literal_1096;
+  assign __out_valid_buf = p2_all_active_inputs_valid & p2_stage_valid & 1'h1;
   assign __out_data_not_has_been_sent = ~__out_data_has_been_sent_reg;
-  assign __fifo_loopback_push_valid_buf = p2_all_active_inputs_valid & p2_stage_valid & literal_1096;
+  assign __fifo_loopback_push_valid_buf = p2_all_active_inputs_valid & p2_stage_valid & 1'h1;
   assign __fifo_loopback_push_data_not_has_been_sent = ~__fifo_loopback_push_data_has_been_sent_reg;
   assign p1_data_enable = p1_enable & p1_stage_done;
   assign p1_not_valid = ~p0_valid;
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DLiteralIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DLiteralIndex.vtxt
index e1e73cfee7..f4a10b4225 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DLiteralIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DLiteralIndex.vtxt
@@ -11,11 +11,14 @@ module ArrayUpdate2DLiteralIndex(
   assign a_unflattened[1][1] = a[39:32];
   assign a_unflattened[1][2] = a[47:40];
   wire [7:0] array_update_10[0:1][0:2];
-  assign array_update_10[0][0] = a_unflattened[0][0];
-  assign array_update_10[0][1] = a_unflattened[0][1];
-  assign array_update_10[0][2] = value;
-  assign array_update_10[1][0] = a_unflattened[1][0];
-  assign array_update_10[1][1] = a_unflattened[1][1];
-  assign array_update_10[1][2] = a_unflattened[1][2];
   assign out = {{array_update_10[1][2], array_update_10[1][1], array_update_10[1][0]}, {array_update_10[0][2], array_update_10[0][1], array_update_10[0][0]}};
+  genvar array_update_10__index_0;
+  genvar array_update_10__index_1;
+  generate
+    for (array_update_10__index_0 = 0; array_update_10__index_0 < 2; array_update_10__index_0 = array_update_10__index_0 + 1) begin : array_update_10__gen_0
+      for (array_update_10__index_1 = 0; array_update_10__index_1 < 3; array_update_10__index_1 = array_update_10__index_1 + 1) begin : array_update_10__gen_1
+        assign array_update_10[array_update_10__index_0][array_update_10__index_1] = 32'h0000_0000 == array_update_10__index_0 && 14'h0002 == array_update_10__index_1 ? value : a_unflattened[array_update_10__index_0][array_update_10__index_1];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayLiteralIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayLiteralIndex.vtxt
index e087a19150..0b5b3a871a 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayLiteralIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayLiteralIndex.vtxt
@@ -15,11 +15,14 @@ module ArrayUpdate2DUpdateArrayLiteralIndex(
   assign value_unflattened[1] = value[15:8];
   assign value_unflattened[2] = value[23:16];
   wire [7:0] array_update_8[0:1][0:2];
-  assign array_update_8[0][0] = a_unflattened[0][0];
-  assign array_update_8[0][1] = a_unflattened[0][1];
-  assign array_update_8[0][2] = a_unflattened[0][2];
-  assign array_update_8[1][0] = value_unflattened[0];
-  assign array_update_8[1][1] = value_unflattened[1];
-  assign array_update_8[1][2] = value_unflattened[2];
   assign out = {{array_update_8[1][2], array_update_8[1][1], array_update_8[1][0]}, {array_update_8[0][2], array_update_8[0][1], array_update_8[0][0]}};
+  genvar array_update_8__index_0;
+  genvar array_update_8__update_0;
+  generate
+    for (array_update_8__index_0 = 0; array_update_8__index_0 < 2; array_update_8__index_0 = array_update_8__index_0 + 1) begin : array_update_8__gen_0
+      for (array_update_8__update_0 = 0; array_update_8__update_0 < 3; array_update_8__update_0 = array_update_8__update_0 + 1) begin : array_update_8__gen_up_0
+        assign array_update_8[array_update_8__index_0][array_update_8__update_0] = 14'h0001 == array_update_8__index_0 ? value_unflattened[array_update_8__update_0] : a_unflattened[array_update_8__index_0][array_update_8__update_0];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayNilIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayNilIndex.vtxt
index 9d493da645..1abddbf876 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayNilIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayNilIndex.vtxt
@@ -18,11 +18,14 @@ module ArrayUpdate2DUpdateArrayNilIndex(
   assign value_unflattened[1][1] = value[39:32];
   assign value_unflattened[1][2] = value[47:40];
   wire [7:0] array_update_6[0:1][0:2];
-  assign array_update_6[0][0] = value_unflattened[0][0];
-  assign array_update_6[0][1] = value_unflattened[0][1];
-  assign array_update_6[0][2] = value_unflattened[0][2];
-  assign array_update_6[1][0] = value_unflattened[1][0];
-  assign array_update_6[1][1] = value_unflattened[1][1];
-  assign array_update_6[1][2] = value_unflattened[1][2];
   assign out = {{array_update_6[1][2], array_update_6[1][1], array_update_6[1][0]}, {array_update_6[0][2], array_update_6[0][1], array_update_6[0][0]}};
+  genvar array_update_6__update_0;
+  genvar array_update_6__update_1;
+  generate
+    for (array_update_6__update_0 = 0; array_update_6__update_0 < 2; array_update_6__update_0 = array_update_6__update_0 + 1) begin : array_update_6__gen_up_0
+      for (array_update_6__update_1 = 0; array_update_6__update_1 < 3; array_update_6__update_1 = array_update_6__update_1 + 1) begin : array_update_6__gen_up_1
+        assign array_update_6[array_update_6__update_0][array_update_6__update_1] = value_unflattened[array_update_6__update_0][array_update_6__update_1];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayVariableIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayVariableIndex.vtxt
index e267d5df11..11fe6deb88 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayVariableIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DUpdateArrayVariableIndex.vtxt
@@ -16,11 +16,14 @@ module ArrayUpdate2DUpdateArrayVariableIndex(
   assign value_unflattened[1] = value[15:8];
   assign value_unflattened[2] = value[23:16];
   wire [7:0] array_update_8[0:1][0:2];
-  assign array_update_8[0][0] = idx == 37'h00_0000_0000 ? value_unflattened[0] : a_unflattened[0][0];
-  assign array_update_8[0][1] = idx == 37'h00_0000_0000 ? value_unflattened[1] : a_unflattened[0][1];
-  assign array_update_8[0][2] = idx == 37'h00_0000_0000 ? value_unflattened[2] : a_unflattened[0][2];
-  assign array_update_8[1][0] = idx == 37'h00_0000_0001 ? value_unflattened[0] : a_unflattened[1][0];
-  assign array_update_8[1][1] = idx == 37'h00_0000_0001 ? value_unflattened[1] : a_unflattened[1][1];
-  assign array_update_8[1][2] = idx == 37'h00_0000_0001 ? value_unflattened[2] : a_unflattened[1][2];
   assign out = {{array_update_8[1][2], array_update_8[1][1], array_update_8[1][0]}, {array_update_8[0][2], array_update_8[0][1], array_update_8[0][0]}};
+  genvar array_update_8__index_0;
+  genvar array_update_8__update_0;
+  generate
+    for (array_update_8__index_0 = 0; array_update_8__index_0 < 2; array_update_8__index_0 = array_update_8__index_0 + 1) begin : array_update_8__gen_0
+      for (array_update_8__update_0 = 0; array_update_8__update_0 < 3; array_update_8__update_0 = array_update_8__update_0 + 1) begin : array_update_8__gen_up_0
+        assign array_update_8[array_update_8__index_0][array_update_8__update_0] = idx == array_update_8__index_0 ? value_unflattened[array_update_8__update_0] : a_unflattened[array_update_8__index_0][array_update_8__update_0];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DVariableIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DVariableIndex.vtxt
index daa89aeaaa..5abda45ccd 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DVariableIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdate2DVariableIndex.vtxt
@@ -13,11 +13,14 @@ module ArrayUpdate2DVariableIndex(
   assign a_unflattened[1][1] = a[39:32];
   assign a_unflattened[1][2] = a[47:40];
   wire [7:0] array_update_10[0:1][0:2];
-  assign array_update_10[0][0] = idx1 == 32'h0000_0000 && idx0 == 32'h0000_0000 ? value : a_unflattened[0][0];
-  assign array_update_10[0][1] = idx1 == 32'h0000_0001 && idx0 == 32'h0000_0000 ? value : a_unflattened[0][1];
-  assign array_update_10[0][2] = idx1 == 32'h0000_0002 && idx0 == 32'h0000_0000 ? value : a_unflattened[0][2];
-  assign array_update_10[1][0] = idx1 == 32'h0000_0000 && idx0 == 32'h0000_0001 ? value : a_unflattened[1][0];
-  assign array_update_10[1][1] = idx1 == 32'h0000_0001 && idx0 == 32'h0000_0001 ? value : a_unflattened[1][1];
-  assign array_update_10[1][2] = idx1 == 32'h0000_0002 && idx0 == 32'h0000_0001 ? value : a_unflattened[1][2];
   assign out = {{array_update_10[1][2], array_update_10[1][1], array_update_10[1][0]}, {array_update_10[0][2], array_update_10[0][1], array_update_10[0][0]}};
+  genvar array_update_10__index_0;
+  genvar array_update_10__index_1;
+  generate
+    for (array_update_10__index_0 = 0; array_update_10__index_0 < 2; array_update_10__index_0 = array_update_10__index_0 + 1) begin : array_update_10__gen_0
+      for (array_update_10__index_1 = 0; array_update_10__index_1 < 3; array_update_10__index_1 = array_update_10__index_1 + 1) begin : array_update_10__gen_1
+        assign array_update_10[array_update_10__index_0][array_update_10__index_1] = idx0 == array_update_10__index_0 && idx1 == array_update_10__index_1 ? value : a_unflattened[array_update_10__index_0][array_update_10__index_1];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateLiteralIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateLiteralIndex.vtxt
index 05380ae3b0..87a43a56ff 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateLiteralIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateLiteralIndex.vtxt
@@ -9,10 +9,10 @@ module ArrayUpdateLiteralIndex(
   assign a_unflattened[2] = a[23:16];
   wire [7:0] array_update_8[0:2];
   assign out = {array_update_8[2], array_update_8[1], array_update_8[0]};
-  genvar array_update_8__index;
+  genvar array_update_8__index_0;
   generate
-    for (array_update_8__index = 0; array_update_8__index < 3; array_update_8__index = array_update_8__index + 1) begin : array_update_8__gen
-      assign array_update_8[array_update_8__index] = 16'h0001 == array_update_8__index ? value : a_unflattened[array_update_8__index];
+    for (array_update_8__index_0 = 0; array_update_8__index_0 < 3; array_update_8__index_0 = array_update_8__index_0 + 1) begin : array_update_8__gen_0
+      assign array_update_8[array_update_8__index_0] = 16'h0001 == array_update_8__index_0 ? value : a_unflattened[array_update_8__index_0];
     end
   endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateVariableIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateVariableIndex.vtxt
index a9131ffda3..ac22c61639 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateVariableIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateVariableIndex.vtxt
@@ -10,10 +10,10 @@ module ArrayUpdateVariableIndex(
   assign a_unflattened[2] = a[23:16];
   wire [7:0] array_update_8[0:2];
   assign out = {array_update_8[2], array_update_8[1], array_update_8[0]};
-  genvar array_update_8__index;
+  genvar array_update_8__index_0;
   generate
-    for (array_update_8__index = 0; array_update_8__index < 3; array_update_8__index = array_update_8__index + 1) begin : array_update_8__gen
-      assign array_update_8[array_update_8__index] = idx == array_update_8__index ? value : a_unflattened[array_update_8__index];
+    for (array_update_8__index_0 = 0; array_update_8__index_0 < 3; array_update_8__index_0 = array_update_8__index_0 + 1) begin : array_update_8__gen_0
+      assign array_update_8[array_update_8__index_0] = idx == array_update_8__index_0 ? value : a_unflattened[array_update_8__index_0];
     end
   endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithDifferentTypesIndices.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithDifferentTypesIndices.vtxt
index dc40e81862..79e8d607af 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithDifferentTypesIndices.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithDifferentTypesIndices.vtxt
@@ -13,11 +13,14 @@ module ArrayUpdateWithDifferentTypesIndices(
   assign a_unflattened[1][1] = a[159:128];
   assign a_unflattened[1][2] = a[191:160];
   wire [31:0] array_update_10[0:1][0:2];
-  assign array_update_10[0][0] = i1 == 5'h00 && i0 == 4'h0 ? value : a_unflattened[0][0];
-  assign array_update_10[0][1] = i1 == 5'h01 && i0 == 4'h0 ? value : a_unflattened[0][1];
-  assign array_update_10[0][2] = i1 == 5'h02 && i0 == 4'h0 ? value : a_unflattened[0][2];
-  assign array_update_10[1][0] = i1 == 5'h00 && i0 == 4'h1 ? value : a_unflattened[1][0];
-  assign array_update_10[1][1] = i1 == 5'h01 && i0 == 4'h1 ? value : a_unflattened[1][1];
-  assign array_update_10[1][2] = i1 == 5'h02 && i0 == 4'h1 ? value : a_unflattened[1][2];
   assign out = {{array_update_10[1][2], array_update_10[1][1], array_update_10[1][0]}, {array_update_10[0][2], array_update_10[0][1], array_update_10[0][0]}};
+  genvar array_update_10__index_0;
+  genvar array_update_10__index_1;
+  generate
+    for (array_update_10__index_0 = 0; array_update_10__index_0 < 2; array_update_10__index_0 = array_update_10__index_0 + 1) begin : array_update_10__gen_0
+      for (array_update_10__index_1 = 0; array_update_10__index_1 < 3; array_update_10__index_1 = array_update_10__index_1 + 1) begin : array_update_10__gen_1
+        assign array_update_10[array_update_10__index_0][array_update_10__index_1] = i0 == array_update_10__index_0 && i1 == array_update_10__index_1 ? value : a_unflattened[array_update_10__index_0][array_update_10__index_1];
+      end
+    end
+  endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithNarrowIndex.vtxt b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithNarrowIndex.vtxt
index e1e66e2054..a6e9e8f6b0 100644
--- a/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithNarrowIndex.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_ArrayUpdateWithNarrowIndex.vtxt
@@ -17,10 +17,10 @@ module ArrayUpdateWithNarrowIndex(
   assign a_unflattened[9] = a[319:288];
   wire [31:0] array_update_8[0:9];
   assign out = {array_update_8[9], array_update_8[8], array_update_8[7], array_update_8[6], array_update_8[5], array_update_8[4], array_update_8[3], array_update_8[2], array_update_8[1], array_update_8[0]};
-  genvar array_update_8__index;
+  genvar array_update_8__index_0;
   generate
-    for (array_update_8__index = 0; array_update_8__index < 10; array_update_8__index = array_update_8__index + 1) begin : array_update_8__gen
-      assign array_update_8[array_update_8__index] = idx == array_update_8__index ? v : a_unflattened[array_update_8__index];
+    for (array_update_8__index_0 = 0; array_update_8__index_0 < 10; array_update_8__index_0 = array_update_8__index_0 + 1) begin : array_update_8__gen_0
+      assign array_update_8[array_update_8__index_0] = idx == array_update_8__index_0 ? v : a_unflattened[array_update_8__index_0];
     end
   endgenerate
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_PrioritySelectArrayOneHot.vtxt b/xls/codegen/testdata/combinational_generator_test_PrioritySelectArrayOneHot.vtxt
index 405cc6985c..a4444e1040 100644
--- a/xls/codegen/testdata/combinational_generator_test_PrioritySelectArrayOneHot.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_PrioritySelectArrayOneHot.vtxt
@@ -23,11 +23,13 @@ module main(
   wire [1:0] one_hot_15;
   wire [2:0] one_hot_18;
   wire [15:0] one_hot_sel_23[0:3];
+  wire eq_20;
   assign one_hot_15 = {!p, p};
   assign one_hot_18 = {one_hot_15[1:0] == 2'h0, one_hot_15[1] && !one_hot_15[0], one_hot_15[0]};
   assign one_hot_sel_23[0] = x_unflattened[0] & {16{one_hot_15[0]}} | y_unflattened[0] & {16{one_hot_15[1]}};
   assign one_hot_sel_23[1] = x_unflattened[1] & {16{one_hot_15[0]}} | y_unflattened[1] & {16{one_hot_15[1]}};
   assign one_hot_sel_23[2] = x_unflattened[2] & {16{one_hot_15[0]}} | y_unflattened[2] & {16{one_hot_15[1]}};
   assign one_hot_sel_23[3] = x_unflattened[3] & {16{one_hot_15[0]}} | y_unflattened[3] & {16{one_hot_15[1]}};
+  assign eq_20 = one_hot_15 == one_hot_18[1:0];
   assign out = {one_hot_sel_23[3], one_hot_sel_23[2], one_hot_sel_23[1], one_hot_sel_23[0]};
 endmodule
diff --git a/xls/codegen/testdata/combinational_generator_test_PrioritySelectOneHot.vtxt b/xls/codegen/testdata/combinational_generator_test_PrioritySelectOneHot.vtxt
index f3364a7896..58945e9ece 100644
--- a/xls/codegen/testdata/combinational_generator_test_PrioritySelectOneHot.vtxt
+++ b/xls/codegen/testdata/combinational_generator_test_PrioritySelectOneHot.vtxt
@@ -7,7 +7,9 @@ module main(
 );
   wire [1:0] one_hot_15;
   wire [2:0] one_hot_18;
+  wire eq_20;
   assign one_hot_15 = {!p, p};
   assign one_hot_18 = {one_hot_15[1:0] == 2'h0, one_hot_15[1] && !one_hot_15[0], one_hot_15[0]};
+  assign eq_20 = one_hot_15 == one_hot_18[1:0];
   assign out = x & {16{one_hot_15[0]}} | y & {16{one_hot_15[1]}};
 endmodule
diff --git a/xls/codegen/testdata/module_builder_test_ArrayUpdate1D.vtxt b/xls/codegen/testdata/module_builder_test_ArrayUpdate1D.vtxt
index d94fdaa957..0615a84a94 100644
--- a/xls/codegen/testdata/module_builder_test_ArrayUpdate1D.vtxt
+++ b/xls/codegen/testdata/module_builder_test_ArrayUpdate1D.vtxt
@@ -9,10 +9,10 @@ module ArrayUpdate1D(
   assign array_unflattened[2] = array[95:64];
   assign array_unflattened[3] = array[127:96];
   wire [31:0] updated_array[0:3];
-  genvar array_update_4__index;
+  genvar array_update_4__index_0;
   generate
-    for (array_update_4__index = 0; array_update_4__index < 4; array_update_4__index = array_update_4__index + 1) begin : array_update_4__gen
-      assign updated_array[array_update_4__index] = value == array_update_4__index ? index : array_unflattened[array_update_4__index];
+    for (array_update_4__index_0 = 0; array_update_4__index_0 < 4; array_update_4__index_0 = array_update_4__index_0 + 1) begin : array_update_4__gen_0
+      assign updated_array[array_update_4__index_0] = value == array_update_4__index_0 ? index : array_unflattened[array_update_4__index_0];
     end
   endgenerate
 endmodule
diff --git a/xls/codegen/testdata/module_builder_test_ArrayUpdate4D.vtxt b/xls/codegen/testdata/module_builder_test_ArrayUpdate4D.vtxt
new file mode 100644
index 0000000000..102096f7ae
--- /dev/null
+++ b/xls/codegen/testdata/module_builder_test_ArrayUpdate4D.vtxt
@@ -0,0 +1,155 @@
+module ArrayUpdate4D(
+  input wire [3839:0] array,
+  input wire [1:0] idx0,
+  input wire [1:0] idx1,
+  input wire [319:0] value
+);
+  wire [31:0] array_unflattened[0:3][0:2][0:1][0:4];
+  assign array_unflattened[0][0][0][0] = array[31:0];
+  assign array_unflattened[0][0][0][1] = array[63:32];
+  assign array_unflattened[0][0][0][2] = array[95:64];
+  assign array_unflattened[0][0][0][3] = array[127:96];
+  assign array_unflattened[0][0][0][4] = array[159:128];
+  assign array_unflattened[0][0][1][0] = array[191:160];
+  assign array_unflattened[0][0][1][1] = array[223:192];
+  assign array_unflattened[0][0][1][2] = array[255:224];
+  assign array_unflattened[0][0][1][3] = array[287:256];
+  assign array_unflattened[0][0][1][4] = array[319:288];
+  assign array_unflattened[0][1][0][0] = array[351:320];
+  assign array_unflattened[0][1][0][1] = array[383:352];
+  assign array_unflattened[0][1][0][2] = array[415:384];
+  assign array_unflattened[0][1][0][3] = array[447:416];
+  assign array_unflattened[0][1][0][4] = array[479:448];
+  assign array_unflattened[0][1][1][0] = array[511:480];
+  assign array_unflattened[0][1][1][1] = array[543:512];
+  assign array_unflattened[0][1][1][2] = array[575:544];
+  assign array_unflattened[0][1][1][3] = array[607:576];
+  assign array_unflattened[0][1][1][4] = array[639:608];
+  assign array_unflattened[0][2][0][0] = array[671:640];
+  assign array_unflattened[0][2][0][1] = array[703:672];
+  assign array_unflattened[0][2][0][2] = array[735:704];
+  assign array_unflattened[0][2][0][3] = array[767:736];
+  assign array_unflattened[0][2][0][4] = array[799:768];
+  assign array_unflattened[0][2][1][0] = array[831:800];
+  assign array_unflattened[0][2][1][1] = array[863:832];
+  assign array_unflattened[0][2][1][2] = array[895:864];
+  assign array_unflattened[0][2][1][3] = array[927:896];
+  assign array_unflattened[0][2][1][4] = array[959:928];
+  assign array_unflattened[1][0][0][0] = array[991:960];
+  assign array_unflattened[1][0][0][1] = array[1023:992];
+  assign array_unflattened[1][0][0][2] = array[1055:1024];
+  assign array_unflattened[1][0][0][3] = array[1087:1056];
+  assign array_unflattened[1][0][0][4] = array[1119:1088];
+  assign array_unflattened[1][0][1][0] = array[1151:1120];
+  assign array_unflattened[1][0][1][1] = array[1183:1152];
+  assign array_unflattened[1][0][1][2] = array[1215:1184];
+  assign array_unflattened[1][0][1][3] = array[1247:1216];
+  assign array_unflattened[1][0][1][4] = array[1279:1248];
+  assign array_unflattened[1][1][0][0] = array[1311:1280];
+  assign array_unflattened[1][1][0][1] = array[1343:1312];
+  assign array_unflattened[1][1][0][2] = array[1375:1344];
+  assign array_unflattened[1][1][0][3] = array[1407:1376];
+  assign array_unflattened[1][1][0][4] = array[1439:1408];
+  assign array_unflattened[1][1][1][0] = array[1471:1440];
+  assign array_unflattened[1][1][1][1] = array[1503:1472];
+  assign array_unflattened[1][1][1][2] = array[1535:1504];
+  assign array_unflattened[1][1][1][3] = array[1567:1536];
+  assign array_unflattened[1][1][1][4] = array[1599:1568];
+  assign array_unflattened[1][2][0][0] = array[1631:1600];
+  assign array_unflattened[1][2][0][1] = array[1663:1632];
+  assign array_unflattened[1][2][0][2] = array[1695:1664];
+  assign array_unflattened[1][2][0][3] = array[1727:1696];
+  assign array_unflattened[1][2][0][4] = array[1759:1728];
+  assign array_unflattened[1][2][1][0] = array[1791:1760];
+  assign array_unflattened[1][2][1][1] = array[1823:1792];
+  assign array_unflattened[1][2][1][2] = array[1855:1824];
+  assign array_unflattened[1][2][1][3] = array[1887:1856];
+  assign array_unflattened[1][2][1][4] = array[1919:1888];
+  assign array_unflattened[2][0][0][0] = array[1951:1920];
+  assign array_unflattened[2][0][0][1] = array[1983:1952];
+  assign array_unflattened[2][0][0][2] = array[2015:1984];
+  assign array_unflattened[2][0][0][3] = array[2047:2016];
+  assign array_unflattened[2][0][0][4] = array[2079:2048];
+  assign array_unflattened[2][0][1][0] = array[2111:2080];
+  assign array_unflattened[2][0][1][1] = array[2143:2112];
+  assign array_unflattened[2][0][1][2] = array[2175:2144];
+  assign array_unflattened[2][0][1][3] = array[2207:2176];
+  assign array_unflattened[2][0][1][4] = array[2239:2208];
+  assign array_unflattened[2][1][0][0] = array[2271:2240];
+  assign array_unflattened[2][1][0][1] = array[2303:2272];
+  assign array_unflattened[2][1][0][2] = array[2335:2304];
+  assign array_unflattened[2][1][0][3] = array[2367:2336];
+  assign array_unflattened[2][1][0][4] = array[2399:2368];
+  assign array_unflattened[2][1][1][0] = array[2431:2400];
+  assign array_unflattened[2][1][1][1] = array[2463:2432];
+  assign array_unflattened[2][1][1][2] = array[2495:2464];
+  assign array_unflattened[2][1][1][3] = array[2527:2496];
+  assign array_unflattened[2][1][1][4] = array[2559:2528];
+  assign array_unflattened[2][2][0][0] = array[2591:2560];
+  assign array_unflattened[2][2][0][1] = array[2623:2592];
+  assign array_unflattened[2][2][0][2] = array[2655:2624];
+  assign array_unflattened[2][2][0][3] = array[2687:2656];
+  assign array_unflattened[2][2][0][4] = array[2719:2688];
+  assign array_unflattened[2][2][1][0] = array[2751:2720];
+  assign array_unflattened[2][2][1][1] = array[2783:2752];
+  assign array_unflattened[2][2][1][2] = array[2815:2784];
+  assign array_unflattened[2][2][1][3] = array[2847:2816];
+  assign array_unflattened[2][2][1][4] = array[2879:2848];
+  assign array_unflattened[3][0][0][0] = array[2911:2880];
+  assign array_unflattened[3][0][0][1] = array[2943:2912];
+  assign array_unflattened[3][0][0][2] = array[2975:2944];
+  assign array_unflattened[3][0][0][3] = array[3007:2976];
+  assign array_unflattened[3][0][0][4] = array[3039:3008];
+  assign array_unflattened[3][0][1][0] = array[3071:3040];
+  assign array_unflattened[3][0][1][1] = array[3103:3072];
+  assign array_unflattened[3][0][1][2] = array[3135:3104];
+  assign array_unflattened[3][0][1][3] = array[3167:3136];
+  assign array_unflattened[3][0][1][4] = array[3199:3168];
+  assign array_unflattened[3][1][0][0] = array[3231:3200];
+  assign array_unflattened[3][1][0][1] = array[3263:3232];
+  assign array_unflattened[3][1][0][2] = array[3295:3264];
+  assign array_unflattened[3][1][0][3] = array[3327:3296];
+  assign array_unflattened[3][1][0][4] = array[3359:3328];
+  assign array_unflattened[3][1][1][0] = array[3391:3360];
+  assign array_unflattened[3][1][1][1] = array[3423:3392];
+  assign array_unflattened[3][1][1][2] = array[3455:3424];
+  assign array_unflattened[3][1][1][3] = array[3487:3456];
+  assign array_unflattened[3][1][1][4] = array[3519:3488];
+  assign array_unflattened[3][2][0][0] = array[3551:3520];
+  assign array_unflattened[3][2][0][1] = array[3583:3552];
+  assign array_unflattened[3][2][0][2] = array[3615:3584];
+  assign array_unflattened[3][2][0][3] = array[3647:3616];
+  assign array_unflattened[3][2][0][4] = array[3679:3648];
+  assign array_unflattened[3][2][1][0] = array[3711:3680];
+  assign array_unflattened[3][2][1][1] = array[3743:3712];
+  assign array_unflattened[3][2][1][2] = array[3775:3744];
+  assign array_unflattened[3][2][1][3] = array[3807:3776];
+  assign array_unflattened[3][2][1][4] = array[3839:3808];
+  wire [31:0] value_unflattened[0:1][0:4];
+  assign value_unflattened[0][0] = value[31:0];
+  assign value_unflattened[0][1] = value[63:32];
+  assign value_unflattened[0][2] = value[95:64];
+  assign value_unflattened[0][3] = value[127:96];
+  assign value_unflattened[0][4] = value[159:128];
+  assign value_unflattened[1][0] = value[191:160];
+  assign value_unflattened[1][1] = value[223:192];
+  assign value_unflattened[1][2] = value[255:224];
+  assign value_unflattened[1][3] = value[287:256];
+  assign value_unflattened[1][4] = value[319:288];
+  wire [31:0] updated_array[0:3][0:2][0:1][0:4];
+  genvar array_update_5__index_0;
+  genvar array_update_5__index_1;
+  genvar array_update_5__update_0;
+  genvar array_update_5__update_1;
+  generate
+    for (array_update_5__index_0 = 0; array_update_5__index_0 < 4; array_update_5__index_0 = array_update_5__index_0 + 1) begin : array_update_5__gen_0
+      for (array_update_5__index_1 = 0; array_update_5__index_1 < 3; array_update_5__index_1 = array_update_5__index_1 + 1) begin : array_update_5__gen_1
+        for (array_update_5__update_0 = 0; array_update_5__update_0 < 2; array_update_5__update_0 = array_update_5__update_0 + 1) begin : array_update_5__gen_up_0
+          for (array_update_5__update_1 = 0; array_update_5__update_1 < 5; array_update_5__update_1 = array_update_5__update_1 + 1) begin : array_update_5__gen_up_1
+            assign updated_array[array_update_5__index_0][array_update_5__index_1][array_update_5__update_0][array_update_5__update_1] = idx0 == array_update_5__index_0 && idx1 == array_update_5__index_1 ? value_unflattened[array_update_5__update_0][array_update_5__update_1] : array_unflattened[array_update_5__index_0][array_update_5__index_1][array_update_5__update_0][array_update_5__update_1];
+          end
+        end
+      end
+    end
+  endgenerate
+endmodule
diff --git a/xls/codegen/testdata/module_builder_test_ArrayUpdateWithTupleWithNestedArray.vtxt b/xls/codegen/testdata/module_builder_test_ArrayUpdateWithTupleWithNestedArray.vtxt
new file mode 100644
index 0000000000..91801bc206
--- /dev/null
+++ b/xls/codegen/testdata/module_builder_test_ArrayUpdateWithTupleWithNestedArray.vtxt
@@ -0,0 +1,17 @@
+module ArrayUpdateWithTupleWithNestedArray(
+  input wire [143:0] array,
+  input wire [1:0] idx,
+  input wire [47:0] value
+);
+  wire [47:0] array_unflattened[0:2];
+  assign array_unflattened[0] = array[47:0];
+  assign array_unflattened[1] = array[95:48];
+  assign array_unflattened[2] = array[143:96];
+  wire [47:0] updated_array[0:2];
+  genvar array_update_4__index_0;
+  generate
+    for (array_update_4__index_0 = 0; array_update_4__index_0 < 3; array_update_4__index_0 = array_update_4__index_0 + 1) begin : array_update_4__gen_0
+      assign updated_array[array_update_4__index_0] = idx == array_update_4__index_0 ? value : array_unflattened[array_update_4__index_0];
+    end
+  endgenerate
+endmodule
diff --git a/xls/codegen/vast/vast.cc b/xls/codegen/vast/vast.cc
index c61e36ffaa..fb25593dd6 100644
--- a/xls/codegen/vast/vast.cc
+++ b/xls/codegen/vast/vast.cc
@@ -576,38 +576,43 @@ std::string StatementBlock::Emit(LineInfo* line_info) const {
   return result;
 }
 
-GenerateLoop::GenerateLoop(LogicRef* genvar, Expression* init,
-                           Expression* limit,
-                           std::optional<std::string_view> label,
-                           VerilogFile* file, const SourceInfo& loc)
-    : Statement(file, loc),
-      genvar_(genvar),
-      init_(init),
-      limit_(limit),
-      label_(label) {
-  genvar_def_ = dynamic_cast<GenvarDef*>(genvar->def());
-}
-
 std::string GenerateLoop::Emit(LineInfo* line_info) const {
   LineInfoStart(line_info, this);
   std::vector<std::string> lines;
   lines.push_back(absl::StrFormat("generate"));
   LineInfoIncrease(line_info, 1);
-  std::string label_suffix =
-      label_.has_value() ? absl::StrCat(" : ", label_.value()) : "";
-  lines.push_back(Indent(absl::StrFormat(
-      "for (%s = %s; %s < %s; %s = %s + 1) begin%s", genvar_->Emit(line_info),
-      init_->Emit(line_info), genvar_->Emit(line_info), limit_->Emit(line_info),
-      genvar_->Emit(line_info), genvar_->Emit(line_info), label_suffix)));
-  for (const auto& node : body_) {
-    std::string pre_emit = node->PreEmit(line_info);
+  int indent_level = 1;
+  for (const GenerateLoopIterationSpec& iteration : iterations_) {
+    std::string label_suffix =
+        iteration.label.has_value()
+            ? absl::StrCat(" : ", iteration.label.value())
+            : "";
+    lines.push_back(Indent(
+        absl::StrFormat(
+            "for (%s = %s; %s < %s; %s = %s + 1) begin%s",
+            iteration.genvar->Emit(line_info), iteration.init->Emit(line_info),
+            iteration.genvar->Emit(line_info), iteration.limit->Emit(line_info),
+            iteration.genvar->Emit(line_info),
+            iteration.genvar->Emit(line_info), label_suffix),
+        indent_level * kDefaultIndentSpaces));
+    LineInfoIncrease(line_info, 1);
+    indent_level++;
+  }
+  for (Statement* statement : statements_) {
+    std::string pre_emit = statement->PreEmit(line_info);
     if (!pre_emit.empty()) {
-      lines.push_back(Indent(Indent(pre_emit)));
+      lines.push_back(Indent(pre_emit, indent_level * kDefaultIndentSpaces));
+      LineInfoIncrease(line_info, 1);
     }
-    lines.push_back(Indent(Indent(node->Emit(line_info))));
+    lines.push_back(Indent(statement->Emit(line_info),
+                           indent_level * kDefaultIndentSpaces));
+    LineInfoIncrease(line_info, 1);
+  }
+  for (const GenerateLoopIterationSpec& _ : iterations_) {
+    indent_level--;
+    lines.push_back(Indent("end", indent_level * kDefaultIndentSpaces));
     LineInfoIncrease(line_info, 1);
   }
-  lines.push_back(Indent("end"));
   lines.push_back("endgenerate");
   LineInfoEnd(line_info, this);
   return absl::StrJoin(lines, "\n");
@@ -680,7 +685,8 @@ std::string VerilogFunction::Emit(LineInfo* line_info) const {
       return_value_def_->data_type()->EmitWithIdentifier(line_info, name());
   if (return_value_def_->data_type()->IsScalar() &&
       file()->use_system_verilog()) {
-    // Preface the return type with "logic", so there's always a type provided.
+    // Preface the return type with "logic", so there's always a type
+    // provided.
     return_type =
         absl::StrCat(DataKindToString(DataKind::kLogic), " ", return_type);
   }
@@ -986,7 +992,8 @@ std::string FourValueBinaryLiteral::Emit(LineInfo* line_info) const {
 // Returns a string representation of the given expression minus one.
 static std::string WidthToLimit(LineInfo* line_info, Expression* expr) {
   if (expr->IsLiteral()) {
-    // If the expression is a literal, then we can emit the value - 1 directly.
+    // If the expression is a literal, then we can emit the value - 1
+    // directly.
     uint64_t value = expr->AsLiteralOrDie()->bits().ToUint64().value();
     return absl::StrCat(value - 1);
   }
@@ -1087,8 +1094,8 @@ std::string PackedArrayType::Emit(LineInfo* line_info) const {
   LineInfoStart(line_info, this);
   std::string result = element_type()->Emit(line_info);
   if (element_type()->IsUserDefined()) {
-    // Imitate the space that a bit vector emits between the kind and innermost
-    // dimension.
+    // Imitate the space that a bit vector emits between the kind and
+    // innermost dimension.
     absl::StrAppend(&result, " ");
   }
   for (Expression* dim : dims()) {
@@ -1334,7 +1341,8 @@ std::string DeferredImmediateAssertion::Emit(LineInfo* line_info) const {
 
 std::string Cover::Emit(LineInfo* line_info) const {
   LineInfoStart(line_info, this);
-  // Coverpoints don't work without clock sources. Don't emit them in that case.
+  // Coverpoints don't work without clock sources. Don't emit them in that
+  // case.
   LineInfoIncrease(line_info, NumberOfNewlines(label_));
   std::string clock = clk_->Emit(line_info);
   std::string condition = condition_->Emit(line_info);
@@ -1510,7 +1518,8 @@ std::string Slice::Emit(LineInfo* line_info) const {
     // If subject is scalar (no width given in declaration) then avoid slicing
     // as this is invalid Verilog. The only valid hi/lo values are zero.
     // TODO(https://github.com/google/xls/issues/43): Avoid this special case
-    // and perform the equivalent logic at a higher abstraction level than VAST.
+    // and perform the equivalent logic at a higher abstraction level than
+    // VAST.
     CHECK(hi_->IsLiteralWithValue(0)) << hi_->Emit(nullptr);
     CHECK(lo_->IsLiteralWithValue(0)) << lo_->Emit(nullptr);
     std::string result = subject_->Emit(line_info);
@@ -1536,10 +1545,12 @@ std::string PartSelect::Emit(LineInfo* line_info) const {
 std::string Index::Emit(LineInfo* line_info) const {
   LineInfoStart(line_info, this);
   if (IsScalarLogicRef(subject_)) {
-    // If subject is scalar (no width given in declaration) then avoid indexing
-    // as this is invalid Verilog. The only valid index values are zero.
+    // If subject is scalar (no width given in declaration) then avoid
+    // indexing as this is invalid Verilog. The only valid index values are
+    // zero.
     // TODO(https://github.com/google/xls/issues/43): Avoid this special case
-    // and perform the equivalent logic at a higher abstraction level than VAST.
+    // and perform the equivalent logic at a higher abstraction level than
+    // VAST.
     CHECK(index_->IsLiteralWithValue(0)) << absl::StreamFormat(
         "%s[%s]", subject_->Emit(nullptr), index_->Emit(nullptr));
     std::string result = subject_->Emit(line_info);
@@ -1722,9 +1733,9 @@ std::string BinaryInfix::Emit(LineInfo* line_info) const {
     return e->IsUnary() && e->AsUnaryOrDie()->IsReduction();
   };
 
-  // Equal precedence operators are evaluated left-to-right so LHS only needs to
-  // be wrapped if its precedence is strictly less than this operators. The RHS,
-  // however, must be wrapped if its less than or equal precedence. Unary
+  // Equal precedence operators are evaluated left-to-right so LHS only needs
+  // to be wrapped if its precedence is strictly less than this operators. The
+  // RHS, however, must be wrapped if its less than or equal precedence. Unary
   // reduction operations should be wrapped in parenthesis unconditionally
   // because some consumers of verilog emit warnings/errors for this
   // error-prone construct (e.g., `|x || |y`)
@@ -1840,8 +1851,8 @@ Conditional::Conditional(Expression* condition, VerilogFile* file,
       consequent_(file->Make<StatementBlock>(SourceInfo())) {}
 
 StatementBlock* Conditional::AddAlternate(Expression* condition) {
-  // The conditional must not have been previously closed with an unconditional
-  // alternate ("else").
+  // The conditional must not have been previously closed with an
+  // unconditional alternate ("else").
   CHECK(alternates_.empty() || alternates_.back().first != nullptr);
   alternates_.push_back(
       {condition, file()->Make<StatementBlock>(SourceInfo())});
diff --git a/xls/codegen/vast/vast.h b/xls/codegen/vast/vast.h
index 7d41ddc05b..c4506fcb08 100644
--- a/xls/codegen/vast/vast.h
+++ b/xls/codegen/vast/vast.h
@@ -698,24 +698,33 @@ class StatementBlock final : public VastNode {
 //   end
 // endgenerate
 // ```
+//
+// Multiple nested loops are supported but the body must be a single statement.
+struct GenerateLoopIterationSpec {
+  LogicRef* genvar;
+  Expression* init;
+  Expression* limit;
+  std::optional<std::string> label;
+};
+
 class GenerateLoop final : public Statement {
  public:
   GenerateLoop(LogicRef* genvar, Expression* init, Expression* limit,
-               std::optional<std::string_view> label, VerilogFile* file,
-               const SourceInfo& loc);
-
-  void AddBodyNode(VastNode* node) { body_.push_back(node); }
+               std::optional<std::string> label, VerilogFile* file,
+               const SourceInfo& loc)
+      : GenerateLoop({GenerateLoopIterationSpec{genvar, init, limit, label}},
+                     file, loc) {}
+  GenerateLoop(absl::Span<const GenerateLoopIterationSpec> iterations,
+               VerilogFile* file, const SourceInfo& loc)
+      : Statement(file, loc),
+        iterations_(iterations.begin(), iterations.end()) {}
+  void AddStatement(Statement* statement) { statements_.push_back(statement); }
 
   std::string Emit(LineInfo* line_info) const final;
 
  private:
-  LogicRef* genvar_;
-  GenvarDef* genvar_def_;
-
-  Expression* init_;
-  Expression* limit_;
-  std::vector<VastNode*> body_;
-  std::optional<std::string> label_;
+  std::vector<GenerateLoopIterationSpec> iterations_;
+  std::vector<Statement*> statements_;
 };
 
 // Similar to statement block,  but for use if `ifdef `else `endif blocks (no
@@ -1864,11 +1873,11 @@ class Ternary final : public Expression {
 // expressions; e.g.
 //
 //    assign {x, y, z} = {a, b, c};
-class ContinuousAssignment final : public VastNode {
+class ContinuousAssignment final : public Statement {
  public:
   ContinuousAssignment(Expression* lhs, Expression* rhs, VerilogFile* file,
                        const SourceInfo& loc)
-      : VastNode(file, loc), lhs_(lhs), rhs_(rhs) {}
+      : Statement(file, loc), lhs_(lhs), rhs_(rhs) {}
 
   std::string Emit(LineInfo* line_info) const final;
   std::string PreEmit(LineInfo* line_info) override;
diff --git a/xls/codegen/vast/vast_test.cc b/xls/codegen/vast/vast_test.cc
index 3ae442f4b7..3a9b5c845b 100644
--- a/xls/codegen/vast/vast_test.cc
+++ b/xls/codegen/vast/vast_test.cc
@@ -21,14 +21,14 @@
 #include <utility>
 #include <vector>
 
-#include "gmock/gmock.h"
-#include "gtest/gtest.h"
 #include "absl/container/flat_hash_map.h"
 #include "absl/status/status.h"
 #include "absl/status/status_matchers.h"
 #include "absl/strings/str_cat.h"
 #include "absl/strings/str_format.h"
 #include "absl/types/span.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
 #include "xls/common/status/matchers.h"
 #include "xls/ir/bits.h"
 #include "xls/ir/fileno.h"
@@ -2658,7 +2658,7 @@ TEST_P(VastTest, SimpleGenerateLoop) {
   // This is not generally necessary but shows a simple legal case.
   auto* generate_loop = m->Add<GenerateLoop>(
       si, i, f.PlainLiteral(0, si), f.PlainLiteral(32, si), "gen_loop");
-  generate_loop->AddBodyNode(f.Make<ContinuousAssignment>(
+  generate_loop->AddStatement(f.Make<ContinuousAssignment>(
       si, f.Make<Index>(si, output, i), f.Make<Index>(si, input, i)));
 
   LineInfo line_info;
@@ -2676,6 +2676,49 @@ TEST_P(VastTest, SimpleGenerateLoop) {
 endmodule)");
 }
 
+TEST_P(VastTest, NestedGenerateLoop) {
+  VerilogFile f(GetFileType());
+  const SourceInfo si;
+  Module* m = f.AddModule("top", si);
+
+  // Create two 2D packed array wires: src and dst with dimensions [4][3].
+  DataType* array_type = f.PackedArrayType(/*element_bit_count=*/1, {4, 3}, si);
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * src, m->AddWire("src", array_type, si));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * dst, m->AddWire("dst", array_type, si));
+
+  // Create two genvars for nested generate loops.
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * i, m->AddGenvar("i", si));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * j, m->AddGenvar("j", si));
+
+  // Add a doubly nested generate loop that assigns dst[i][j] = src[i][j].
+  GenerateLoopIterationSpec outer{i, f.PlainLiteral(0, si),
+                                  f.PlainLiteral(4, si), "outer"};
+  GenerateLoopIterationSpec inner{j, f.PlainLiteral(0, si),
+                                  f.PlainLiteral(3, si), "inner"};
+  std::vector<GenerateLoopIterationSpec> iterations = {outer, inner};
+  auto* generate_loop =
+      m->Add<GenerateLoop>(si, absl::MakeConstSpan(iterations));
+  generate_loop->AddStatement(f.Make<ContinuousAssignment>(
+      si, f.Make<Index>(si, f.Make<Index>(si, dst, i), j),
+      f.Make<Index>(si, f.Make<Index>(si, src, i), j)));
+
+  LineInfo line_info;
+  EXPECT_EQ(m->Emit(&line_info),
+            R"(module top;
+  wire [0:0][3:0][2:0] src;
+  wire [0:0][3:0][2:0] dst;
+  genvar i;
+  genvar j;
+  generate
+    for (i = 0; i < 4; i = i + 1) begin : outer
+      for (j = 0; j < 3; j = j + 1) begin : inner
+        assign dst[i][j] = src[i][j];
+      end
+    end
+  endgenerate
+endmodule)");
+}
+
 TEST_P(VastTest, ModuleParametersPortsNoIo) {
   VerilogFile f(GetFileType());
   Module* m = f.AddModule("top", SourceInfo());
diff --git a/xls/contrib/xlscc/unit_tests/testdata/translator_verilog_test_IOProcComboGenOneToNMux.vtxt b/xls/contrib/xlscc/unit_tests/testdata/translator_verilog_test_IOProcComboGenOneToNMux.vtxt
index 495c0b7f26..5b1095e7d0 100644
--- a/xls/contrib/xlscc/unit_tests/testdata/translator_verilog_test_IOProcComboGenOneToNMux.vtxt
+++ b/xls/contrib/xlscc/unit_tests/testdata/translator_verilog_test_IOProcComboGenOneToNMux.vtxt
@@ -12,15 +12,13 @@ module foo_proc(
 );
   wire continuation_3_ctx_3__full_condi_output__1;
   wire ctx_3__full_condition_ctx_3__rel_output__1;
-  wire literal_225;
   wire p0_all_active_outputs_ready;
   assign continuation_3_ctx_3__full_condi_output__1 = dir == 32'h0000_0000;
   assign ctx_3__full_condition_ctx_3__rel_output__1 = ~continuation_3_ctx_3__full_condi_output__1;
-  assign literal_225 = 1'h1;
   assign p0_all_active_outputs_ready = (~continuation_3_ctx_3__full_condi_output__1 | out1_rdy) & (~ctx_3__full_condition_ctx_3__rel_output__1 | out2_rdy);
   assign in_rdy = p0_all_active_outputs_ready;
   assign out1 = in;
-  assign out1_vld = in_vld & literal_225 & literal_225 & continuation_3_ctx_3__full_condi_output__1;
+  assign out1_vld = in_vld & 1'h1 & 1'h1 & continuation_3_ctx_3__full_condi_output__1;
   assign out2 = in;
-  assign out2_vld = in_vld & literal_225 & literal_225 & ctx_3__full_condition_ctx_3__rel_output__1;
+  assign out2_vld = in_vld & 1'h1 & 1'h1 & ctx_3__full_condition_ctx_3__rel_output__1;
 endmodule
diff --git a/xls/dev_tools/rebuild_golden_files.sh b/xls/dev_tools/rebuild_golden_files.sh
index 0e884c0810..0c1064444e 100755
--- a/xls/dev_tools/rebuild_golden_files.sh
+++ b/xls/dev_tools/rebuild_golden_files.sh
@@ -1,4 +1,4 @@
-#!/bin/sh -ex
+#!/bin/bash -ex
 
 # Rebuilds the golden files of all tests using
 # `xls/common/golden_files.h` infrastructure.
@@ -10,7 +10,8 @@ if [[ "$@" ]]
 then
   TARGETS=($@)
 else
-  TARGETS=($(bazel query "kind(cc_test, rdeps(//xls/..., //xls/common:golden_files))"))
+  # Keep-going and ignore failures as the query hits irrelevant errors in OSS.
+  TARGETS=($(bazel query "kind(cc_test, rdeps(//xls/..., //xls/common:golden_files) except //xls/common:golden_files_test)" --keep_going || /bin/true))
 fi
 
 if [[ ! -f "$(pwd)/WORKSPACE" ]]