target/riscv: Enable Sv32 for xlen=64

Before this patch, the sv32 only works with xlen=32. The new proposal of
64sv32 in the RVI community would permit xlen=64 sv32 to support
s64ilp32 Linux. The difference is that sv32 allows zext(MSB) and
sext(MSB) concurrently, but sv39,48.57 only allows sext(MSB).

Signed-off-by: Weiwei Li <[email protected]>
Reviewed-by: Guo Ren <[email protected]>

Author: Weiwei Li

target/riscv/cpu_helper.c

@@ -872,8 +872,12 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     }
     masked_msbs = (addr >> (va_bits - 1)) & mask;
 
-    if (masked_msbs != 0 && masked_msbs != mask) {
-        return TRANSLATE_FAIL;
+    if (vm == VM_1_10_SV32) {
+        if (masked_msbs != 0 && masked_msbs != mask && masked_msbs != 1)
+            return TRANSLATE_FAIL;
+    } else {
+        if (masked_msbs != 0 && masked_msbs != mask)
+            return TRANSLATE_FAIL;
     }
 
     int ptshift = (levels - 1) * ptidxbits;

target/riscv/csr.c

@@ -1130,6 +1130,7 @@ static const char valid_vm_1_10_32[16] = {
 
 static const char valid_vm_1_10_64[16] = {
     [VM_1_10_MBARE] = 1,
+    [VM_1_10_SV32] = 1,
     [VM_1_10_SV39] = 1,
     [VM_1_10_SV48] = 1,
     [VM_1_10_SV57] = 1