From c2e987c70adf4b25c64b287ffa28fdf8a79e2513 Mon Sep 17 00:00:00 2001 From: "B.Burt" <144288296+beeburt@users.noreply.github.com> Date: Sat, 9 Dec 2023 17:12:35 -0700 Subject: [PATCH] Update 1-the-basics.mdx - change "different" to "difference" --- src/content/chapters/1-the-basics.mdx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/content/chapters/1-the-basics.mdx b/src/content/chapters/1-the-basics.mdx index 9042633..85d3411 100644 --- a/src/content/chapters/1-the-basics.mdx +++ b/src/content/chapters/1-the-basics.mdx @@ -78,7 +78,7 @@ In kernel mode, anything goes: the CPU is allowed to execute any supported instr Processors start in kernel mode. Before executing a program, the kernel initiates the switch to user mode. -Two fake iMessage screenshots demonstrating the different between user and kernel mode protections. The first, labeled Kernel Mode: right side says "Read this protected memory!", left side replies "Here you go, dear :)". The second, labeled User Mode: right side says "Read this protected memory!", left side replies "No! Segmentation fault!" +Two fake iMessage screenshots demonstrating the difference between user and kernel mode protections. The first, labeled Kernel Mode: right side says "Read this protected memory!", left side replies "Here you go, dear :)". The second, labeled User Mode: right side says "Read this protected memory!", left side replies "No! Segmentation fault!" An example of how processor modes manifest in a real architecture: on x86-64, the current privilege level (CPL) can be read from a register called `cs` (code segment). Specifically, the CPL is contained in the two [least significant bits](https://en.wikipedia.org/wiki/Bit_numbering) of the `cs` register. Those two bits can store x86-64's four possible rings: ring 0 is kernel mode and ring 3 is user mode. Rings 1 and 2 are designed for running drivers but are only used by a handful of older niche operating systems. If the CPL bits are `11`, for example, the CPU is running in ring 3: user mode.