RISC-V cross-compilation without RVV support

[bpervan]

Hi all,

I'm trying to cross-compile a Halide kernel to a RISC-V platform. The target is a research (embedded) platform that is complex from the architectural point of view but relatively simple from the software perspective (no OS, no runtime, etc.). However, whenever I try to cross-compile a kernel for RISC-V target (with some additional flags), I face multiple errors related to the support for RVV.

Here is the snippet of setting the target:

Halide::Target target;
target.os = Halide::Target::NoOS;
target.arch = Halide::Target::RISCV;
target.bits = 32;
//target.vector_bits = 128;

std::vector<Halide::Target::Feature> features;
features.push_back(Halide::Target::Feature::SoftFloatABI);
features.push_back(Halide::Target::Feature::NoAsserts);
features.push_back(Halide::Target::Feature::NoBoundsQuery);
features.push_back(Halide::Target::Feature::NoRuntime);    
//features.push_back(Halide::Target::RVV);
//features.push_back(Halide::Target::Debug);
target.set_features(features);

If I do not set Halide::Target::vector_bits and add Halide::Target::RVV to target features, I get

Error: No vector_bits was specified for RISCV codegen; this is almost certainly a mistake. You should add -rvv-vector_bits_N to your Target string, where N is the SIMD width in bits (e.g. 128).

originating from CodeGen_RISCV.cpp

If I set Halide::Target::vector_bits to 128, and add Halide::Target::RVV to target features, then the cross-compilation passes, but that is not what I need as that's not what my platform can execute.

I tried digging around regarding this topic but to no avail. Is it really not possible (at least with no major messing around) to cross-compile a kernel to RISC-V platform without RVV support? Right now, I simply don't need that support, as we are primarily testing the feasibility of writing kernels for our hardware in Halide. We are not yet exploring scheduling and/or other features.

It might be important to mention that this approach works on this particular platform for relatively simple kernels for which RVV instructions are not emitted. Sorry if I missed something obvious, of which I still think there is a non-insignificant probability 😄

[abadams]

Reading the code, this looks unintentional on our part because the vector extension is an explicit feature that you need to turn on, but the assert you're hitting is always going to fail if it's not turned on. Are you compiling Halide yourself? If so, can you try just removing that assertion in CodeGen_RISCV.cpp line 143?

[bpervan]

So far I have mostly been using precompiled libraries. Your suggestion of removing the assertion and rebuilding Halide from scratch crossed my mind, but to be frank, I assumed that things would then start breaking apart elsewhere. Now I will certainly give it a shot. Thanks for the suggestion, I will report the findings here.

[bpervan]

Tried, but now LLVM's verifyFunction on line 654 and verifyModule on line 589 fail, both in CodeGen_LLVM.cpp. This can also be bypassed by disabling the appropriate assertions, which results in a (technically) successful cross-compilation of the kernel without RVV instructions, but with wrong library behavior (works/executes but returns zeroes for my test case).

[abadams]

Ah well. Thanks for doing the experiment. It looks like there's some non-trivial work to be done to support risc-v without the vector extension.

[bpervan]

Any time! Thanks for the suggestions. If you (or anyone else) have any other ideas, we would greatly appreciate them so that we can either close or keep open this research direction.