From ab23b18cdeae826ce7b552dfceeacafdf56ad433 Mon Sep 17 00:00:00 2001 From: memeka Date: Mon, 21 Oct 2019 10:58:47 +1030 Subject: [PATCH 001/133] ODROID-XU4: ARM: dma-mapping: increase DMA coherent pool size to 2M Change-Id: I8e3e7707ac182f3956f7415a80876b9d4c8ac771 --- arch/arm/mm/dma-mapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 27576c7b836ee6..09c51e5f345974 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -340,7 +340,7 @@ static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, pgprot_t prot, struct page **ret_page, const void *caller, bool want_vaddr); -#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K +#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M static struct gen_pool *atomic_pool __ro_after_init; static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; From a74c9e7a366c62703db8cb3c6eb879c89e48fbc8 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 4 Sep 2019 10:49:51 +0200 Subject: [PATCH 002/133] ODROID-XU4: soc: samsung: chipid: Make exynos_chipid_early_init() static Add missing static qualifier to the chipid initcall function. Change-Id: I3d0b4b5d7710fe69e23a94637f640dff736f3661 Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka --- drivers/soc/samsung/exynos-chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index c55a47cfe61751..25562dd0b2069e 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -45,7 +45,7 @@ static const char * __init product_id_to_soc_id(unsigned int product_id) return NULL; } -int __init exynos_chipid_early_init(void) +static int __init exynos_chipid_early_init(void) { struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; From a82e01e09d08e2174df6e8b02e960caeeedc26b1 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 28 Aug 2019 14:10:04 +0200 Subject: [PATCH 003/133] ODROID-XU4: ARM: dts: exynos: Add support ARM architected timers on Exynos5 All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Change-Id: I87807b0bcd63d6d98f9765fd4cb9663ab5d221e9 Signed-off-by: Marek Szyprowski Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Signed-off-by: memeka --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++++ arch/arm/boot/dts/exynos54xx.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 9eb48cabcca450..2bcbdf8a39bf51 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -1065,6 +1065,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 9c3b63b7cac6c5..02d34957cd836d 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -45,6 +45,15 @@ status = "disabled"; }; + timer: timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 4398f2d1fe8817..60ca3d68524786 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -1034,6 +1034,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; }; From c58558293fe1851fccb44a3dc300530770b8ccaf Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 19 Jul 2019 11:27:34 +0200 Subject: [PATCH 004/133] ODROID-XU4: phy: exynos5-usbdrd: Calibrating makes sense only for USB2.0 PHY PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY. Fixes: d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800") Change-Id: Ic3aaf6e70648e1a0a8177d3501f64c0ecfff2951 Signed-off-by: Marek Szyprowski Signed-off-by: memeka --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index e510732afb8b0a..7f6279fb4f8fa4 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -714,7 +714,9 @@ static int exynos5_usbdrd_phy_calibrate(struct phy *phy) struct phy_usb_instance *inst = phy_get_drvdata(phy); struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); - return exynos5420_usbdrd_phy_calibrate(phy_drd); + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) + return exynos5420_usbdrd_phy_calibrate(phy_drd); + return 0; } static const struct phy_ops exynos5_usbdrd_phy_ops = { From b6e5819f7e143f57022ae1bf7739b4b2075dfb30 Mon Sep 17 00:00:00 2001 From: Brian Kim Date: Thu, 5 Jan 2017 19:05:44 +0900 Subject: [PATCH 005/133] ODROID-XU4: drm/exynos/hdmi: add 'HPD' and 'vout' as boot parameters Change-Id: Ia3c94b0ee99e761a774ac63398ca86477b703b8c Signed-off-by: Brian Kim Signed-off-by: memeka Signed-off-by: Dongjin Kim Signed-off-by: memeka --- drivers/gpu/drm/exynos/exynos_hdmi.c | 39 +++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 09aa73c0f2adda..f1359a04fa31ec 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -143,6 +143,33 @@ struct hdmi_context { bool powered; }; +static bool gdvi_mode = false; +static bool gEnableHPD = true; + +static int __init dvi_force_enable(char *str) +{ + if (!strcmp(str, "dvi")) { + gdvi_mode = true; + pr_info("hdmi: using DVI mode\n"); + } else { + gdvi_mode = false; + pr_info("hdmi: using HDMI mode\n"); + } + + return 0; +} +__setup("vout=", dvi_force_enable); + +static int __init hdmi_hpd_enable(char *str) +{ + if (!strcmp(str, "false")) { + gEnableHPD = false; + } + + return 0; +} +__setup("HPD=", hdmi_hpd_enable); + static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) { return container_of(e, struct hdmi_context, encoder); @@ -843,6 +870,9 @@ static enum drm_connector_status hdmi_detect(struct drm_connector *connector, { struct hdmi_context *hdata = connector_to_hdmi(connector); + if (!gEnableHPD) + return connector_status_connected; + if (gpiod_get_value(hdata->hpd_gpio)) return connector_status_connected; @@ -882,7 +912,10 @@ static int hdmi_get_modes(struct drm_connector *connector) if (!edid) return -ENODEV; - hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); + if (gdvi_mode) + hdata->dvi_mode = true; + else + hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n", (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), edid->width_cm, edid->height_cm); @@ -1580,6 +1613,9 @@ static int hdmi_audio_hw_params(struct device *dev, void *data, { struct hdmi_context *hdata = dev_get_drvdata(dev); + if (hdata->dvi_mode) + return 0; + if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv || daifmt->frame_clk_inv || daifmt->bit_clk_master || daifmt->frame_clk_master) { @@ -1966,6 +2002,7 @@ static int hdmi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, hdata); hdata->dev = dev; + hdata->dvi_mode = gdvi_mode; mutex_init(&hdata->mutex); From 860fcf78870a0d279f6a5188fa808288463663ae Mon Sep 17 00:00:00 2001 From: "Mauro (mdrjr) Ribeiro" Date: Sun, 1 Jan 2017 13:23:58 -0200 Subject: [PATCH 006/133] ODROID-XU4: drm/exynos: add new HDMI PHY pll and resolutions + pre-build EDIDs - 480x800 60hz - 848x480 60hz - 1024x600 60hz (the old one is 1024x600p43hz) - 1152x864 75hz - 1280x768 60hz - 1400x1050 60hz - 1792x1344 60hz - 1920x800 60hz - 1920x1080 24Hz - 1920x1080 23.976Hz - 1920x1200 60hz - support for Vu5A - support for Vu7A+ new file: firmware/edid/480x800.bin new file: firmware/edid/640x480.bin new file: firmware/edid/720x480.bin new file: firmware/edid/720x576.bin new file: firmware/edid/800x480.bin new file: firmware/edid/800x600.bin new file: firmware/edid/848x480.bin new file: firmware/edid/1024x600.bin new file: firmware/edid/1024x768.bin new file: firmware/edid/1152x864_75hz.bin new file: firmware/edid/1280x1024.bin new file: firmware/edid/1280x720.bin new file: firmware/edid/1280x768.bin new file: firmware/edid/1280x800.bin new file: firmware/edid/1360x768.bin new file: firmware/edid/1366x768.bin new file: firmware/edid/1400x1050.bin new file: firmware/edid/1440x900.bin new file: firmware/edid/1600x1200.bin new file: firmware/edid/1600x900.bin new file: firmware/edid/1680x1050.bin new file: firmware/edid/1792x1344.bin new file: firmware/edid/1920x1080.bin new file: firmware/edid/1920x1080_23_976hz.bin new file: firmware/edid/1920x1080_24hz.bin new file: firmware/edid/1920x1080_50hz.bin new file: firmware/edid/1920x1200_30hz.bin new file: firmware/edid/1920x1200_60hz.bin new file: firmware/edid/1920x800.bin To support Vu5A, a pixel clock, 33.9MHz is needed. But, there is no exact hdmi phy table of exynos5422, so the cloest table will be used as a workaround. - Vu5A timing Detailed mode: Clock 33.900 MHz, 476 mm x 268 mm 800 844 932 1056 hborder 0 480 483 489 535 vborder 0 +hsync +vsync To support Vu7A+, a pixel clock, 49MHz is needed. But there is no exact hdmi phy table of exynos5422, so the closest table of 50.04MHz will be used as a workaround. - Vu7A+ timing Detailed mode (1) : Clock 49 MHz, 255 mm x 255 mm 1024 1029 1042 1312 hborder 0 600 602 605 622 vborder 0 -hsync +vsync - 1024x600 60hz timing Detailed mode: Clock 50.400 MHz, 355 mm x 208 mm 1024 1048 1184 1344 hborder 0 600 601 604 625 vborder 0 -hsync +vsync Change-Id: I1278be0ef8812d709429f02f1738c73033e2d5a0 Signed-off-by: memeka --- drivers/gpu/drm/exynos/exynos_hdmi.c | 192 ++++++++++++++++++++++++++- firmware/edid/1024x600.bin | Bin 0 -> 128 bytes firmware/edid/1024x768.bin | Bin 0 -> 128 bytes firmware/edid/1152x864_75hz.bin | Bin 0 -> 128 bytes firmware/edid/1280x1024.bin | Bin 0 -> 128 bytes firmware/edid/1280x720.bin | Bin 0 -> 128 bytes firmware/edid/1280x768.bin | Bin 0 -> 128 bytes firmware/edid/1280x800.bin | Bin 0 -> 128 bytes firmware/edid/1360x768.bin | Bin 0 -> 128 bytes firmware/edid/1366x768.bin | Bin 0 -> 128 bytes firmware/edid/1400x1050.bin | Bin 0 -> 128 bytes firmware/edid/1440x900.bin | Bin 0 -> 128 bytes firmware/edid/1600x1200.bin | Bin 0 -> 128 bytes firmware/edid/1600x900.bin | Bin 0 -> 128 bytes firmware/edid/1680x1050.bin | Bin 0 -> 128 bytes firmware/edid/1792x1344.bin | Bin 0 -> 128 bytes firmware/edid/1920x1080.bin | Bin 0 -> 128 bytes firmware/edid/1920x1080_23_976hz.bin | Bin 0 -> 128 bytes firmware/edid/1920x1080_24hz.bin | Bin 0 -> 128 bytes firmware/edid/1920x1080_50hz.bin | Bin 0 -> 128 bytes firmware/edid/1920x1200_30hz.bin | Bin 0 -> 128 bytes firmware/edid/1920x1200_60hz.bin | Bin 0 -> 128 bytes firmware/edid/1920x800.bin | Bin 0 -> 128 bytes firmware/edid/480x800.bin | Bin 0 -> 128 bytes firmware/edid/640x480.bin | Bin 0 -> 128 bytes firmware/edid/720x480.bin | Bin 0 -> 128 bytes firmware/edid/720x576.bin | Bin 0 -> 128 bytes firmware/edid/800x480.bin | Bin 0 -> 128 bytes firmware/edid/800x600.bin | Bin 0 -> 128 bytes firmware/edid/848x480.bin | Bin 0 -> 128 bytes 30 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 firmware/edid/1024x600.bin create mode 100644 firmware/edid/1024x768.bin create mode 100644 firmware/edid/1152x864_75hz.bin create mode 100644 firmware/edid/1280x1024.bin create mode 100644 firmware/edid/1280x720.bin create mode 100644 firmware/edid/1280x768.bin create mode 100644 firmware/edid/1280x800.bin create mode 100644 firmware/edid/1360x768.bin create mode 100644 firmware/edid/1366x768.bin create mode 100644 firmware/edid/1400x1050.bin create mode 100644 firmware/edid/1440x900.bin create mode 100644 firmware/edid/1600x1200.bin create mode 100644 firmware/edid/1600x900.bin create mode 100644 firmware/edid/1680x1050.bin create mode 100644 firmware/edid/1792x1344.bin create mode 100644 firmware/edid/1920x1080.bin create mode 100644 firmware/edid/1920x1080_23_976hz.bin create mode 100644 firmware/edid/1920x1080_24hz.bin create mode 100644 firmware/edid/1920x1080_50hz.bin create mode 100644 firmware/edid/1920x1200_30hz.bin create mode 100644 firmware/edid/1920x1200_60hz.bin create mode 100644 firmware/edid/1920x800.bin create mode 100644 firmware/edid/480x800.bin create mode 100644 firmware/edid/640x480.bin create mode 100644 firmware/edid/720x480.bin create mode 100644 firmware/edid/720x576.bin create mode 100644 firmware/edid/800x480.bin create mode 100644 firmware/edid/800x600.bin create mode 100644 firmware/edid/848x480.bin diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index f1359a04fa31ec..f2e1a0d2641c03 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -421,6 +421,38 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 31490000, + .conf = { + 0x01, 0xD1, 0x34, 0x74, 0x44, 0x3C, 0x3A, 0xC2, + 0x81, 0xE8, 0x3B, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xC3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 32000000, + .conf = { + 0x01, 0x51, 0x28, 0x55, 0x44, 0x40, 0x00, 0xC8, + 0x02, 0xC8, 0xF0, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x80, 0x25, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + /* + * To support Vu5A, pixel clock 33.9MHz is needed + * but we don't have the exact HDMI PHY table + * so as a workaround, the closest table will be used. + */ + { + .pixel_clock = 33900000, + .conf = { + 0x01, 0x51, 0x28, 0x55, 0x44, 0x40, 0x00, 0xC8, + 0x02, 0xC8, 0xF0, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x80, 0x25, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 36000000, .conf = { @@ -439,6 +471,29 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, }, }, + /* + * To support Vu7A+, pixel clock 49MHz is needed + * but we don't have the exact HDMI PHY table + * so as a workaround, the closest table will be used. + */ + { + .pixel_clock = 49000000, + .conf = { + 0x01, 0x51, 0x2A, 0x32, 0x42, 0x30, 0x00, 0xC4, + 0x83, 0xE8, 0xFC, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x7A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 50400000, + .conf = { + 0x01, 0x51, 0x2A, 0x32, 0x42, 0x30, 0x00, 0xC4, + 0x83, 0xE8, 0xFC, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x7A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 65000000, .conf = { @@ -467,7 +522,7 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { }, }, { - .pixel_clock = 74176000, + .pixel_clock = 74170000, .conf = { 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, @@ -484,6 +539,15 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 80140000, + .conf = { + 0x01, 0xD1, 0x21, 0x11, 0x40, 0x3C, 0x2F, 0xC8, + 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x99, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 83500000, .conf = { @@ -493,6 +557,24 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 84750000, + .conf = { + 0x01, 0xD1, 0x23, 0x11, 0x40, 0x30, 0x1E, 0xC7, + 0x84, 0xE8, 0xD4, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x48, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 85860000, + .conf = { + 0x01, 0xD1, 0x24, 0x11, 0x40, 0x30, 0xD2, 0xC8, + 0x84, 0xE8, 0xD5, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x48, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 88750000, .conf = { @@ -502,6 +584,24 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 89750000, + .conf = { + 0x01, 0xD1, 0x25, 0x11, 0x40, 0x30, 0x26, 0xC9, + 0x83, 0xE8, 0xE0, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x89, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 104990000, + .conf = { + 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x78, 0xC3, 0xC2, + 0x81, 0xE8, 0x06, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x3B, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 106500000, .conf = { @@ -511,6 +611,24 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 106560000, + .conf = { + 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x78, 0x73, 0xCA, + 0x85, 0xE8, 0x0B, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 107800000, + .conf = { + 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, + 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, + 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 108000000, .conf = { @@ -529,6 +647,33 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, }, }, + { + .pixel_clock = 119000000, + .conf = { + 0x01, 0xD1, 0x31, 0x14, 0x40, 0x78, 0x41, 0xCB, + 0x89, 0xE8, 0x28, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x68, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 122000000, + .conf = { + 0x01, 0xD1, 0x33, 0x14, 0x40, 0x30, 0xF0, 0xC8, + 0x85, 0xE8, 0x31, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x65, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 125590000, + .conf = { + 0x01, 0xD1, 0x34, 0x14, 0x40, 0x78, 0x4F, 0xC2, + 0x81, 0xE8, 0x3A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x87, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, { .pixel_clock = 146250000, .conf = { @@ -547,6 +692,51 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = { 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, }, }, + { + .pixel_clock = 154000000, + .conf = { + 0x01, 0xD1, 0x20, 0x01, 0x40, 0x30, 0x08, 0xCC, + 0x8C, 0xE8, 0xC1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x3F, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 162000000, + .conf = { + 0x01, 0xD1, 0x22, 0x01, 0x40, 0x30, 0xD4, 0xCD, + 0x89, 0xE8, 0xC9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x31, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 164100000, + .conf = { + 0x01, 0xD1, 0x22, 0x89, 0x49, 0xB0, 0x15, 0xCE, + 0x8A, 0xF8, 0xCD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x2B, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 196900000, + .conf = { + 0x01, 0xD1, 0x29, 0x1618, 0x418, 0x190, 0xF5, 0xCF, + 0x8D, 0x168, 0xF5, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xFA, 0x24, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 204800000, + .conf = { + 0x01, 0xD1, 0x2B, 0x02, 0x40, 0x30, 0xE0, 0xC8, + 0x85, 0xE8, 0x00, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x3C, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, }; static const struct hdmiphy_config hdmiphy_5433_configs[] = { diff --git a/firmware/edid/1024x600.bin b/firmware/edid/1024x600.bin new file mode 100644 index 0000000000000000000000000000000000000000..fd22361c4a86c3ea6150b4a91ed5f6dead8f1946 GIT binary patch literal 128 zcmZSh4+ad1ISgRHBhAR1t1MFSD(=9NNUs^H3IQQN@x%j+C}4vygM(v)q=H0;FhlYM y0R{#cprZc_KACx?6$;7*Tnaz{6#2_wZL6Zj#sKDnMgA}t8W@>Wm>EFTgaH6No*V%H literal 0 HcmV?d00001 diff --git a/firmware/edid/1024x768.bin b/firmware/edid/1024x768.bin new file mode 100644 index 0000000000000000000000000000000000000000..bae478cead8bc655c2a5d9531b630cb666acf111 GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S6Qm!RosCkkzO-Y6#_ySI2aNg7*RlqB!hz^gPH-y1T%(Y wE{t0Sq=A0RR91 literal 0 HcmV?d00001 diff --git a/firmware/edid/1152x864_75hz.bin b/firmware/edid/1152x864_75hz.bin new file mode 100644 index 0000000000000000000000000000000000000000..49c9110d7ab3efed4cf471e395b3efdd09a85c2a GIT binary patch literal 128 zcmZSh4+ad1ISgRHBhAR1t07nMD(=9NNUs^H3IQQN@j`z_6u_+6Fu^fF&A_8Um|=pB yAOnL8P|<$|pUk|{3I$~YE(IU}iu`5p@^NzEW&rcSB7YbR4NZ+IEX+(GYP10}xEuih literal 0 HcmV?d00001 diff --git a/firmware/edid/1280x1024.bin b/firmware/edid/1280x1024.bin new file mode 100644 index 0000000000000000000000000000000000000000..b4d16341a27e753641ca62e9a6cc16055656545d GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S4X+xRosCkkzO-Y6#_zl;*AZAD8N9AVMZW>mV-foFvFf? xK?VjnprZc_KACx?6$;7*Tnaz{6#2_wZENSi%>d?uMgBn51V^|#0!0}X004Dp9svLV literal 0 HcmV?d00001 diff --git a/firmware/edid/1280x720.bin b/firmware/edid/1280x720.bin new file mode 100644 index 0000000000000000000000000000000000000000..1631cd184db9b3832c6052b413484af5ec1c49dc GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S5c_qRosCkkzO-Y6#_zl;*AFwQGqN&L*NA&1&0Px2H)KR t3=DEWMgJLmGV@9+6qF6P6o3FI@|VHdR$G^Y0n7)B{DG?RaDk|q0sxkz9svLV literal 0 HcmV?d00001 diff --git a/firmware/edid/1280x768.bin b/firmware/edid/1280x768.bin new file mode 100644 index 0000000000000000000000000000000000000000..139191261c6418418dfac28f8602678e2ac8c8bc GIT binary patch literal 128 zcmZSh4+ad1ISgRHBhAR1t0+?OD(=9NNUs^H3IQQN@x}v;D8NsiVL~8-w1Gp1FoW+2 z0R{#cprZc_KACx?6$;7*Tnaz{6#2_wZL4R%$pGeqMgA}t8d(@rn44KZ)HnbDJRuwb literal 0 HcmV?d00001 diff --git a/firmware/edid/1280x800.bin b/firmware/edid/1280x800.bin new file mode 100644 index 0000000000000000000000000000000000000000..d7c59430b572232172a33b657680bd158cc4b4f2 GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S5c(mRosCkkzO-Y6#_zl;*AFwQNSK)h6Mo%;syo^W(>X; u1Q;0PfQtSz_+;jlRwyVNa47%*P~2LqT77Wo5JJi~M0QG&VD literal 0 HcmV?d00001 diff --git a/firmware/edid/1400x1050.bin b/firmware/edid/1400x1050.bin new file mode 100644 index 0000000000000000000000000000000000000000..61627d0669ebfb7775efc361c6ac2762896f4c9c GIT binary patch literal 128 zcmZSh4+ad1ISgRHBhAR1t0G^?RosCkkzO-Y6#_zl;!_VWqJY&(3l;>lNEsL?m@$;U u5@2AE11kE@;FFnGTA`q9z@-2LK#{);*0yFAoD5(-SmX~>jfV?FjT->;P9FgP literal 0 HcmV?d00001 diff --git a/firmware/edid/1600x1200.bin b/firmware/edid/1600x1200.bin new file mode 100644 index 0000000000000000000000000000000000000000..369fc35a6464431d3c02fadf1a83c62775e16161 GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952*IcvWRosCkkzO-Y6#_zl;wv2(QNR;B2ZN*yS`HZ-gc-CK zC^9g}02Tdb@X5?8tx!-l;8FkrpvYeaYge y1sNFRfQtSz_+;jlRwyVNa47%*P~F9Vnl7Wuv} literal 0 HcmV?d00001 diff --git a/firmware/edid/480x800.bin b/firmware/edid/480x800.bin new file mode 100644 index 0000000000000000000000000000000000000000..87f7e8f7fcaa1b4c0f42925d842cad4484081edf GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S3tVrRosCkkzO-Y6#_zl;}k+%M8mz z85tNPfQtSz_+;jlRwyVNa47%*P~%B7WuVyLYKk=T>$~R`3%37 u0ToC9@qY%N%)HVH1!V&+1t0*5{AIAVl~Z750Q12jf1qk2+#NxJ42uE3+8+S` literal 0 HcmV?d00001 diff --git a/firmware/edid/720x576.bin b/firmware/edid/720x576.bin new file mode 100644 index 0000000000000000000000000000000000000000..9c6cb38a752e7077a9b8790a976f9f4cbd5e5ac2 GIT binary patch literal 128 zcmZSh4+ac|HyFTxRg952S5lVy!UP2eE(IQ+P=;S8 ufC?ml_&y8Li~NDAiEwuW2{L#A08mIB0RR91 literal 0 HcmV?d00001 diff --git a/firmware/edid/848x480.bin b/firmware/edid/848x480.bin new file mode 100644 index 0000000000000000000000000000000000000000..48cea801e011a53ca12ceaceffe58e59352b3661 GIT binary patch literal 128 zcmZSh4+ad1ISgRHBhAR1D=Sd(D(=9NNUs^H3IQQNaqk0+D8QE|;DW&eK>>jXVFtBj z0t^f?Kt=x Date: Sun, 9 Apr 2017 17:31:25 +0000 Subject: [PATCH 007/133] ODROID-XU4: drm/exynos/mixer: never blend the base layer On Exynos there is a solid color plane that is logically below all the other display planes. This causes display artifacts due to alpha. The patch disables blending the base plane with the solid color plane (no alpha). Change-Id: Ibb2ada1d7a7be156d2f05ed477ee5972d63edd98 Reviewed-by: memeka Signed-off-by: memeka --- drivers/gpu/drm/exynos/exynos_mixer.c | 33 +++++++++++++++------------ 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 7b24338fad3c8c..609235e145bd75 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -314,23 +314,26 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, u32 val; val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ - switch (pixel_alpha) { - case DRM_MODE_BLEND_PIXEL_NONE: - break; - case DRM_MODE_BLEND_COVERAGE: - val |= MXR_GRP_CFG_PIXEL_BLEND_EN; - break; - case DRM_MODE_BLEND_PREMULTI: - default: - val |= MXR_GRP_CFG_BLEND_PRE_MUL; - val |= MXR_GRP_CFG_PIXEL_BLEND_EN; - break; - } + if (win) { + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + val |= MXR_GRP_CFG_PIXEL_BLEND_EN; + break; + case DRM_MODE_BLEND_PREMULTI: + default: + val |= MXR_GRP_CFG_BLEND_PRE_MUL; + val |= MXR_GRP_CFG_PIXEL_BLEND_EN; + break; + } - if (alpha != DRM_BLEND_ALPHA_OPAQUE) { - val |= MXR_GRP_CFG_WIN_BLEND_EN; - val |= win_alpha; + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val |= MXR_GRP_CFG_WIN_BLEND_EN; + val |= win_alpha; + } } + mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), val, MXR_GRP_CFG_MISC_MASK); } From a19ce3b6291a02d8a37f2bac22bf2754e32e9fcf Mon Sep 17 00:00:00 2001 From: memeka Date: Thu, 24 Jan 2019 16:07:24 +1030 Subject: [PATCH 008/133] ODROID-XU4: media: s5p-jpeg: Enable decoding with multiple buffers Change-Id: Ia83449849d4636baf57ed64d7183c2a9cec7fe22 Signed-off-by: memeka --- drivers/media/platform/s5p-jpeg/jpeg-core.c | 45 ++++++++++++++++----- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c index 8dbbd5f2a40a0f..b5e0105ae05f04 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c @@ -1798,6 +1798,31 @@ static int exynos3250_jpeg_try_crop(struct s5p_jpeg_ctx *ctx, * V4L2 controls */ +static int vidioc_decoder_cmd(struct file *file, void *priv, + struct v4l2_decoder_cmd *cmd) +{ + struct s5p_jpeg_ctx *ctx = fh_to_ctx(priv); + struct vb2_queue *vq_src = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + struct vb2_v4l2_buffer *buf; + + switch (cmd->cmd) { + case V4L2_DEC_CMD_STOP: + if (cmd->flags != 0) + return -EINVAL; + if (!vb2_is_streaming(vq_src)) + return -EINVAL; + + buf = v4l2_m2m_last_src_buf(ctx->fh.m2m_ctx); + buf->flags |= V4L2_BUF_FLAG_LAST; + + break; + default: + return -EINVAL; + } + + return 0; +} + static int s5p_jpeg_g_selection(struct file *file, void *priv, struct v4l2_selection *s) { @@ -1832,9 +1857,6 @@ static int s5p_jpeg_g_selection(struct file *file, void *priv, return 0; } -/* - * V4L2 controls - */ static int s5p_jpeg_s_selection(struct file *file, void *fh, struct v4l2_selection *s) { @@ -2026,6 +2048,8 @@ static const struct v4l2_ioctl_ops s5p_jpeg_ioctl_ops = { .vidioc_streamon = v4l2_m2m_ioctl_streamon, .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + .vidioc_decoder_cmd = vidioc_decoder_cmd, + .vidioc_g_selection = s5p_jpeg_g_selection, .vidioc_s_selection = s5p_jpeg_s_selection, @@ -2472,13 +2496,6 @@ static int s5p_jpeg_queue_setup(struct vb2_queue *vq, size = q_data->size; - /* - * header is parsed during decoding and parsed information stored - * in the context so we do not allow another buffer to overwrite it - */ - if (ctx->mode == S5P_JPEG_DECODE) - count = 1; - *nbuffers = count; *nplanes = 1; sizes[0] = size; @@ -2589,6 +2606,7 @@ static int s5p_jpeg_start_streaming(struct vb2_queue *q, unsigned int count) static void s5p_jpeg_stop_streaming(struct vb2_queue *q) { struct s5p_jpeg_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *buf; /* * STREAMOFF is an acknowledgment for resolution change event. @@ -2601,6 +2619,11 @@ static void s5p_jpeg_stop_streaming(struct vb2_queue *q) ctx->state = JPEGCTX_RUNNING; } + while ((buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx))) + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + while ((buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx))) + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + pm_runtime_put(ctx->jpeg->dev); } @@ -2840,6 +2863,8 @@ static irqreturn_t exynos3250_jpeg_irq(int irq, void *dev_id) v4l2_m2m_buf_done(src_buf, state); if (curr_ctx->mode == S5P_JPEG_ENCODE) vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload_size); + if (src_buf->flags & V4L2_BUF_FLAG_LAST) + dst_buf->flags |= V4L2_BUF_FLAG_LAST; v4l2_m2m_buf_done(dst_buf, state); curr_ctx->subsampling = From 231071577877b5dacb9bb3eb5e48cbcf1681689a Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 10 Jul 2018 11:24:56 +0930 Subject: [PATCH 009/133] ODROID-XU4: media: exynos-gsc: fix v4l2 SELECTION api Change-Id: Ida63e217cd989d661b7620d390515c0ffcb830ac Signed-off-by: memeka --- drivers/media/platform/exynos-gsc/gsc-core.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/exynos-gsc/gsc-core.h b/drivers/media/platform/exynos-gsc/gsc-core.h index 8e5a9acb78aad4..235d687614f025 100644 --- a/drivers/media/platform/exynos-gsc/gsc-core.h +++ b/drivers/media/platform/exynos-gsc/gsc-core.h @@ -474,9 +474,9 @@ static inline struct gsc_frame *ctx_get_frame(struct gsc_ctx *ctx, { struct gsc_frame *frame; - if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { + if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type || V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { frame = &ctx->s_frame; - } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { + } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type || V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { frame = &ctx->d_frame; } else { pr_err("Wrong buffer/video queue type (%d)", type); From 79d5eaa79e078248ac780f09a1acf721ec0691db Mon Sep 17 00:00:00 2001 From: Thierry Escande Date: Wed, 26 Oct 2016 10:52:05 +0200 Subject: [PATCH 010/133] ODROID-XU4: videobuf2-dc: Move vb2_dc_get_base_sgt() above mmap callbacks This patch moves vb2_dc_get_base_sgt() function above mmap buffers callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it will be called for cacheable MMAP support introduced in the next patch. Change-Id: Ia504fbc1f0b3741986e8fff1ad329215b6e2db2e Signed-off-by: Thierry Escande Signed-off-by: memeka --- .../common/videobuf2/videobuf2-dma-contig.c | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c index 44cd0e530bbd30..b525c63a5501af 100644 --- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c +++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c @@ -62,6 +62,28 @@ static unsigned long vb2_dc_get_contiguous_size(struct sg_table *sgt) return size; } +static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf) +{ + int ret; + struct sg_table *sgt; + + sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) { + dev_err(buf->dev, "failed to alloc sg table\n"); + return NULL; + } + + ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr, + buf->size, buf->attrs); + if (ret < 0) { + dev_err(buf->dev, "failed to get scatterlist from DMA API\n"); + kfree(sgt); + return NULL; + } + + return sgt; +} + /*********************************************/ /* callbacks for all buffers */ /*********************************************/ @@ -366,28 +388,6 @@ static const struct dma_buf_ops vb2_dc_dmabuf_ops = { .release = vb2_dc_dmabuf_ops_release, }; -static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf) -{ - int ret; - struct sg_table *sgt; - - sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); - if (!sgt) { - dev_err(buf->dev, "failed to alloc sg table\n"); - return NULL; - } - - ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr, - buf->size, buf->attrs); - if (ret < 0) { - dev_err(buf->dev, "failed to get scatterlist from DMA API\n"); - kfree(sgt); - return NULL; - } - - return sgt; -} - static struct dma_buf *vb2_dc_get_dmabuf(void *buf_priv, unsigned long flags) { struct vb2_dc_buf *buf = buf_priv; From 303d1da722956d2fc156d74257262098a8334189 Mon Sep 17 00:00:00 2001 From: Heng-Ruey Hsu Date: Wed, 26 Oct 2016 10:52:06 +0200 Subject: [PATCH 011/133] ODROID-XU4: videobuf2-dc: Support cacheable MMAP DMA allocations for MMAP type are uncached by default. But for some cases, CPU has to access the buffers. ie: memcpy for format converter. Supporting cacheable MMAP improves huge performance. This patch enables cacheable memory for DMA coherent allocator in mmap buffer allocation if non-consistent DMA attribute is set and kernel mapping is present. Even if userspace doesn't mmap the buffer, sync still should be happening if kernel mapping is present. If not done in allocation, it is enabled when memory is mapped from userspace (if non-consistent DMA attribute is set). Change-Id: I1e8e65086a2e4511563e8e7c3748d3b5403f18c3 Signed-off-by: Heng-Ruey Hsu Tested-by: Heng-ruey Hsu Reviewed-by: Tomasz Figa Signed-off-by: Thierry Escande Signed-off-by: memeka --- .../common/videobuf2/videobuf2-dma-contig.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c index b525c63a5501af..aafa499a53a85f 100644 --- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c +++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c @@ -152,6 +152,10 @@ static void vb2_dc_put(void *buf_priv) sg_free_table(buf->sgt_base); kfree(buf->sgt_base); } + if (buf->dma_sgt) { + sg_free_table(buf->dma_sgt); + kfree(buf->dma_sgt); + } dma_free_attrs(buf->dev, buf->size, buf->cookie, buf->dma_addr, buf->attrs); put_device(buf->dev); @@ -193,6 +197,14 @@ static void *vb2_dc_alloc(struct device *dev, unsigned long attrs, buf->handler.put = vb2_dc_put; buf->handler.arg = buf; + /* + * Enable cache maintenance. Even if userspace doesn't mmap the buffer, + * sync still should be happening if kernel mapping is present. + */ + if (!(buf->attrs & DMA_ATTR_NO_KERNEL_MAPPING) && + buf->attrs & DMA_ATTR_NON_CONSISTENT) + buf->dma_sgt = vb2_dc_get_base_sgt(buf); + refcount_set(&buf->refcount, 1); return buf; @@ -222,6 +234,10 @@ static int vb2_dc_mmap(void *buf_priv, struct vm_area_struct *vma) vma->vm_ops->open(vma); + /* Enable cache maintenance if not enabled in allocation. */ + if (!buf->dma_sgt && buf->attrs & DMA_ATTR_NON_CONSISTENT) + buf->dma_sgt = vb2_dc_get_base_sgt(buf); + pr_debug("%s: mapped dma addr 0x%08lx at 0x%08lx, size %ld\n", __func__, (unsigned long)buf->dma_addr, vma->vm_start, buf->size); From e5f91a97687e01535ca43b1e434ebcb82d51064a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 15 Feb 2017 14:08:49 +0100 Subject: [PATCH 012/133] ODROID-XU4: ARM: dma-mapping: add support for non-consistent dma_mmap Change-Id: I6b574d2a73ed0cda41e19f1e4982828f8f591177 Signed-off-by: Marek Szyprowski Signed-off-by: memeka --- arch/arm/mm/dma-mapping.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 09c51e5f345974..39f3d5e795d277 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -593,7 +593,8 @@ static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot) { prot = (attrs & DMA_ATTR_WRITE_COMBINE) ? pgprot_writecombine(prot) : - pgprot_dmacoherent(prot); + (attrs & DMA_ATTR_NON_CONSISTENT) ? + prot : pgprot_dmacoherent(prot); return prot; } From 831c9043c6726dc02cd72adb0123164f7c35fc6a Mon Sep 17 00:00:00 2001 From: memeka Date: Mon, 30 Oct 2017 09:31:09 +1030 Subject: [PATCH 013/133] ODROID-XU4: media: s5p-mfc: use cacheable DMA buffers to improve performance Change-Id: I2054a87278e545515be927ddcc52f52991224a6e Signed-off-by: memeka --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index b776f83e395e00..b4a2b2da675112 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -858,7 +858,7 @@ static int s5p_mfc_open(struct file *file) * We'll do mostly sequential access, so sacrifice TLB efficiency for * faster allocation. */ - q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; + q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | DMA_ATTR_NON_CONSISTENT | DMA_ATTR_NO_KERNEL_MAPPING; q->mem_ops = &vb2_dma_contig_memops; q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); @@ -893,7 +893,7 @@ static int s5p_mfc_open(struct file *file) * We'll do mostly sequential access, so sacrifice TLB efficiency for * faster allocation. */ - q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; + q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | DMA_ATTR_NON_CONSISTENT | DMA_ATTR_NO_KERNEL_MAPPING; q->mem_ops = &vb2_dma_contig_memops; q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); From 8f0da09def433788d92801871b5b7e7f17b9afaf Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 10 Jul 2018 22:01:38 +0930 Subject: [PATCH 014/133] ODROID-XU4: media: s5p-mfc: copy timestamp and timecode in encoder output Change-Id: Ic3a2f6eb94d60604df50976eca4e210898f40b32 Signed-off-by: memeka --- drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index 912fe0c5ab184e..d48e7b57d96a37 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -1208,6 +1208,7 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_buf *mb_entry; + struct s5p_mfc_buf *dst_buf; unsigned long enc_y_addr = 0, enc_c_addr = 0; unsigned long mb_y_addr, mb_c_addr; int slice_type; @@ -1227,8 +1228,12 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) &mb_entry->b->vb2_buf, 0); mb_c_addr = vb2_dma_contig_plane_dma_addr( &mb_entry->b->vb2_buf, 1); + dst_buf = list_entry(ctx->dst_queue.next, + struct s5p_mfc_buf, list); if ((enc_y_addr == mb_y_addr) && (enc_c_addr == mb_c_addr)) { + dst_buf->b->timecode = mb_entry->b->timecode; + dst_buf->b->vb2_buf.timestamp = mb_entry->b->vb2_buf.timestamp; list_del(&mb_entry->list); ctx->src_queue_cnt--; vb2_buffer_done(&mb_entry->b->vb2_buf, @@ -1241,8 +1246,12 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) &mb_entry->b->vb2_buf, 0); mb_c_addr = vb2_dma_contig_plane_dma_addr( &mb_entry->b->vb2_buf, 1); + dst_buf = list_entry(ctx->dst_queue.next, + struct s5p_mfc_buf, list); if ((enc_y_addr == mb_y_addr) && (enc_c_addr == mb_c_addr)) { + dst_buf->b->timecode = mb_entry->b->timecode; + dst_buf->b->vb2_buf.timestamp = mb_entry->b->vb2_buf.timestamp; list_del(&mb_entry->list); ctx->ref_queue_cnt--; vb2_buffer_done(&mb_entry->b->vb2_buf, From 85eafee9f0f7186358542cd1cde6198e29f63f7f Mon Sep 17 00:00:00 2001 From: OtherCrashOverride Date: Fri, 19 May 2017 12:59:51 +0000 Subject: [PATCH 015/133] ODROID-XU4: media: s5p-mfc: stop streaming before releasing queues If streaming is active when the MFC device is closed, it will generate an IOMMU page-fault. Change-Id: Ie5c664ecddaebedf282eae1d56e82821b5883ffd Signed-off-by: memeka --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index b4a2b2da675112..fe401d6764cc4f 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -941,6 +941,11 @@ static int s5p_mfc_release(struct file *file) mfc_debug_enter(); if (dev) mutex_lock(&dev->mfc_mutex); + + /* stop streaming */ + vb2_streamoff(&ctx->vq_src, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + vb2_streamoff(&ctx->vq_dst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + vb2_queue_release(&ctx->vq_src); vb2_queue_release(&ctx->vq_dst); if (dev) { From b08c0c162fab54c229a57e1edbcf2d0f7db3ea99 Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 15 Oct 2019 16:49:25 +1030 Subject: [PATCH 016/133] ODROID-XU4: clk: samsung: exynos5420: add VPLL rate table Add new table rate for VPLL for Exynos 542x SoC required to support Mali GPU clock frequencies. Change-Id: I71303661fe2f66840386028ef2a53f2242073eef --- drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 27fd274e92f87b..5dbddc5afca380 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1440,6 +1440,17 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = { + PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2), + PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2), + PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2), + PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2), + PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3), + PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3), + PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), +}; + static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), @@ -1564,6 +1575,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; } if (soc == EXYNOS5420) From e2023889544d048428e33cd4736e34dcc7215b1f Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 25 Oct 2019 11:34:35 +0200 Subject: [PATCH 017/133] ODROID-XU4: clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D, so the G3D MALI driver can simply adjust the rate of its clock by doing a single clk_set_rate() call, without the need to know the whole clock topology in Exynos542x SoCs. Change-Id: I0506b4cf9c5318ee8d16a5122a21e0bf8ad20e62 Suggested-by: Marian Mihailescu Signed-off-by: Marek Szyprowski Signed-off-by: memeka --- drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5dbddc5afca380..c9e5a1fb66539e 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -614,7 +614,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), - MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), + MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, SRC_TOP3, 0, 1), @@ -656,8 +657,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { SRC_TOP5, 8, 1), MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5, 12, 1), - MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, - SRC_TOP5, 16, 1), + MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, + SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, SRC_TOP5, 20, 1), MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", @@ -666,7 +667,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), - MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), + MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1, + CLK_SET_RATE_PARENT, 0), MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), @@ -710,7 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { SRC_TOP12, 8, 1), MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, SRC_TOP12, 12, 1), - MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), + MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", @@ -807,8 +810,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV_TOP2, 8, 3), DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), - DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, - 16, 3), + DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, + 16, 3, CLK_SET_RATE_PARENT, 0), DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", @@ -1256,7 +1259,8 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { }; static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, + CLK_SET_RATE_PARENT, 0), }; static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { From 689cdab60ab37b90825bddcea7a219d685dd7096 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 21 Nov 2019 11:11:45 +0100 Subject: [PATCH 018/133] ODROID-XU4: clk: samsung: exynos5420: Keep top G3D clocks enabled All top clocks on G3D path has to be enabled all the time to allow proper G3D power domain operation. This is achieved by adding CRITICAL flag to "mout_sw_aclk_g3d" clock, what keeps this clock and all its parents enabled. This fixes following imprecise abort issue observed on Odroid XU3/XU4 after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): panfrost 11800000.gpu: clock rate = 400000000 panfrost 11800000.gpu: failed to get regulator: -517 panfrost 11800000.gpu: regulator init failed -517 Power domain G3D disable failed ... panfrost 11800000.gpu: clock rate = 400000000 8<--- cut here --- Unhandled fault: imprecise external abort (0x1406) at 0x00000000 pgd = (ptrval) [00000000] *pgd=00000000 Internal error: : 1406 [#1] PREEMPT SMP ARM Modules linked in: CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events deferred_probe_work_func PC is at panfrost_gpu_soft_reset+0x94/0x110 LR is at ___might_sleep+0x128/0x2dc ... [] (panfrost_gpu_soft_reset) from [] (panfrost_gpu_init+0x10/0x67c) [] (panfrost_gpu_init) from [] (panfrost_device_init+0x158/0x2cc) [] (panfrost_device_init) from [] (panfrost_probe+0x80/0x178) [] (panfrost_probe) from [] (platform_drv_probe+0x48/0x9c) [] (platform_drv_probe) from [] (really_probe+0x1c4/0x474) [] (really_probe) from [] (driver_probe_device+0x78/0x1bc) [] (driver_probe_device) from [] (bus_for_each_drv+0x74/0xb8) [] (bus_for_each_drv) from [] (__device_attach+0xd4/0x16c) [] (__device_attach) from [] (bus_probe_device+0x88/0x90) [] (bus_probe_device) from [] (deferred_probe_work_func+0x4c/0xd0) [] (deferred_probe_work_func) from [] (process_one_work+0x300/0x864) [] (process_one_work) from [] (worker_thread+0x58/0x5a0) [] (worker_thread) from [] (kthread+0x12c/0x160) [] (kthread) from [] (ret_from_fork+0x14/0x20) Exception stack(0xee03dfb0 to 0xee03dff8) ... Code: e594300c e5933020 e3130c01 1a00000f (ebefff50). ---[ end trace badde2b74a65a540 ]--- In the above case, the Panfrost driver disables G3D clocks after failure of getting the needed regulator and return with -EPROVE_DEFER code. This causes G3D power domain disable failure and then, during second probe an imprecise abort is triggered due to undefined power domain state. Fixes: 45f10dabb56b ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path") Fixes: c9f7567aff31 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU") Signed-off-by: Marek Szyprowski Acked-by: Chanwoo Choi Change-Id: Ic999b9c06b43a3fa148ab254ccef518cecc99460 Signed-off-by: Marian Mihailescu --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c9e5a1fb66539e..bba0fe205c4eb2 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -713,7 +713,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, SRC_TOP12, 12, 1), MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1, - CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", From 38308205aeb411c23c57baf193c709b3851d6499 Mon Sep 17 00:00:00 2001 From: Marian Mihailescu Date: Thu, 14 Nov 2019 10:39:00 +1030 Subject: [PATCH 019/133] ODROID-XU4: ARM: dts: exynos5420: add mali dt node and enable mali on Odroid XU3/4 Add device tree node for Mali GPU for Exynos 542x SoC. GPU is disabled by default, and is enabled for each board after the regulator is defined. Tested on Odroid-XU4. Change-Id: I902932d29c7093b666fa3a8a8e1d0fda8fb11d5c Signed-off-by: Marian Mihailescu --- arch/arm/boot/dts/exynos5420.dtsi | 50 +++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 6 ++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 7d51e0f4ab79ad..8c354902c3f8e7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -670,6 +670,56 @@ iommus = <&sysmmu_gscl1>; }; + gpu: gpu@11800000 { + compatible = "samsung,exynos5420-mali", "arm,mali-t628"; + reg = <0x11800000 0x5000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&clock CLK_G3D>; + clock-names = "core"; + power-domains = <&g3d_pd>; + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + #cooling-cells = <2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = <812500>; + }; + opp-266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <862500>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <912500>; + }; + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <962500>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1000000>; + }; + opp-543000000 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <1037500>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1150000>; + }; + }; + }; + scaler_0: scaler@12800000 { compatible = "samsung,exynos5420-scaler"; reg = <0x12800000 0x1294>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 829147e320e081..f880aeccbacedf 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -522,7 +522,6 @@ regulator-name = "vdd_g3d"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { @@ -654,6 +653,11 @@ vtmu-supply = <&ldo7_reg>; }; +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; From 553eeab5a1b58a53a4ba8f41354ac42c870a560a Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 10 Jul 2018 22:13:03 +0930 Subject: [PATCH 020/133] ODROID-XU4: thermal: exynos: add support for 8 trip points on Exynos5422 TMU Change-Id: I6014d6d3fdecb6f58c6160f79ac969c6816f365d Signed-off-by: memeka --- drivers/thermal/samsung/exynos_tmu.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index fb2c55123a99ef..029f72f5c7d765 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -912,8 +912,6 @@ static int exynos_map_dt_data(struct platform_device *pdev) case SOC_ARCH_EXYNOS4412: case SOC_ARCH_EXYNOS5250: case SOC_ARCH_EXYNOS5260: - case SOC_ARCH_EXYNOS5420: - case SOC_ARCH_EXYNOS5420_TRIMINFO: data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; data->tmu_initialize = exynos4412_tmu_initialize; @@ -932,6 +930,22 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->min_efuse_value = 0; data->max_efuse_value = 100; break; + case SOC_ARCH_EXYNOS5420: + case SOC_ARCH_EXYNOS5420_TRIMINFO: + data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; + data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; + data->tmu_initialize = exynos4412_tmu_initialize; + data->tmu_control = exynos4210_tmu_control; + data->tmu_read = exynos4412_tmu_read; + data->tmu_set_emulation = exynos4412_tmu_set_emulation; + data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->ntrip = 8; + data->gain = 8; + data->reference_voltage = 16; + data->efuse_value = 55; + data->min_efuse_value = 16; + data->max_efuse_value = 76; + break; case SOC_ARCH_EXYNOS5433: data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; From 6fc99ddf7d0f82fa9bb45d3c76cf3e203ef1bb36 Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 22 Jan 2019 11:55:07 +1030 Subject: [PATCH 021/133] ODROID-XU4: arm: dts: exynos5422: enable Exynos5422 TMU Change-Id: I3fb73f0f9a2f349fc667354a607c50ffefa7084e Signed-off-by: memeka --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index f880aeccbacedf..ce774f7b2ce04c 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -635,22 +635,27 @@ &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; + status = "okay"; }; &tmu_cpu1 { vtmu-supply = <&ldo7_reg>; + status = "okay"; }; &tmu_cpu2 { vtmu-supply = <&ldo7_reg>; + status = "okay"; }; &tmu_cpu3 { vtmu-supply = <&ldo7_reg>; + status = "okay"; }; &tmu_gpu { vtmu-supply = <&ldo7_reg>; + status = "okay"; }; &gpu { From cfbb0fbe09b5a1b746a1e2494903f77290e8f6e6 Mon Sep 17 00:00:00 2001 From: memeka Date: Fri, 18 Oct 2019 15:54:55 +1030 Subject: [PATCH 022/133] ODROID-XU4: arm: dts: exynos: correct the cpu frequencies and voltages for Exynos5422 Odroid boards Change-Id: I7f6dfebc2842f671f91cc9eb239f92b6cb2a03f9 --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 16 +++--- .../boot/dts/exynos5422-odroidxu3-lite.dts | 9 ++++ arch/arm/boot/dts/exynos5800.dtsi | 54 ++++++++++++------- 3 files changed, 53 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index e4a5857c135f67..aea3893fed2487 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -26,7 +26,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; + clock-frequency = <1400000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -38,7 +38,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; + clock-frequency = <1400000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -50,7 +50,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; + clock-frequency = <1400000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -62,7 +62,7 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; + clock-frequency = <1400000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -74,7 +74,7 @@ compatible = "arm,cortex-a15"; reg = <0x0>; clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; + clock-frequency = <2000000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -86,7 +86,7 @@ compatible = "arm,cortex-a15"; reg = <0x1>; clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; + clock-frequency = <2000000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -98,7 +98,7 @@ compatible = "arm,cortex-a15"; reg = <0x2>; clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; + clock-frequency = <2000000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -110,7 +110,7 @@ compatible = "arm,cortex-a15"; reg = <0x3>; clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; + clock-frequency = <2000000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index c19b5a51ca4495..8082e3ce4228c4 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -18,6 +18,15 @@ compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; }; +&cluster_a15_opp_table { + /delete-node/opp-2000000000; + /delete-node/opp-1900000000; +}; + +&cluster_a7_opp_table { + /delete-node/opp-1400000000; +}; + &arm_a7_pmu { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index de639eecc5c913..da293b0ec4114a 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -21,35 +21,48 @@ }; &cluster_a15_opp_table { - opp-1700000000 { + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <1312500>; + clock-latency-ns = <140000>; + }; + opp-1900000000 { + opp-hz = /bits/64 <1900000000>; opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp-1800000000 { + opp-microvolt = <1200000>; + }; + opp-1700000000 { + opp-microvolt = <1162500>; }; opp-1600000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1125000>; }; opp-1500000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1087500>; }; opp-1400000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1062500>; }; opp-1300000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1050000>; }; opp-1200000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1050000>; }; opp-1100000000 { opp-microvolt = <1000000>; }; opp-1000000000 { - opp-microvolt = <1000000>; + opp-microvolt = <975000>; }; opp-900000000 { - opp-microvolt = <1000000>; + opp-microvolt = <950000>; }; opp-800000000 { - opp-microvolt = <900000>; + opp-microvolt = <925000>; }; opp-700000000 { opp-microvolt = <900000>; @@ -82,38 +95,43 @@ }; &cluster_a7_opp_table { + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; opp-1300000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1225000>; }; opp-1200000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1175000>; }; opp-1100000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1137500>; }; opp-1000000000 { opp-microvolt = <1100000>; }; opp-900000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1062500>; }; opp-800000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1025000>; }; opp-700000000 { - opp-microvolt = <1000000>; + opp-microvolt = <987500>; }; opp-600000000 { - opp-microvolt = <1000000>; + opp-microvolt = <950000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1000000>; + opp-microvolt = <900000>; clock-latency-ns = <140000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1000000>; + opp-microvolt = <900000>; clock-latency-ns = <140000>; }; opp-300000000 { From 0a5617332f4bd57f3e2c6fe58494510f5f3a0409 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 7 Nov 2018 18:09:44 +0100 Subject: [PATCH 023/133] ODROID-XU4: thermal: add irq-mode configuration for trip point This patch adds support irq mode in trip point. When that flag is set in DT, there is no need for polling in thermal framework. Crossing the trip point will rise an IRQ. The naming convention for tip point 'type' can be confussing and 'passive' (whic is passive cooling) might be interpretted wrongly. This mechanism prevents from missue and adds explicit setting for hardware which support interrupts for pre-configured temperature threshold. Change-Id: I2ee4c318bc74c07bfc3654ac9f3d6de4f2142088 Cc: Zhang Rui Cc: Eduardo Valentin Cc: Daniel Lezcano Signed-off-by: Lukasz Luba Signed-off-by: memeka --- drivers/thermal/of-thermal.c | 17 +++++++++++++++++ drivers/thermal/thermal_core.c | 10 ++++++++-- include/linux/thermal.h | 5 +++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index dc5093be553ec1..0ff966096475f1 100644 --- a/drivers/thermal/of-thermal.c +++ b/drivers/thermal/of-thermal.c @@ -315,6 +315,20 @@ static int of_thermal_get_trip_type(struct thermal_zone_device *tz, int trip, return 0; } +static int +of_thermal_get_trip_irq_mode(struct thermal_zone_device *tz, int trip, + bool *mode) +{ + struct __thermal_zone *data = tz->devdata; + + if (trip >= data->ntrips || trip < 0) + return -EDOM; + + *mode = data->trips[trip].irq_mode; + + return 0; +} + static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip, int *temp) { @@ -397,6 +411,7 @@ static struct thermal_zone_device_ops of_thermal_ops = { .set_mode = of_thermal_set_mode, .get_trip_type = of_thermal_get_trip_type, + .get_trip_irq_mode = of_thermal_get_trip_irq_mode, .get_trip_temp = of_thermal_get_trip_temp, .set_trip_temp = of_thermal_set_trip_temp, .get_trip_hyst = of_thermal_get_trip_hyst, @@ -830,6 +845,8 @@ static int thermal_of_populate_trip(struct device_node *np, return ret; } + trip->irq_mode = of_property_read_bool(np, "irq-mode"); + /* Required for cooling map matching */ trip->np = np; of_node_get(np); diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index c28271817e43f6..d26b2fe42fada1 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -412,6 +412,7 @@ static void handle_critical_trips(struct thermal_zone_device *tz, static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) { enum thermal_trip_type type; + bool irq_mode = false; /* Ignore disabled trip points */ if (test_bit(trip, &tz->trips_disabled)) @@ -425,9 +426,14 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) handle_non_critical_trips(tz, trip); /* * Alright, we handled this trip successfully. - * So, start monitoring again. + * So, start monitoring in polling mode if + * trip is not using irq HW support. */ - monitor_thermal_zone(tz); + if (tz->ops->get_trip_irq_mode) + tz->ops->get_trip_irq_mode(tz, trip, &irq_mode); + + if (!irq_mode) + monitor_thermal_zone(tz); } static void update_temperature(struct thermal_zone_device *tz) diff --git a/include/linux/thermal.h b/include/linux/thermal.h index e45659c7592096..39e18a2d7366cf 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -103,6 +103,7 @@ struct thermal_zone_device_ops { enum thermal_device_mode); int (*get_trip_type) (struct thermal_zone_device *, int, enum thermal_trip_type *); + int (*get_trip_irq_mode) (struct thermal_zone_device *, int, bool *); int (*get_trip_temp) (struct thermal_zone_device *, int, int *); int (*set_trip_temp) (struct thermal_zone_device *, int, int); int (*get_trip_hyst) (struct thermal_zone_device *, int, int *); @@ -196,6 +197,7 @@ struct thermal_zone_device { struct thermal_attr *trip_temp_attrs; struct thermal_attr *trip_type_attrs; struct thermal_attr *trip_hyst_attrs; + struct thermal_attr *trip_irq_mode_attrs; void *devdata; int trips; unsigned long trips_disabled; /* bitmap for disabled trips */ @@ -364,6 +366,8 @@ struct thermal_zone_of_device_ops { * @temperature: temperature value in miliCelsius * @hysteresis: relative hysteresis in miliCelsius * @type: trip point type + * @irq_mode: to not use polling in framework set support of HW irq (which will + * be triggered when temperature reaches this level). */ struct thermal_trip { @@ -371,6 +375,7 @@ struct thermal_trip { int temperature; int hysteresis; enum thermal_trip_type type; + bool irq_mode; }; /* Function declarations */ From c4b647bda1cb4419821a963ddb0974e91d2ff8d7 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 7 Nov 2018 18:09:45 +0100 Subject: [PATCH 024/133] ODROID-XU4: thermal: add new sysfs file for irq-mode Patch adds show functions for irq-mode feature. It allocates new attributes and extends the old list. Change-Id: I7966bfd783ac0abc78bb89c7ed5ee5fe61b2d1b9 Cc: Zhang Rui Cc: Eduardo Valentin Cc: Daniel Lezcano Signed-off-by: Lukasz Luba Signed-off-by: memeka --- drivers/thermal/thermal_sysfs.c | 53 +++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c index aa99edb4dff7dc..e3ede8af79cc91 100644 --- a/drivers/thermal/thermal_sysfs.c +++ b/drivers/thermal/thermal_sysfs.c @@ -21,6 +21,8 @@ #include "thermal_core.h" +#define TRIP_ATTR_NUM 4 + /* sys I/F for thermal zone */ static ssize_t @@ -166,6 +168,28 @@ trip_point_temp_show(struct device *dev, struct device_attribute *attr, return sprintf(buf, "%d\n", temperature); } +static ssize_t +trip_point_irq_mode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct thermal_zone_device *tz = to_thermal_zone(dev); + int trip, ret; + bool mode; + + if (!tz->ops->get_trip_irq_mode) + return -EPERM; + + if (sscanf(attr->attr.name, "trip_point_%d_irq", &trip) != 1) + return -EINVAL; + + ret = tz->ops->get_trip_irq_mode(tz, trip, &mode); + + if (ret) + return ret; + + return sprintf(buf, "%d\n", mode); +} + static ssize_t trip_point_hyst_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) @@ -520,10 +544,19 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask) if (!tz->trip_type_attrs) return -ENOMEM; + tz->trip_irq_mode_attrs = kcalloc(tz->trips, + sizeof(*tz->trip_irq_mode_attrs), + GFP_KERNEL); + if (!tz->trip_irq_mode_attrs) { + kfree(tz->trip_type_attrs); + return -ENOMEM; + } + tz->trip_temp_attrs = kcalloc(tz->trips, sizeof(*tz->trip_temp_attrs), GFP_KERNEL); if (!tz->trip_temp_attrs) { kfree(tz->trip_type_attrs); + kfree(tz->trip_irq_mode_attrs); return -ENOMEM; } @@ -533,14 +566,17 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask) GFP_KERNEL); if (!tz->trip_hyst_attrs) { kfree(tz->trip_type_attrs); + kfree(tz->trip_irq_mode_attrs); kfree(tz->trip_temp_attrs); return -ENOMEM; } } - attrs = kcalloc(tz->trips * 3 + 1, sizeof(*attrs), GFP_KERNEL); + attrs = kcalloc(tz->trips * TRIP_ATTR_NUM + 1, sizeof(*attrs), + GFP_KERNEL); if (!attrs) { kfree(tz->trip_type_attrs); + kfree(tz->trip_irq_mode_attrs); kfree(tz->trip_temp_attrs); if (tz->ops->get_trip_hyst) kfree(tz->trip_hyst_attrs); @@ -559,6 +595,19 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask) tz->trip_type_attrs[indx].attr.show = trip_point_type_show; attrs[indx] = &tz->trip_type_attrs[indx].attr.attr; + /* create trip irq_mode attribute */ + snprintf(tz->trip_irq_mode_attrs[indx].name, + THERMAL_NAME_LENGTH, "trip_point_%d_irq", indx); + + sysfs_attr_init(&tz->trip_irq_mode_attrs[indx].attr.attr); + tz->trip_irq_mode_attrs[indx].attr.attr.name = + tz->trip_irq_mode_attrs[indx].name; + tz->trip_irq_mode_attrs[indx].attr.attr.mode = S_IRUGO; + tz->trip_irq_mode_attrs[indx].attr.show = + trip_point_irq_mode_show; + attrs[indx + tz->trips * 3] = + &tz->trip_irq_mode_attrs[indx].attr.attr; + /* create trip temp attribute */ snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH, "trip_point_%d_temp", indx); @@ -595,7 +644,7 @@ static int create_trip_attrs(struct thermal_zone_device *tz, int mask) attrs[indx + tz->trips * 2] = &tz->trip_hyst_attrs[indx].attr.attr; } - attrs[tz->trips * 3] = NULL; + attrs[tz->trips * TRIP_ATTR_NUM] = NULL; tz->trips_attribute_group.attrs = attrs; From 9fc04761ca206ccd336cac1204021c330a1cf6f7 Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 15 Oct 2019 16:17:38 +1030 Subject: [PATCH 025/133] ODROID-XU4: arm: dts: exynos: enable per cpu thermal trips with irq-mode for Odroid XU3/4 1. Each A15 cores thermal sensor now correctly used and will trigger the fan or passive throttling as required. 2. Separate file used for trip points to allow unique labels per trip per cpu to be generated without having to duplicate the trips each time. Keeps code clear and allows for easy changes. 3. Trip points tweaked to optimise performance. A7's kept at full speed for longer since they contribute little to the thermal load. Efficiency is improved by not throttling them until required. A15's throttled earlier to manage performance better under heavy loads to extract maximum performance from the available cooling. 4. Cooling levels and temperature trip points tweaked by memeka Change-Id: I5353daa395ed5234dc955eab036956855e952ce0 --- .../boot/dts/exynos5422-odroidxu3-common.dtsi | 310 +----------------- .../dts/exynos5422-odroidxu3-trip-points.dtsi | 117 +++++++ 2 files changed, 130 insertions(+), 297 deletions(-) create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 8388720374932d..10129b44f88778 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -45,317 +45,33 @@ compatible = "pwm-fan"; pwms = <&pwm 0 20972 0>; #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; + cooling-levels = <0 120 180 240>; }; thermal-zones { cpu0_thermal: cpu0-thermal { thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ - cpu0_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu0_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu0_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1600 MHz and 1100 MHz. - */ - map3 { - trip = <&cpu0_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert4, reduce CPU - * further, down to 600 MHz (12 steps for big, - * 7 steps for LITTLE). - */ - map4 { - trip = <&cpu0_alert4>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 0 + #include "exynos5422-odroidxu3-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu1_thermal: cpu1-thermal { thermal-sensors = <&tmu_cpu1 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu1_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu1_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu1_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu1_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map4 { - trip = <&cpu1_alert4>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 1 + #include "exynos5422-odroidxu3-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu2_thermal: cpu2-thermal { thermal-sensors = <&tmu_cpu2 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu2_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu2_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu2_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu2_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map4 { - trip = <&cpu2_alert4>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 2 + #include "exynos5422-odroidxu3-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu3_thermal: cpu3-thermal { thermal-sensors = <&tmu_cpu3 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu3_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu3_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu3_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu3_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map4 { - trip = <&cpu3_alert4>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 3 + #include "exynos5422-odroidxu3-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi new file mode 100644 index 00000000000000..ebf4b70e7089d6 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi @@ -0,0 +1,117 @@ +/* + * Device tree sources for default OdroidXU3/Exynos5422 thermal zone definition + * + * Copyright (c) 2015 Lukasz Majewski + * Anand Moon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define _TOKENPASTE(x, y) x ## y +#define TOKENPASTE(x, y) _TOKENPASTE(x, y) +#define UNIQIFY(label) TOKENPASTE(label, CPU_THERMAL_ZONE_NUM) + + polling-delay-passive = <250>; + polling-delay = <1000>; + trips { + UNIQIFY(cpu_alert0): cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_alert1): cpu-alert-1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_alert2): cpu-alert-2 { + temperature = <80000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_criti0): cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + irq-mode; + }; + /* + * Exynos542x supports only 4 trip-points + * so for these polling mode is required. + */ + UNIQIFY(cpu_alert3): cpu-alert-3 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + }; + UNIQIFY(cpu_alert4): cpu-alert-4 { + temperature = <90000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + }; + UNIQIFY(cpu_alert5): cpu-alert-5 { + temperature = <95000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&UNIQIFY(cpu_alert0)>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&UNIQIFY(cpu_alert1)>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&UNIQIFY(cpu_alert2)>; + cooling-device = <&fan0 2 3>; + }; + /* + * When reaching cpu_alert3, reduce A15 cores by 4 steps (e.g. 2.0GHz -> 1.6GHz). + * The top frequency causes high thermals on multithreaded workloads + * so better performance is gained by managing it out early. + */ + map3 { + trip = <&UNIQIFY(cpu_alert3)>; + cooling-device = <&cpu4 0 4>, + <&cpu5 0 4>, + <&cpu6 0 4>, + <&cpu7 0 4>; + }; + /* + * When reaching cpu_alert4, reduce A15 cores by 4 more steps (e.g. 1.6GHz -> 1.2GHz) + * to further manage the performance level while keeping + * thermals under control. + */ + map4 { + trip = <&UNIQIFY(cpu_alert4)>; + cooling-device = <&cpu4 5 8>, + <&cpu5 5 8>, + <&cpu6 5 8>, + <&cpu7 5 8>; + }; + /* + * When reaching cpu_alert5, reduce all CPUs to ensure thermal + * safety. A7 cores don't produce much thermal load so they are + * reduced less to optimise performance. + */ + map5 { + trip = <&UNIQIFY(cpu_alert5)>; + cooling-device = <&cpu0 0 4>, + <&cpu1 0 4>, + <&cpu2 0 4>, + <&cpu3 0 4>, + <&cpu4 9 12>, + <&cpu5 9 12>, + <&cpu6 9 12>, + <&cpu7 9 12>; + }; + }; From 98a4e76081f83d908d41c1a1cde8bf3666fc21b2 Mon Sep 17 00:00:00 2001 From: memeka Date: Tue, 12 Mar 2019 13:02:08 +1030 Subject: [PATCH 026/133] ODROID-XU4: arm: dts: exynos: enable per cpu thermal trips with irq-mode for Odroid HC1 Change-Id: I7e03be0fb60cd8948fa7bbde91789130b944a3b4 Signed-off-by: memeka --- .../dts/exynos5422-odroidhc1-trip-points.dtsi | 84 ++++++++ arch/arm/boot/dts/exynos5422-odroidhc1.dts | 187 ++---------------- 2 files changed, 96 insertions(+), 175 deletions(-) create mode 100644 arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi b/arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi new file mode 100644 index 00000000000000..e2510b5e975a7a --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi @@ -0,0 +1,84 @@ +/* + * Device tree sources for default OdroidXU3/Exynos5422 thermal zone definition + * + * Copyright (c) 2015 Lukasz Majewski + * Anand Moon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define _TOKENPASTE(x, y) x ## y +#define TOKENPASTE(x, y) _TOKENPASTE(x, y) +#define UNIQIFY(label) TOKENPASTE(label, CPU_THERMAL_ZONE_NUM) + + trips { + UNIQIFY(cpu_alert0): cpu-alert-0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_alert1): cpu-alert-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_alert2): cpu-alert-2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <2500>; /* millicelsius */ + type = "passive"; + irq-mode; + }; + UNIQIFY(cpu_criti0): cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + irq-mode; + }; + }; + cooling-maps { + /* + * When reaching cpu_alert0, reduce A15 cores by 4 steps. + * The top frequency causes high thermals on multithreaded workloads + * so better performance is gained by managing it out early. + */ + map0 { + trip = <&UNIQIFY(cpu_alert0)>; + cooling-device = <&cpu4 0 4>, + <&cpu5 0 4>, + <&cpu6 0 4>, + <&cpu7 0 4>; + }; + /* + * When reaching cpu_alert1, reduce A15 cores by 4 more steps + * to further manage the performance level while keeping + * thermals under control. + */ + map1 { + trip = <&UNIQIFY(cpu_alert1)>; + cooling-device = <&cpu4 5 8>, + <&cpu5 5 8>, + <&cpu6 5 8>, + <&cpu7 5 8>; + }; + /* + * When reaching cpu_alert2, reduce all CPUs to ensure thermal + * safety. A7 cores don't produce much thermal load so they are + * reduced less to optimise performance. + */ + map2 { + trip = <&UNIQIFY(cpu_alert2)>; + cooling-device = <&cpu0 0 4>, + <&cpu1 0 4>, + <&cpu2 0 4>, + <&cpu3 0 4>, + <&cpu4 9 12>, + <&cpu5 9 12>, + <&cpu6 9 12>, + <&cpu7 9 12>; + }; + }; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index d271e754882626..9a2c3638d95d36 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -30,190 +30,27 @@ thermal-zones { cpu0_thermal: cpu0-thermal { thermal-sensors = <&tmu_cpu0 0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * When reaching cpu0_alert0, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1600 MHz and 1100 MHz. - */ - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert1, reduce CPU - * further, down to 600 MHz (12 steps for big, - * 7 steps for LITTLE). - */ - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 0 + #include "exynos5422-odroidhc1-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu1_thermal: cpu1-thermal { thermal-sensors = <&tmu_cpu1 0>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 1 + #include "exynos5422-odroidhc1-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu2_thermal: cpu2-thermal { thermal-sensors = <&tmu_cpu2 0>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 2 + #include "exynos5422-odroidhc1-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; cpu3_thermal: cpu3-thermal { thermal-sensors = <&tmu_cpu3 0>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; - }; - }; + #define CPU_THERMAL_ZONE_NUM 3 + #include "exynos5422-odroidhc1-trip-points.dtsi" + #undef CPU_THERMAL_ZONE_NUM }; }; From aebfe71ac2e0f3f4b55842db8e5c3d95eaa23c7e Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:56 +0200 Subject: [PATCH 027/133] ODROID-XU4: dt-bindings: ddr: rename lpddr2 directory Change directory name to be ready for new types of memories. Change-Id: If95f444fbca82d0735402e3427d14870ac9dc169 Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba Signed-off-by: memeka --- .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%) diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt similarity index 100% rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt similarity index 96% rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt rename to Documentation/devicetree/bindings/ddr/lpddr2.txt index 58354a075e1392..ddd40121e6f685 100644 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -36,7 +36,7 @@ Child nodes: "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" Example: From faeeba0f4cb66c3ab5d80b5b30e5d82e39650981 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:57 +0200 Subject: [PATCH 028/133] ODROID-XU4: dt-bindings: ddr: add LPDDR3 memories Specifies the AC timing parameters of the LPDDR3 memory device. Change-Id: I05b121fb8eaa682afd88d383e38a9cfe9f6fa175 Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba Signed-off-by: memeka --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 00000000000000..84705e50a3fd57 --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 00000000000000..3b2485b84b3ff3 --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From 25abd884e52586af03cb3a4ebb788b04b41b7186 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:58 +0200 Subject: [PATCH 029/133] ODROID-XU4: drivers: memory: extend of_memory by LPDDR3 support The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Change-Id: I42ab5749c048f38a6e64c8ce401311228de87c93 Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: memeka --- drivers/memory/jedec_ddr.h | 61 +++++++++++++++ drivers/memory/of_memory.c | 149 +++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 18 +++++ 3 files changed, 228 insertions(+) diff --git a/drivers/memory/jedec_ddr.h b/drivers/memory/jedec_ddr.h index 4a21b5044ff888..e59ccbd982d025 100644 --- a/drivers/memory/jedec_ddr.h +++ b/drivers/memory/jedec_ddr.h @@ -29,6 +29,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -169,4 +170,64 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) excluding max_freq, min_freq which + * are in Hz. + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __JEDEC_DDR_H */ diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 46539b27a3fb92..71f26eac7350ff 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -3,6 +3,7 @@ * OpenFirmware helpers for memory drivers * * Copyright (C) 2012 Texas Instruments, Inc. + * Copyright (C) 2019 Samsung Electronics Co., Ltd. */ #include @@ -149,3 +150,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + +/** + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3 + * @np: pointer to ddr device tree node + * @device: device requesting for min timing values + * + * Populates the lpddr3_min_tck structure by extracting data + * from device tree node. Returns a pointer to the populated + * structure. If any error in populating the structure, returns NULL. + */ +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + /* The 'reg' param required since DT has changed, used as 'max-freq' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +/** + * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of + * frequencies available. + * @np_ddr: Pointer to ddr device tree node + * @dev: Device requesting for ddr timings + * @device_type: Type of ddr + * @nr_frequencies: No of frequencies available for ddr + * (updated by this function) + * + * Populates lpddr3_timings structure by extracting data from device + * tree node. Returns pointer to populated structure. If any error + * while populating, returns NULL. + */ +const struct lpddr3_timings +*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev, + u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: failed to get timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index b077cc836b0b6a..e39ecc4c733d11 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -14,6 +14,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -27,6 +32,19 @@ static inline const struct lpddr2_timings { return NULL; } + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} #endif /* CONFIG_OF && CONFIG_DDR */ #endif /* __LINUX_MEMORY_OF_REG_ */ From 7cd7ae05a8eaa0c7e93cd91e7994f53b81cf07d5 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:59 +0200 Subject: [PATCH 030/133] ODROID-XU4: dt-bindings: memory-controllers: add Exynos5422 DMC device description The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Change-Id: I50cc19ae01d34bd30890e0dc65bf741bc5bc0aad Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba Signed-off-by: memeka --- .../memory-controllers/exynos5422-dmc.txt | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 00000000000000..02aeb3b5a82087 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; From 9eeb23744d90ac4d323a6c2b2f8c8ff476effc9c Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:00 +0200 Subject: [PATCH 031/133] ODROID-XU4: drivers: memory: add DMC driver for Exynos5422 This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Change-Id: I6b81edf71772f9dd8ed3fde27b64cba9bbb29042 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 13 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1257 +++++++++++++++++++++++ 4 files changed, 1279 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index d1aeebb59e6a5b..10fb83dad050ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4965,6 +4965,14 @@ F: include/linux/dma-direct.h F: include/linux/dma-mapping.h F: include/linux/dma-noncoherent.h +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + DME1737 HARDWARE MONITOR DRIVER M: Juerg Haefliger L: linux-hwmon@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea589034f..e9c3ce92350c07 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -7,6 +7,19 @@ config SAMSUNG_MC if SAMSUNG_MC +config EXYNOS5422_DMC + tristate "EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS || (COMPILE_TEST && HAS_IOMEM) + select DDR + depends on DEVFREQ_GOV_SIMPLE_ONDEMAND + depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT) + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + config EXYNOS_SROM bool "Exynos SROM controller driver" if COMPILE_TEST depends on (ARM && ARCH_EXYNOS) || (COMPILE_TEST && HAS_IOMEM) diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be6621159..ea071be21c4498 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 00000000000000..8c2ec29a7d570c --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * Author: Lukasz Luba + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../jedec_ddr.h" +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x2091c) +#define CDREX_LPDDR3PHY_CON3 (0x20a20) +#define CDREX_LPDDR3PHY_CLKM_SRC (0x20700) +#define EXYNOS5_TIMING_SET_SWI BIT(28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) +#define EXYNOS5_AREF_NORMAL (0x2e) + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + struct regmap *clk_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = (t_val) << (timing)->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static const struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static const struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static const struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +static int exynos5_counters_set_event(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_set_event(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_enable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_disable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dmc->dev); + if (ret < 0) { + dev_err(dmc->dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dmc->dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt <= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int +exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + if (ret) + goto disable_clocks; + + /* + * We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings will be ready for the upcoming clock + * source change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + goto disable_clocks; + + /* + * Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + +disable_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dmc: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc, + unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dmc->dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + const struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np_ddr); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + unsigned int tmp; + + dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev, + "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + /* + * Some bootloaders do not set clock routes correctly. + * Stop one path in clocks to PHY. + */ + regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); + tmp &= ~(BIT(1) | BIT(0)); + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + exynos5_counters_disable_edev(dmc); + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct exynos5_dmc *dmc; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-clk"); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + return ret; + } + + ret = exynos5_dmc_init_clks(dmc); + if (ret) + return ret; + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto err_devfreq_add; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(dev, "DMC initialized\n"); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + dev_pm_opp_remove_table(dmc->dev); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Lukasz Luba"); From f8f287e6bebe2fc3c5a386dc1533c8e19e6504dc Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:01 +0200 Subject: [PATCH 032/133] ODROID-XU4: ARM: dts: exynos: add syscon to clock compatible In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Change-Id: I5f844e15214928b1b2240c4df9802a1924f207d3 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8c354902c3f8e7..57feb596e83a9b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -175,7 +175,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index da293b0ec4114a..5aac4de5d01ae5 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From 488f252988279d5ccce82ff8f3e91febae861699 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:02 +0200 Subject: [PATCH 033/133] ODROID-XU4: ARM: dts: exynos: add DMC device for exynos5422 Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Change-Id: Icd26d77033c2e1e4e71f28e64f5b126d865bdbbc Signed-off-by: Lukasz Luba Signed-off-by: memeka --- arch/arm/boot/dts/exynos5420.dtsi | 71 +++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++ 2 files changed, 187 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 57feb596e83a9b..44c753fb65ba9a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -237,6 +237,29 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -273,6 +296,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index ce774f7b2ce04c..b3ed4c6a656709 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,97 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +223,15 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -633,6 +733,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; status = "okay"; From 9a2fba379b9ad3c20911c90e7aedc9237dd8aead Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:03 +0200 Subject: [PATCH 034/133] ODROID-XU4: ARM: exynos_defconfig: enable DMC driver Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Change-Id: Ib31c2789a5a87823a5441d922f3aec5c8696e187 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 34d4acbcee347c..5c966cad2b0b8b 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -297,6 +297,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_EXYNOS5422_DMC=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14577=y From 3685fe5099c447ae8f74d54000712c22c71f14a6 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 19 Sep 2019 11:26:40 +0200 Subject: [PATCH 035/133] ODROID-XU4: memory: samsung: exynos5422-dmc: Fix kfree() of devm-allocated memory and missing static Fix issues captured by static checkers: used kfree() and missing 'static' in the private function. Fixes Smatch warning: drivers/memory/samsung/exynos5422-dmc.c:272 exynos5_init_freq_table() warn: passing devm_ allocated variable to kfree. 'dmc->opp' Fixes Sparse warning: drivers/memory/samsung/exynos5422-dmc.c:736:1: warning: symbol 'exynos5_dmc_align_init_freq' was not declared. Change-Id: I98f7b908abc26f17187c771f668b7bf64658be38 Reported-by: kbuild test robot Reported-by: Dan Carpenter Reported-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: memeka --- drivers/memory/samsung/exynos5422-dmc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 8c2ec29a7d570c..1b54fc8c912e38 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -258,7 +258,7 @@ static int exynos5_init_freq_table(struct exynos5_dmc *dmc, opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); if (IS_ERR(opp)) - goto err_free_tables; + goto err_opp; dmc->opp[idx - i].freq_hz = freq; dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); @@ -268,8 +268,6 @@ static int exynos5_init_freq_table(struct exynos5_dmc *dmc, return 0; -err_free_tables: - kfree(dmc->opp); err_opp: dev_pm_opp_of_remove_table(dmc->dev); @@ -732,7 +730,7 @@ static struct devfreq_dev_profile exynos5_dmc_df_profile = { * statistics engine which supports only registered values. Thus, some alignment * must be made. */ -unsigned long +static unsigned long exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, unsigned long bootloader_init_freq) { From b639d00c2f3a63af3a8d371da0d26e36e8f624d8 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 19 Sep 2019 11:26:41 +0200 Subject: [PATCH 036/133] ODROID-XU4: dt-bindings: ddr: Add bindings for Samsung LPDDR3 memories Add compatible for Samsung k3qf2f20db LPDDR3 memory bindings. Suggested to based on at25.txt compatible section. Introduce minor fixes in the old documentation. Change-Id: I48f8025c745f95cbd4b29cf2ad04d77cac685a1f Suggested-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: memeka --- Documentation/devicetree/bindings/ddr/lpddr3.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt index 3b2485b84b3ff3..a0eda35a86eef9 100644 --- a/Documentation/devicetree/bindings/ddr/lpddr3.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -1,7 +1,10 @@ * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C Required properties: -- compatible : Should be - "jedec,lpddr3" +- compatible : Should be ",", and generic value "jedec,lpddr3". + Example "," values: + "samsung,K3QF2F20DB" + - density : representing density in Mb (Mega bits) - io-width : representing bus width. Possible values are 8, 16, 32, 64 - #address-cells: Must be set to 1 @@ -43,7 +46,7 @@ Child nodes: Example: samsung_K3QF2F20DB: lpddr3 { - compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; #address-cells = <1>; @@ -73,7 +76,8 @@ samsung_K3QF2F20DB: lpddr3 { timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; From f0614e49fe51a76a7add75bc8150193a36c03e89 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:52 +0200 Subject: [PATCH 037/133] ODROID-XU4: dt-bindings: memory-controllers: Add Exynos5422 DMC interrupts description Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Change-Id: I3be940bc4d49620cd63287c8be8ccf6f73ba3d24 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- .../bindings/memory-controllers/exynos5422-dmc.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index 02aeb3b5a82087..e2434cac485815 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -31,6 +31,14 @@ Required properties for DMC device for Exynos5422: The register offsets are in the driver code and specyfic for this SoC type. +Optional properties for DMC device for Exynos5422: +- interrupt-parent : The parent interrupt controller. +- interrupts : Contains the IRQ line numbers for the DMC internal performance + event counters in DREX0 and DREX1 channels. Align with specification of the + interrupt line(s) in the interrupt-parent controller. +- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the + same as in the 'interrupts' list above. + Example: ppmu_dmc0_0: ppmu@10d00000 { @@ -70,4 +78,7 @@ Example: device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; }; From 28b0636f476b75448b8689274e7ad1a72ceefb35 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:53 +0200 Subject: [PATCH 038/133] ODROID-XU4: ARM: dts: exynos: Add interrupt to DMC controller in Exynos5422 Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Change-Id: I2b4680ff82a7ff2fc038196c197c85f33b258359 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 44c753fb65ba9a..47ca6aa8f93c07 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,6 +240,9 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From 564dd71772f39a6e0c6fcefb6d3b5349d26ce673 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:54 +0200 Subject: [PATCH 039/133] ODROID-XU4: ARM: dts: exynos: map 0x10000 SFR instead of 0x100 in DMC Exynos5422 There is a need to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Change-Id: Iba1fd2397507b313f190e9232f0fab791fc28a3a Signed-off-by: Lukasz Luba Signed-off-by: memeka --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 47ca6aa8f93c07..4625af8fea7631 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -239,7 +239,7 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; interrupt-parent = <&combiner>; interrupts = <16 0>, <16 1>; interrupt-names = "drex_0", "drex_1"; From 3b37cbc72de5aa13122cd968c214b68f030a1efc Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:55 +0200 Subject: [PATCH 040/133] ODROID-XU4: memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters Introduce a new interrupt driven mechanism for managing speed of the memory controller. The interrupts are generated due to performance counters overflow. The performance counters might track memory reads, writes, transfers, page misses, etc. In the basic algorithm tracking read transfers and calculating memory pressure should be enough to skip polling mode in devfreq. Change-Id: Idb5deaa423d75a9a0961b64f9f9514d6ce7c95c1 Signed-off-by: Lukasz Luba Signed-off-by: memeka --- drivers/memory/samsung/exynos5422-dmc.c | 345 ++++++++++++++++++++++-- 1 file changed, 320 insertions(+), 25 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 1b54fc8c912e38..bdb264bdfb2dd2 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,61 @@ #define USE_BPLL_TIMINGS (0) #define EXYNOS5_AREF_NORMAL (0x2e) +#define DREX_PPCCLKCON (0x0130) +#define DREX_PEREV2CONFIG (0x013c) +#define DREX_PMNC_PPC (0xE000) +#define DREX_CNTENS_PPC (0xE010) +#define DREX_CNTENC_PPC (0xE020) +#define DREX_INTENS_PPC (0xE030) +#define DREX_INTENC_PPC (0xE040) +#define DREX_FLAG_PPC (0xE050) +#define DREX_PMCNT2_PPC (0xE130) + +/* + * A value for register DREX_PMNC_PPC which should be written to reset + * the cycle counter CCNT (a reference wall clock). It sets zero to the + * CCNT counter. + */ +#define CC_RESET BIT(2) + +/* + * A value for register DREX_PMNC_PPC which does the reset of all performance + * counters to zero. + */ +#define PPC_COUNTER_RESET BIT(1) + +/* + * Enables all configured counters (including cycle counter). The value should + * be written to the register DREX_PMNC_PPC. + */ +#define PPC_ENABLE BIT(0) + +/* A value for register DREX_PPCCLKCON which enables performance events clock. + * Must be written before first access to the performance counters register + * set, otherwise it could crash. + */ +#define PEREV_CLK_EN BIT(0) + +/* + * Values which are used to enable counters, interrupts or configure flags of + * the performance counters. They configure counter 2 and cycle counter. + */ +#define PERF_CNT2 BIT(2) +#define PERF_CCNT BIT(31) + +/* + * Performance event types which are used for setting the preferred event + * to track in the counters. + * There is a set of different types, the values are from range 0 to 0x6f. + * These settings should be written to the configuration register which manages + * the type of the event (register DREX_PEREV2CONFIG). + */ +#define READ_TRANSFER_CH0 (0x6d) +#define READ_TRANSFER_CH1 (0x6f) + +#define PERF_COUNTER_START_VALUE 0xff000000 +#define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL + /** * struct dmc_opp_table - Operating level desciption * @@ -85,6 +141,10 @@ struct exynos5_dmc { struct clk *mout_mx_mspll_ccore_phy; struct devfreq_event_dev **counter; int num_counters; + u64 last_overflow_ts[2]; + unsigned long load; + unsigned long total; + bool in_irq_mode; }; #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ @@ -653,6 +713,173 @@ static int exynos5_counters_get(struct exynos5_dmc *dmc, return 0; } +/** + * exynos5_dmc_start_perf_events() - Setup and start performance event counters + * @dmc: device for which the counters are going to be checked + * @beg_value: initial value for the counter + * + * Function which enables needed counters, interrupts and sets initial values + * then starts the counters. + */ +static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc, + u32 beg_value) +{ + /* Enable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC); + + /* Enable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); + + /* Reset all counters */ + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* + * Set start value for the counters, the number of samples that + * will be gathered is calculated as: 0xffffffff - beg_value + */ + writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC); + writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC); + + /* Start all counters */ + writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC); +} + +/** + * exynos5_dmc_perf_events_calc() - Calculate utilization + * @dmc: device for which the counters are going to be checked + * @diff_ts: time between last interrupt and current one + * + * Function which calculates needed utilization for the devfreq governor. + * It prepares values for 'busy_time' and 'total_time' based on elapsed time + * between interrupts, which approximates utilization. + */ +static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts) +{ + /* + * This is a simple algorithm for managing traffic on DMC. + * When there is almost no load the counters overflow every 4s, + * no mater the DMC frequency. + * The high load might be approximated using linear function. + * Knowing that, simple calculation can provide 'busy_time' and + * 'total_time' to the devfreq governor which picks up target + * frequency. + * We want a fast ramp up and slow decay in frequency change function. + */ + if (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) { + /* + * Set higher utilization for the simple_ondemand governor. + * The governor should increase the frequency of the DMC. + */ + dmc->load = 70; + dmc->total = 100; + } else { + /* + * Set low utilization for the simple_ondemand governor. + * The governor should decrease the frequency of the DMC. + */ + dmc->load = 35; + dmc->total = 100; + } + + dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts); +} + +/** + * exynos5_dmc_perf_events_check() - Checks the status of the counters + * @dmc: device for which the counters are going to be checked + * + * Function which is called from threaded IRQ to check the counters state + * and to call approximation for the needed utilization. + */ +static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc) +{ + u32 val; + u64 diff_ts, ts; + + ts = ktime_get_ns(); + + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Check the source in interrupt flag registers (which channel) */ + val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); + if (val) { + diff_ts = ts - dmc->last_overflow_ts[0]; + dmc->last_overflow_ts[0] = ts; + dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val); + } else { + val = readl(dmc->base_drexi1 + DREX_FLAG_PPC); + diff_ts = ts - dmc->last_overflow_ts[1]; + dmc->last_overflow_ts[1] = ts; + dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val); + } + + exynos5_dmc_perf_events_calc(dmc, diff_ts); + + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); +} + +/** + * exynos5_dmc_enable_perf_events() - Enable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which is setup needed environment and enables counters. + */ +static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc) +{ + u64 ts; + + /* Enable Performance Event Clock */ + writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON); + writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON); + + /* Select read transfers as performance event2 */ + writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG); + writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG); + + ts = ktime_get_ns(); + dmc->last_overflow_ts[0] = ts; + dmc->last_overflow_ts[1] = ts; + + /* Devfreq shouldn't be faster than initialization, play safe though. */ + dmc->load = 99; + dmc->total = 100; +} + +/** + * exynos5_dmc_disable_perf_events() - Disable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which stops, disables performance event counters and interrupts. + */ +static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc) +{ + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Disable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC); + + /* Disable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); +} + /** * exynos5_dmc_get_status() - Read current DMC performance statistics. * @dev: device for which the statistics are requested @@ -669,18 +896,24 @@ static int exynos5_dmc_get_status(struct device *dev, unsigned long load, total; int ret; - ret = exynos5_counters_get(dmc, &load, &total); - if (ret < 0) - return -EINVAL; + if (dmc->in_irq_mode) { + stat->current_frequency = dmc->curr_rate; + stat->busy_time = dmc->load; + stat->total_time = dmc->total; + } else { + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; - /* To protect from overflow in calculation ratios, divide by 1024 */ - stat->busy_time = load >> 10; - stat->total_time = total >> 10; + /* To protect from overflow, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; - ret = exynos5_counters_set_event(dmc); - if (ret < 0) { - dev_err(dev, "could not set event counter\n"); - return ret; + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } } return 0; @@ -712,7 +945,6 @@ static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) * It provides to the devfreq framework needed functions and polling period. */ static struct devfreq_dev_profile exynos5_dmc_df_profile = { - .polling_ms = 500, .target = exynos5_dmc_target, .get_dev_status = exynos5_dmc_get_status, .get_cur_freq = exynos5_dmc_get_cur_freq, @@ -1108,6 +1340,24 @@ static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) return 0; } +static irqreturn_t dmc_irq_thread(int irq, void *priv) +{ + int res; + struct exynos5_dmc *dmc = priv; + + mutex_lock(&dmc->df->lock); + + exynos5_dmc_perf_events_check(dmc); + + res = update_devfreq(dmc->df); + if (res) + dev_warn(dmc->dev, "devfreq failed with %d\n", res); + + mutex_unlock(&dmc->df->lock); + + return IRQ_HANDLED; +} + /** * exynos5_dmc_probe() - Probe function for the DMC driver * @pdev: platform device for which the driver is going to be initialized @@ -1125,6 +1375,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; struct exynos5_dmc *dmc; struct resource *res; + int irq[2]; dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); if (!dmc) @@ -1172,24 +1423,59 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto remove_clocks; } - ret = exynos5_performance_counters_init(dmc); + ret = exynos5_dmc_set_pause_on_switching(dmc); if (ret) { - dev_warn(dev, "couldn't probe performance counters\n"); + dev_warn(dev, "couldn't get access to PAUSE register\n"); goto remove_clocks; } - ret = exynos5_dmc_set_pause_on_switching(dmc); - if (ret) { - dev_warn(dev, "couldn't get access to PAUSE register\n"); - goto err_devfreq_add; + /* There is two modes in which the driver works: polling or IRQ */ + irq[0] = platform_get_irq_byname(pdev, "drex_0"); + irq[1] = platform_get_irq_byname(pdev, "drex_1"); + if (irq[0] > 0 && irq[1] > 0) { + ret = devm_request_threaded_irq(dev, irq[0], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + ret = devm_request_threaded_irq(dev, irq[1], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 55; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_enable_perf_events(dmc); + + dmc->in_irq_mode = 1; + } else { + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_df_profile.polling_ms = 500; } - /* - * Setup default thresholds for the devfreq governor. - * The values are chosen based on experiments. - */ - dmc->gov_data.upthreshold = 30; - dmc->gov_data.downdifferential = 5; dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, @@ -1200,12 +1486,18 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto err_devfreq_add; } + if (dmc->in_irq_mode) + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); + dev_info(dev, "DMC initialized\n"); return 0; err_devfreq_add: - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); remove_clocks: clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll); @@ -1225,7 +1517,10 @@ static int exynos5_dmc_remove(struct platform_device *pdev) { struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll); From 91a738e8ead882ac996d31dc64c93c0ccd26e132 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Oct 2019 19:44:01 +0200 Subject: [PATCH 041/133] ODROID-XU4: dt-bindings: memory-controllers: exynos5422-dmc: Correct example syntax and memory region After adding the interrupt properties to Exynos5422 DMC bindings example, the mapped memory region must be big enough to access performance counters registers. Fix also syntax errors (semicolons) and adjust indentation. Change-Id: Ibbf0579f8aa76c56d9cee48809ed341e3561d383 Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lukasz Luba Signed-off-by: memeka --- .../bindings/memory-controllers/exynos5422-dmc.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index e2434cac485815..02e4a1f862f1fb 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -55,7 +55,7 @@ Example: dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, @@ -63,7 +63,7 @@ Example: <&clock CLK_MOUT_BPLL>, <&clock CLK_SCLK_BPLL>, <&clock CLK_MOUT_MX_MSPLL_CCORE>, - <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_MOUT_MCLK_CDREX>; clock-names = "fout_spll", "mout_sclk_spll", "ff_dout_spll2", @@ -71,10 +71,10 @@ Example: "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", - "mout_mclk_cdrex", + "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, - <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; From afa8e3942d6966afcd4272ec174fd78a95ce6b2a Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 10 Sep 2019 14:36:17 +0200 Subject: [PATCH 042/133] ODROID-XU4: ARM: dts: Add "syscon" compatible string to chipid node The CHIP ID block in addition to exact chip revision information contains data and control registers for ASV (Adaptive Supply Voltage) and ABB (Adaptive Body Bias). Add "syscon" compatible so the CHIPID block can be shared by respective drivers. Change-Id: Id7469143417eac92f1f7d010004b67ae6ed35e8d Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka --- arch/arm/boot/dts/exynos5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 67f9b4504a4215..4801ca759feb0f 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -35,8 +35,8 @@ #size-cells = <1>; ranges; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid", "syscon"; reg = <0x10000000 0x100>; }; From 37f8113486edae732e38e21131c4557b33baa960 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 10 Sep 2019 14:36:18 +0200 Subject: [PATCH 043/133] ODROID-XU4: ARM: dts: Add samsung,asv-bin property for odroidxu3-lite The Exynos5422 SoC used on Odroid XU3 Lite boards belongs to a special ASV bin but this information cannot be read from the CHIPID block registers. Add samsung,asv-bin property for XU3 Lite to ensure the ASV bin is properly determined. Change-Id: I6e977b9cf0829be7ffff5aa84d7ee6b3e65b49cd Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka --- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 8082e3ce4228c4..a0d5e370da3ecc 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -35,6 +35,10 @@ status = "disabled"; }; +&chipid { + samsung,asv-bin = <2>; +}; + &pwm { /* * PWM 0 -- fan From 1e4ebb650c1af1f5cba1b73f436bfb0572b9f006 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 7 Sep 2019 11:20:02 +0200 Subject: [PATCH 044/133] ODROID-XU4: dt-bindings: arm: samsung: Convert Exynos Chipid bindings to json-schema Convert Samsung Exynos Chipid bindings to DT schema format using json-schema. Change-Id: Ia6906a3f50d6f0a791fdd3e6e583e92a08716e4b Signed-off-by: Krzysztof Kozlowski Signed-off-by: memeka --- .../bindings/arm/samsung/exynos-chipid.txt | 12 --------- .../bindings/arm/samsung/exynos-chipid.yaml | 25 +++++++++++++++++++ 2 files changed, 25 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt create mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt deleted file mode 100644 index 85c5dfd4a7203d..00000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt +++ /dev/null @@ -1,12 +0,0 @@ -SAMSUNG Exynos SoCs Chipid driver. - -Required properties: -- compatible : Should at least contain "samsung,exynos4210-chipid". - -- reg: offset and length of the register set - -Example: - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml new file mode 100644 index 00000000000000..9c573ad7dc7d03 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Chipid driver + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + items: + - const: samsung,exynos4210-chipid + + reg: + maxItems: 1 + +examples: + - | + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; From c543f0f92b9ac361834cbd243d20a0bfb830c5f4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Oct 2019 16:57:53 +0200 Subject: [PATCH 045/133] ODROID-XU4: PM / OPP: Support adjusting OPP voltages at runtime On some SoCs the Adaptive Voltage Scaling (AVS) technique is employed to optimize the operating voltage of a device. At a given frequency, the hardware monitors dynamic factors and either makes a suggestion for how much to adjust a voltage for the current frequency, or it automatically adjusts the voltage without software intervention. Add an API to the OPP library for the former case, so that AVS type devices can update the voltages for an OPP when the hardware determines the voltage should change. The assumption is that drivers like CPUfreq or devfreq will register for the OPP notifiers and adjust the voltage according to suggestions that AVS makes. This patch is derived from [1] submitted by Stephen. [1] https://lore.kernel.org/patchwork/patch/599279/ Signed-off-by: Stephen Boyd Signed-off-by: Roger Lu [s.nawrocki@samsung.com: added handling of OPP min/max voltage] Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka Change-Id: I172ca9d88d40e97216eeac76ba3e74f12f984765 --- drivers/opp/core.c | 69 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 13 ++++++++ 2 files changed, 82 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 9ff0538ee83a01..be7a7d332332d4 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2102,6 +2102,75 @@ static int _opp_set_availability(struct device *dev, unsigned long freq, return r; } +/** + * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP + * @dev: device for which we do this operation + * @freq: OPP frequency to adjust voltage of + * @u_volt: new OPP target voltage + * @u_volt_min: new OPP min voltage + * @u_volt_max: new OPP max voltage + * + * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the + * copy operation, returns 0 if no modifcation was done OR modification was + * successful. + */ +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt, unsigned long u_volt_min, + unsigned long u_volt_max) + +{ + struct opp_table *opp_table; + struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV); + int r = 0; + + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + r = PTR_ERR(opp_table); + dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r); + return r; + } + + mutex_lock(&opp_table->lock); + + /* Do we have the frequency? */ + list_for_each_entry(tmp_opp, &opp_table->opp_list, node) { + if (tmp_opp->rate == freq) { + opp = tmp_opp; + break; + } + } + + if (IS_ERR(opp)) { + r = PTR_ERR(opp); + goto adjust_unlock; + } + + /* Is update really needed? */ + if (opp->supplies->u_volt == u_volt) + goto adjust_unlock; + + opp->supplies->u_volt = u_volt; + opp->supplies->u_volt_min = u_volt_min; + opp->supplies->u_volt_max = u_volt_max; + + dev_pm_opp_get(opp); + mutex_unlock(&opp_table->lock); + + /* Notify the voltage change of the OPP */ + blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE, + opp); + + dev_pm_opp_put(opp); + goto adjust_put_table; + +adjust_unlock: + mutex_unlock(&opp_table->lock); +adjust_put_table: + dev_pm_opp_put_opp_table(opp_table); + return r; +} + /** * dev_pm_opp_enable() - Enable a specific OPP * @dev: device for which we do this operation diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index b8197ab014f296..747861816f4f55 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -22,6 +22,7 @@ struct opp_table; enum dev_pm_opp_event { OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, + OPP_EVENT_ADJUST_VOLTAGE, }; /** @@ -113,6 +114,10 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq, void dev_pm_opp_remove(struct device *dev, unsigned long freq); void dev_pm_opp_remove_all_dynamic(struct device *dev); +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt, unsigned long u_volt_min, + unsigned long u_volt_max); + int dev_pm_opp_enable(struct device *dev, unsigned long freq); int dev_pm_opp_disable(struct device *dev, unsigned long freq); @@ -242,6 +247,14 @@ static inline void dev_pm_opp_remove_all_dynamic(struct device *dev) { } +static inline int +dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt, unsigned long u_volt_min, + unsigned long u_volt_max) +{ + return 0; +} + static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) { return 0; From ca147c5f2b23a436271de56de5997e683c3d4865 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 16 Oct 2019 16:57:54 +0200 Subject: [PATCH 046/133] ODROID-XU4: dt-bindings: arm: samsung: Update the CHIPID binding for ASV This patch adds documentation of new optional "samsung,asv-bin" property in the chipid device node and documents requirement of "syscon" compatible string. These additions are needed to support Exynos ASV (Adaptive Supply Voltage) feature. Change-Id: Ib51dbc3ad36705abc3df17a6b80a614a0b28c215 Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Signed-off-by: memeka --- .../bindings/arm/samsung/exynos-chipid.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml index 9c573ad7dc7d03..df84d9e9f4c2bd 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -9,17 +9,42 @@ title: Samsung Exynos SoC series Chipid driver maintainers: - Krzysztof Kozlowski +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + const: samsung,exynos4210-chipid + required: + - compatible + properties: compatible: - items: - - const: samsung,exynos4210-chipid + allOf: + - items: + - const: samsung,exynos4210-chipid + - const: syscon reg: maxItems: 1 + samsung,asv-bin: + description: + Adaptive Supply Voltage bin selection. This can be used + to determine the ASV bin of an SoC if respective information + is missing in the CHIPID registers or in the OTP memory. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1, 2, 3 ] + +required: + - compatible + - reg + examples: - | chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; + compatible = "samsung,exynos4210-chipid", "syscon"; reg = <0x10000000 0x100>; + samsung,asv-bin = <2>; }; From f7b16d53c36222111848a89f3288c456af47d7d6 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 16 Oct 2019 16:57:55 +0200 Subject: [PATCH 047/133] ODROID-XU4: soc: samsung: Add Exynos Adaptive Supply Voltage driver The Adaptive Supply Voltage (ASV) driver adjusts CPU cluster operating points depending on exact revision of an SoC retrieved from the CHIPID block or the OTP memory. This allows for some power saving as for some CPU clock frequencies we can lower CPU cluster's supply voltage comparing to safe values common to all the SoC revisions. This patch adds support for Exynos5422/5800 SoC, it is partially based on code from https://github.com/hardkernel/linux repository, branch odroidxu4-4.14.y, files: arch/arm/mach-exynos/exynos5422-asv.[ch]. Tested on Odroid XU3, XU4, XU3 Lite. Change-Id: I1cfc9324ba11a77ebccbca1176caa28abb2527de Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka --- drivers/soc/samsung/Kconfig | 10 + drivers/soc/samsung/Makefile | 3 + drivers/soc/samsung/exynos-asv.c | 179 ++++++++++ drivers/soc/samsung/exynos-asv.h | 82 +++++ drivers/soc/samsung/exynos5422-asv.c | 509 +++++++++++++++++++++++++++ drivers/soc/samsung/exynos5422-asv.h | 25 ++ 6 files changed, 808 insertions(+) create mode 100644 drivers/soc/samsung/exynos-asv.c create mode 100644 drivers/soc/samsung/exynos-asv.h create mode 100644 drivers/soc/samsung/exynos5422-asv.c create mode 100644 drivers/soc/samsung/exynos5422-asv.h diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index 33ad0de2de3c39..27fc59bbb5206d 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -7,6 +7,16 @@ menuconfig SOC_SAMSUNG if SOC_SAMSUNG +config EXYNOS_ASV + bool "Exynos Adaptive Supply Voltage support" if COMPILE_TEST + depends on (ARCH_EXYNOS && EXYNOS_CHIPID) || COMPILE_TEST + select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS + +# There is no need to enable these drivers for ARMv8 +config EXYNOS_ASV_ARM + bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST + depends on EXYNOS_ASV + config EXYNOS_CHIPID bool "Exynos Chipid controller driver" if COMPILE_TEST depends on ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 3b6a8797416c03..edd1d6ea064d8f 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_EXYNOS_ASV) += exynos-asv.o +obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o + obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c new file mode 100644 index 00000000000000..c6f2e4f0dcc5da --- /dev/null +++ b/drivers/soc/samsung/exynos-asv.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * Author: Sylwester Nawrocki + * + * Samsung Exynos SoC Adaptive Supply Voltage support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "exynos-asv.h" +#include "exynos5422-asv.h" + +#define MHZ 1000000U + +static int exynos_asv_update_cpu_opps(struct exynos_asv *asv, + struct device *cpu) +{ + struct exynos_asv_subsys *subsys = NULL; + struct dev_pm_opp *opp; + unsigned int opp_freq; + int i; + + for (i = 0; i < ARRAY_SIZE(asv->subsys); i++) { + if (of_device_is_compatible(cpu->of_node, + asv->subsys[i].cpu_dt_compat)) { + subsys = &asv->subsys[i]; + break; + } + } + if (!subsys) + return -EINVAL; + + for (i = 0; i < subsys->table.num_rows; i++) { + unsigned int new_volt, volt; + int ret; + + opp_freq = exynos_asv_opp_get_frequency(subsys, i); + + opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); + if (IS_ERR(opp)) { + dev_info(asv->dev, "cpu%d opp%d, freq: %u missing\n", + cpu->id, i, opp_freq); + + continue; + } + + volt = dev_pm_opp_get_voltage(opp); + new_volt = asv->opp_get_voltage(subsys, i, volt); + dev_pm_opp_put(opp); + + if (new_volt == volt) + continue; + + ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, + new_volt, new_volt, new_volt); + if (ret < 0) + dev_err(asv->dev, + "Failed to adjust OPP %u Hz/%u uV for cpu%d\n", + opp_freq, new_volt, cpu->id); + else + dev_dbg(asv->dev, + "Adjusted OPP %u Hz/%u -> %u uV, cpu%d\n", + opp_freq, volt, new_volt, cpu->id); + } + + return 0; +} + +static int exynos_asv_update_opps(struct exynos_asv *asv) +{ + struct opp_table *last_opp_table = NULL; + struct device *cpu; + int ret, cpuid; + + for_each_possible_cpu(cpuid) { + struct opp_table *opp_table; + + cpu = get_cpu_device(cpuid); + if (!cpu) + continue; + + opp_table = dev_pm_opp_get_opp_table(cpu); + if (IS_ERR(opp_table)) + continue; + + if (!last_opp_table || opp_table != last_opp_table) { + last_opp_table = opp_table; + + ret = exynos_asv_update_cpu_opps(asv, cpu); + if (ret < 0) + dev_err(asv->dev, "Couldn't udate OPPs for cpu%d\n", + cpuid); + } + + dev_pm_opp_put_opp_table(opp_table); + } + + return 0; +} + +static int exynos_asv_probe(struct platform_device *pdev) +{ + int (*probe_func)(struct exynos_asv *asv); + struct exynos_asv *asv; + struct device *cpu_dev; + u32 product_id = 0; + int ret, i; + + cpu_dev = get_cpu_device(0); + ret = dev_pm_opp_get_opp_count(cpu_dev); + if (ret < 0) + return -EPROBE_DEFER; + + asv = devm_kzalloc(&pdev->dev, sizeof(*asv), GFP_KERNEL); + if (!asv) + return -ENOMEM; + + asv->chipid_regmap = syscon_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(asv->chipid_regmap)) { + dev_err(&pdev->dev, "Could not find syscon regmap\n"); + return PTR_ERR(asv->chipid_regmap); + } + + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id); + + switch (product_id & EXYNOS_MASK) { + case 0xE5422000: + probe_func = exynos5422_asv_init; + break; + default: + dev_err(&pdev->dev, "Unsupported product ID: %#x", product_id); + return -ENODEV; + } + + ret = of_property_read_u32(pdev->dev.of_node, "samsung,asv-bin", + &asv->of_bin); + if (ret < 0) + asv->of_bin = -EINVAL; + + asv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, asv); + + for (i = 0; i < ARRAY_SIZE(asv->subsys); i++) + asv->subsys[i].asv = asv; + + ret = probe_func(asv); + if (ret < 0) + return ret; + + return exynos_asv_update_opps(asv); +} + +static const struct of_device_id exynos_asv_of_device_ids[] = { + { .compatible = "samsung,exynos4210-chipid" }, + {} +}; + +static struct platform_driver exynos_asv_driver = { + .driver = { + .name = "exynos-asv", + .of_match_table = exynos_asv_of_device_ids, + }, + .probe = exynos_asv_probe, +}; +module_platform_driver(exynos_asv_driver); diff --git a/drivers/soc/samsung/exynos-asv.h b/drivers/soc/samsung/exynos-asv.h new file mode 100644 index 00000000000000..14b4fedf2dddbe --- /dev/null +++ b/drivers/soc/samsung/exynos-asv.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * Author: Sylwester Nawrocki + * + * Samsung Exynos SoC Adaptive Supply Voltage support + */ +#ifndef __LINUX_SOC_EXYNOS_ASV_H +#define __LINUX_SOC_EXYNOS_ASV_H + +enum { + EXYNOS_ASV_SUBSYS_ID_ARM, + EXYNOS_ASV_SUBSYS_ID_EGL = EXYNOS_ASV_SUBSYS_ID_ARM, + EXYNOS_ASV_SUBSYS_ID_KFC, + EXYNOS_ASV_SUBSYS_ID_INT, + EXYNOS_ASV_SUBSYS_ID_MIF, + EXYNOS_ASV_SUBSYS_ID_G3D, + EXYNOS_ASV_SUBSYS_ID_CAM, + EXYNOS_ASV_SUBSYS_ID_MAX +}; + +struct regmap; + +/* HPM, IDS values to select target group */ +struct asv_limit_entry { + unsigned int hpm; + unsigned int ids; +}; + +struct exynos_asv_table { + unsigned int num_rows; + unsigned int num_cols; + u32 *buf; +}; + +struct exynos_asv_subsys { + struct exynos_asv *asv; + const char *cpu_dt_compat; + int id; + struct exynos_asv_table table; + + unsigned int base_volt; + unsigned int offset_volt_h; + unsigned int offset_volt_l; +}; + +struct exynos_asv { + struct device *dev; + struct regmap *chipid_regmap; + struct exynos_asv_subsys subsys[2]; + + int (*opp_get_voltage)(struct exynos_asv_subsys *subs, int level, + unsigned int voltage); + unsigned int group; + unsigned int table; + + /* True if SG fields from PKG_ID register should be used */ + bool use_sg; + /* ASV bin read from DT */ + int of_bin; +}; + +static inline u32 __asv_get_table_entry(struct exynos_asv_table *table, + unsigned int row, unsigned int col) +{ + return table->buf[row * (table->num_cols) + col]; +} + +static inline u32 exynos_asv_opp_get_voltage(struct exynos_asv_subsys *subsys, + unsigned int level, unsigned int group) +{ + return __asv_get_table_entry(&subsys->table, level, group + 1); +} + +static inline u32 exynos_asv_opp_get_frequency(struct exynos_asv_subsys *subsys, + unsigned int level) +{ + return __asv_get_table_entry(&subsys->table, level, 0); +} + +#endif /* __LINUX_SOC_EXYNOS_ASV_H */ diff --git a/drivers/soc/samsung/exynos5422-asv.c b/drivers/soc/samsung/exynos5422-asv.c new file mode 100644 index 00000000000000..7982f2ca0f11b3 --- /dev/null +++ b/drivers/soc/samsung/exynos5422-asv.c @@ -0,0 +1,509 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Exynos 5422 SoC Adaptive Supply Voltage support + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "exynos-asv.h" + +#define ASV_GROUPS_NUM 14 +#define ASV_ARM_DVFS_NUM 20 +#define ASV_ARM_BIN2_DVFS_NUM 17 +#define ASV_KFC_DVFS_NUM 14 +#define ASV_KFC_BIN2_DVFS_NUM 12 + +/* + * This array is a set of 4 ASV data tables, first column of each ASV table + * contains frequency value in MHz and subsequent columns contain the CPU + * cluster's supply voltage values in uV. + * In order to create a set of OPPs for specific SoC revision one of the voltage + * columns (1...14) from one of the tables (0...3) is selected during + * initialization. There are separate ASV tables for the big (ARM) and little + * (KFC) CPU cluster. Only OPPs which are already defined in devicetree + * will be updated. + */ + +static const u32 asv_arm_table[][ASV_ARM_DVFS_NUM][ASV_GROUPS_NUM + 1] = { +{ + /* ARM 0, 1 */ + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 }, + { 2000, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1900, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000, + 1162500, 1150000, 1162500, 1150000, 1137500, 1125000, 1112500 }, + { 1800, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, + 1112500, 1100000, 1112500, 1100000, 1087500, 1075000, 1062500 }, + { 1700, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500, + 1075000, 1062500, 1075000, 1062500, 1050000, 1037500, 1025000 }, + { 1600, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000, + 1037500, 1025000, 1037500, 1025000, 1012500, 1000000, 987500 }, + { 1500, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 1000000, 987500, 975000, 962500, 950000 }, + { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 975000, 962500, 950000, 937500, 925000 }, + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 962500, 950000, 937500, 925000, 912500 }, + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 937500, 925000, 912500, 900000, 900000 }, + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* ARM 2 */ + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 }, + { 2000, 1312500, 1312500, 1312500, 1300000, 1275000, 1262500, 1250000, + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1900, 1262500, 1250000, 1250000, 1237500, 1212500, 1200000, 1187500, + 1175000, 1162500, 1175000, 1162500, 1150000, 1137500, 1125000 }, + { 1800, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, + 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000 }, + { 1700, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1087500, 1075000, 1062500, 1050000, 1037500 }, + { 1600, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000 }, + { 1500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 }, + { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, + 987500, 975000, 987500, 975000, 962500, 950000, 937500 }, + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 962500, 950000, 937500, 925000, 912500 }, + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 937500, 925000, 912500, 900000, 900000 }, + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* ARM 3 */ + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 }, + { 2000, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1900, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, + 1175000, 1162500, 1175000, 1162500, 1150000, 1137500, 1125000 }, + { 1800, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, + 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000 }, + { 1700, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1087500, 1075000, 1062500, 1050000, 1037500 }, + { 1600, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000 }, + { 1500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 }, + { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, + 987500, 975000, 987500, 975000, 962500, 950000, 937500 }, + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 962500, 950000, 937500, 925000, 912500 }, + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 937500, 925000, 912500, 900000, 900000 }, + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* ARM bin 2 */ + { 1800, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, + 1150000, 1137500, 1150000, 1137500, 1125000, 1112500, 1100000 }, + { 1700, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, + 1112500, 1100000, 1112500, 1100000, 1087500, 1075000, 1062500 }, + { 1600, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500, + 1075000, 1062500, 1075000, 1062500, 1050000, 1037500, 1025000 }, + { 1500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000, + 1037500, 1025000, 1037500, 1025000, 1012500, 1000000, 987500 }, + { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 }, + { 1300, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 1000000, 987500, 975000, 962500, 950000 }, + { 1200, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 975000, 962500, 950000, 937500, 925000 }, + { 1100, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 962500, + 950000, 937500, 950000, 937500, 925000, 912500, 900000 }, + { 1000, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, + 925000, 912500, 925000, 912500, 900000, 900000, 900000 }, + { 900, 987500, 975000, 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 800, 962500, 950000, 937500, 925000, 912500, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 700, 937500, 925000, 912500, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +} +}; + +static const u32 asv_kfc_table[][ASV_KFC_DVFS_NUM][ASV_GROUPS_NUM + 1] = { +{ + /* KFC 0, 1 */ + { 1500000, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000, + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1400000, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 }, + { 1300000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 }, + { 1200000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 }, + { 1100000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, + { 1000000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 }, + { 900000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, 912500, 900000 }, + { 800000, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000, 900000, 900000 }, + { 700000, 987500, 975000, 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600000, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* KFC 2 */ + { 1500, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000, + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 }, + { 1300, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 }, + { 1200, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 }, + { 1100, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, + { 1000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 }, + { 900, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, 912500, 900000 }, + { 800, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000, 900000, 900000 }, + { 700, 987500, 975000, 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 912500, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* KFC 3 */ + { 1500, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000, + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 }, + { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 }, + { 1300, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 }, + { 1200, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 }, + { 1100, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, + { 1000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 }, + { 900, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, 912500, 900000 }, + { 800, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000, 900000, 900000 }, + { 700, 987500, 975000, 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 600, 950000, 937500, 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 912500, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +}, { + /* KFC bin 2 */ + { 1300, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000, + 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500 }, + { 1200, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, + 1112500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500 }, + { 1100, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500, + 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000 }, + { 1000, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000, + 1037500, 1025000, 1012500, 1000000, 987500, 975000, 962500 }, + { 900, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 975000, 962500, 950000, 937500, 925000 }, + { 800, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 937500, 925000, 912500, 900000, 900000 }, + { 700, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, + 925000, 912500, 900000, 900000, 900000, 900000, 900000 }, + { 600, 975000, 962500, 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 500, 937500, 925000, 912500, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 400, 925000, 912500, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, +} +}; + +static const struct asv_limit_entry __asv_limits[ASV_GROUPS_NUM] = { + { 13, 55 }, + { 21, 65 }, + { 25, 69 }, + { 30, 72 }, + { 36, 74 }, + { 43, 76 }, + { 51, 78 }, + { 65, 80 }, + { 81, 82 }, + { 98, 84 }, + { 119, 87 }, + { 135, 89 }, + { 150, 92 }, + { 999, 999 }, +}; + +static int exynos5422_asv_get_group(struct exynos_asv *asv) +{ + unsigned int pkgid_reg, auxi_reg; + int hpm, ids, i; + + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PKG_ID, &pkgid_reg); + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_AUX_INFO, &auxi_reg); + + if (asv->use_sg) { + u32 sga = (pkgid_reg >> EXYNOS5422_SG_A_OFFSET) & + EXYNOS5422_SG_A_MASK; + + u32 sgb = (pkgid_reg >> EXYNOS5422_SG_B_OFFSET) & + EXYNOS5422_SG_B_MASK; + + if ((pkgid_reg >> EXYNOS5422_SG_BSIGN_OFFSET) & + EXYNOS5422_SG_BSIGN_MASK) + return sga + sgb; + else + return sga - sgb; + } + + hpm = (auxi_reg >> EXYNOS5422_TMCB_OFFSET) & EXYNOS5422_TMCB_MASK; + ids = (pkgid_reg >> EXYNOS5422_IDS_OFFSET) & EXYNOS5422_IDS_MASK; + + for (i = 0; i < ASV_GROUPS_NUM; i++) { + if (ids <= __asv_limits[i].ids) + break; + if (hpm <= __asv_limits[i].hpm) + break; + } + if (i < ASV_GROUPS_NUM) + return i; + + return 0; +} + +static int __asv_offset_voltage(unsigned int index) +{ + switch (index) { + case 1: + return 12500; + case 2: + return 50000; + case 3: + return 25000; + default: + return 0; + }; +} + +static void exynos5422_asv_offset_voltage_setup(struct exynos_asv *asv) +{ + struct exynos_asv_subsys *subsys; + unsigned int reg, value; + + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_AUX_INFO, ®); + + /* ARM offset voltage setup */ + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_ARM]; + + subsys->base_volt = 1000000; + + value = (reg >> EXYNOS5422_ARM_UP_OFFSET) & EXYNOS5422_ARM_UP_MASK; + subsys->offset_volt_h = __asv_offset_voltage(value); + + value = (reg >> EXYNOS5422_ARM_DN_OFFSET) & EXYNOS5422_ARM_DN_MASK; + subsys->offset_volt_l = __asv_offset_voltage(value); + + /* KFC offset voltage setup */ + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_KFC]; + + subsys->base_volt = 1000000; + + value = (reg >> EXYNOS5422_KFC_UP_OFFSET) & EXYNOS5422_KFC_UP_MASK; + subsys->offset_volt_h = __asv_offset_voltage(value); + + value = (reg >> EXYNOS5422_KFC_DN_OFFSET) & EXYNOS5422_KFC_DN_MASK; + subsys->offset_volt_l = __asv_offset_voltage(value); +} + +static int exynos5422_asv_opp_get_voltage(struct exynos_asv_subsys *subsys, + int level, unsigned int volt) +{ + unsigned int asv_volt; + + if (level >= subsys->table.num_rows) + return volt; + + asv_volt = exynos_asv_opp_get_voltage(subsys, level, + subsys->asv->group); + + if (volt > subsys->base_volt) + asv_volt += subsys->offset_volt_h; + else + asv_volt += subsys->offset_volt_l; + + return asv_volt; +} + +static unsigned int exynos5422_asv_parse_table(struct exynos_asv *asv, + unsigned int pkg_id) +{ + return (pkg_id >> EXYNOS5422_TABLE_OFFSET) & EXYNOS5422_TABLE_MASK; +} + +static bool exynos5422_asv_parse_bin2(struct exynos_asv *asv, + unsigned int pkg_id) +{ + return (pkg_id >> EXYNOS5422_BIN2_OFFSET) & EXYNOS5422_BIN2_MASK; +} + +static bool exynos5422_asv_parse_sg(struct exynos_asv *asv, + unsigned int pkg_id) +{ + return (pkg_id >> EXYNOS5422_USESG_OFFSET) & EXYNOS5422_USESG_MASK; +} + +int exynos5422_asv_init(struct exynos_asv *asv) +{ + struct exynos_asv_subsys *subsys; + unsigned int table_index; + unsigned int pkg_id; + bool bin2; + + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PKG_ID, &pkg_id); + + if (asv->of_bin == 2) { + bin2 = true; + asv->use_sg = false; + } else { + asv->use_sg = exynos5422_asv_parse_sg(asv, pkg_id); + bin2 = exynos5422_asv_parse_bin2(asv, pkg_id); + } + + asv->group = exynos5422_asv_get_group(asv); + asv->table = exynos5422_asv_parse_table(asv, pkg_id); + + exynos5422_asv_offset_voltage_setup(asv); + + if (bin2) { + table_index = 3; + } else { + if (asv->table == 2 || asv->table == 3) + table_index = asv->table - 1; + else + table_index = 0; + } + + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_ARM]; + subsys->cpu_dt_compat = "arm,cortex-a15"; + if (bin2) + subsys->table.num_rows = ASV_ARM_BIN2_DVFS_NUM; + else + subsys->table.num_rows = ASV_ARM_DVFS_NUM; + subsys->table.num_cols = ASV_GROUPS_NUM + 1; + subsys->table.buf = (u32 *)asv_arm_table[table_index]; + + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_KFC]; + subsys->cpu_dt_compat = "arm,cortex-a7"; + if (bin2) + subsys->table.num_rows = ASV_KFC_BIN2_DVFS_NUM; + else + subsys->table.num_rows = ASV_KFC_DVFS_NUM; + subsys->table.num_cols = ASV_GROUPS_NUM + 1; + subsys->table.buf = (u32 *)asv_kfc_table[table_index]; + + asv->opp_get_voltage = exynos5422_asv_opp_get_voltage; + + return 0; +} diff --git a/drivers/soc/samsung/exynos5422-asv.h b/drivers/soc/samsung/exynos5422-asv.h new file mode 100644 index 00000000000000..85218d2800fbe7 --- /dev/null +++ b/drivers/soc/samsung/exynos5422-asv.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Exynos 5422 SoC Adaptive Supply Voltage support + */ + +#ifndef __LINUX_SOC_EXYNOS5422_ASV_H +#define __LINUX_SOC_EXYNOS5422_ASV_H + +#include + +struct exynos_asv; + +#ifdef CONFIG_EXYNOS_ASV_ARM +int exynos5422_asv_init(struct exynos_asv *asv); +#else +static inline int exynos5422_asv_init(struct exynos_asv *asv) +{ + return -ENOTSUPP; +} +#endif + +#endif /* __LINUX_SOC_EXYNOS5422_ASV_H */ From 13610b81f7a08740873cfab353090d668ddc769d Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 16 Oct 2019 16:57:56 +0200 Subject: [PATCH 048/133] ODROID-XU4: ARM: EXYNOS: Enable exynos-asv driver for ARCH_EXYNOS Enable exynos-asv driver for Exynos 32-bit SoCs. Change-Id: Ifa8152915fda8f4c1c36dc11c96c8804ea6860dd Signed-off-by: Sylwester Nawrocki Signed-off-by: memeka --- arch/arm/mach-exynos/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 9dab1f50a02f83..4ef56571145bf5 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS select ARM_AMBA select ARM_GIC select COMMON_CLK_SAMSUNG + select EXYNOS_ASV select EXYNOS_CHIPID select EXYNOS_THERMAL select EXYNOS_PMU From 272199d2275f5cfb360ee268795be128055187e9 Mon Sep 17 00:00:00 2001 From: "k.konieczny@partner.samsung.com" Date: Tue, 8 Oct 2019 15:49:23 +0200 Subject: [PATCH 049/133] ODROID-XU4: devfreq: exynos-bus: workaround dev_pm_opp_set_rate() errors on Exynos5422/5800 SoCs Commit 4294a779bd8d ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()") introduced errors: exynos-bus: new bus device registered: soc:bus_wcore ( 84000 KHz ~ 400000 KHz) exynos-bus: new bus device registered: soc:bus_noc ( 67000 KHz ~ 100000 KHz) exynos-bus: new bus device registered: soc:bus_fsys_apb (100000 KHz ~ 200000 KHz) ... exynos-bus soc:bus_wcore: dev_pm_opp_set_rate: failed to find current OPP for freq 532000000 (-34) exynos-bus soc:bus_noc: dev_pm_opp_set_rate: failed to find current OPP for freq 111000000 (-34) exynos-bus soc:bus_fsys_apb: dev_pm_opp_set_rate: failed to find current OPP for freq 222000000 (-34) They are caused by incorrect PLL assigned to clock source, which results in clock rate outside of OPP range. Add workaround for this in exynos_bus_parse_of() by adjusting clock rate to those present in OPP. Fixes: 4294a779bd8d ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()") Change-Id: Ic07e2d68e0da2efa07cb81cc9b4f76d8ad15bd76 Reported-by: Krzysztof Kozlowski Signed-off-by: Kamil Konieczny Signed-off-by: memeka --- drivers/devfreq/exynos-bus.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c index c832673273a28d..37bd34d5625b49 100644 --- a/drivers/devfreq/exynos-bus.c +++ b/drivers/devfreq/exynos-bus.c @@ -243,7 +243,7 @@ static int exynos_bus_parse_of(struct device_node *np, { struct device *dev = bus->dev; struct dev_pm_opp *opp; - unsigned long rate; + unsigned long rate, opp_rate; int ret; /* Get the clock to provide each bus with source clock */ @@ -267,13 +267,21 @@ static int exynos_bus_parse_of(struct device_node *np, } rate = clk_get_rate(bus->clk); - - opp = devfreq_recommended_opp(dev, &rate, 0); + opp_rate = rate; + opp = devfreq_recommended_opp(dev, &opp_rate, 0); if (IS_ERR(opp)) { dev_err(dev, "failed to find dev_pm_opp\n"); ret = PTR_ERR(opp); goto err_opp; } + /* + * FIXME: U-boot leaves clock source at incorrect PLL, this results + * in clock rate outside defined OPP rate. Work around this bug by + * setting clock rate to recommended one. + */ + if (rate > opp_rate) + clk_set_rate(bus->clk, opp_rate); + bus->curr_freq = dev_pm_opp_get_freq(opp); dev_pm_opp_put(opp); From 06aca826d8079a7745fb6189858267df38f49ec4 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Sun, 12 Jul 2015 18:41:20 +0530 Subject: [PATCH 050/133] ODROID-XU4: regulator: s2mps11: call shutdown function to poweroff Added .shutdown function to s2mps11 to help poweroff the board successfully. The device driver clears the register to turn off the PMIC. s2mps11-pmic: S2MPS11_REG_CTRL1 reg value 16:00000000000000000000000000010000 Console log. * Unmounting temporary filesystems... [ OK ] * Deactivating swap... [ OK ] * Unmounting local filesystems... [ OK ] * Will now halt [ 209.020280] reboot: Power down [ 209.122039] Power down failed, please power off system manually. Change-Id: If6ea0dec154b00ceeaaddbac393c67dc35c26279 Signed-off-by: Anand Moon Signed-off-by: memeka Signed-off-by: Marian Mihailescu --- drivers/regulator/s2mps11.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 5bc00884cf512d..3e449092e1fbe0 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1244,6 +1244,31 @@ static int s2mps11_pmic_probe(struct platform_device *pdev) return ret; } +static void s2mps11_pmic_shutdown(struct platform_device *pdev) +{ + struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); + unsigned int reg_val, ret; + + ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_CTRL1, ®_val); + if (ret < 0) { + dev_crit(&pdev->dev, "could not read S2MPS11_REG_CTRL1 value\n"); + } else { + /* + * s2mps11-pmic: S2MPS11_REG_CTRL1 reg value + * is 00000000000000000000000000010000 + * clear the S2MPS11_REG_CTRL1 0x10 value to shutdown. + */ + if (reg_val & BIT(4)) { + ret = regmap_update_bits(iodev->regmap_pmic, + S2MPS11_REG_CTRL1, + BIT(4), BIT(0)); + if (ret) + dev_crit(&pdev->dev, + "could not write S2MPS11_REG_CTRL1 value\n"); + } + } +} + static const struct platform_device_id s2mps11_pmic_id[] = { { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, @@ -1259,6 +1284,7 @@ static struct platform_driver s2mps11_pmic_driver = { .name = "s2mps11-pmic", }, .probe = s2mps11_pmic_probe, + .shutdown = s2mps11_pmic_shutdown, .id_table = s2mps11_pmic_id, }; From 3dc73d4f29c6ce1ce7c2d3293d3ea015d57a0837 Mon Sep 17 00:00:00 2001 From: memeka Date: Fri, 18 Jan 2019 14:36:21 +1030 Subject: [PATCH 051/133] ODROID-XU4: regulator: s2mps11: add ethernet power reset in shutdown function Ethernet device cannot be detected on warm boot sometimes. This patch is to add the power reset routines for ethernet device using PMIC. Then ethernet device can be reset hardware-wise. Change-Id: Iffbe2966da7e4679f63b91ab79241167391792df Signed-off-by: Brian Kim Signed-off-by: Marian Mihailescu --- drivers/regulator/s2mps11.c | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 3e449092e1fbe0..d9804787d83590 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1118,6 +1118,57 @@ static const struct regulator_desc s2mpu02_regulators[] = { regulator_desc_s2mpu02_buck7(7), }; +static int s2mps11_pmic_ethonoff(struct platform_device *pdev, bool onoff) +{ + struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); + unsigned int reg_val = 0; + int ret = 0; + + ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, ®_val); + if (ret) { + dev_err(&pdev->dev, "failed to read S2MPS11_REG_L15CTRL value\n"); + return ret; + } + + ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, ®_val); + if (ret) { + dev_err(&pdev->dev, "failed to read S2MPS11_REG_L17CTRL value\n"); + return ret; + } + + if (onoff) { + /* ETH VDD0 ON */ + ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, 0xFF, 0x72); + if (ret) { + dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL15 register\n"); + return ret; + } + + /* ETH VDD1 ON */ + ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, 0xFF, 0x72); + if (ret) { + dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL17 register\n"); + return ret; + } + } else { + /* ETH VDD0 OFF */ + ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L15CTRL, 0x3F, 0x00); + if (ret) { + dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL15 register\n"); + return ret; + } + + /* ETH VDD1 OFF */ + ret = regmap_update_bits(iodev->regmap_pmic, S2MPS11_REG_L17CTRL, 0x3F, 0x00); + if (ret) { + dev_err(&pdev->dev, "cannot update S2MPS11 LDO CTRL17 register\n"); + return ret; + } + } + + return ret; +} + static int s2mps11_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); @@ -1267,6 +1318,9 @@ static void s2mps11_pmic_shutdown(struct platform_device *pdev) "could not write S2MPS11_REG_CTRL1 value\n"); } } + s2mps11_pmic_ethonoff(pdev, false); + mdelay(10); + s2mps11_pmic_ethonoff(pdev, true); } static const struct platform_device_id s2mps11_pmic_id[] = { From 322727a11eb007faf06c3527bc33c6864da93933 Mon Sep 17 00:00:00 2001 From: Marian Mihailescu Date: Thu, 14 Nov 2019 12:19:37 +1030 Subject: [PATCH 052/133] ODROID-XU4: fix eMMC clock settings Change-Id: Ifa5b2f4730d96071f11931f4719c86c624f60194 --- drivers/mmc/host/dw_mmc-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index 0280d394a32ab4..7088e39de5d28c 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -61,7 +61,7 @@ /* Fixed clock divider */ #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 -#define HS400_FIXED_CIU_CLK_DIV 1 +#define HS400_FIXED_CIU_CLK_DIV 2 /* Minimal required clock frequency for cclkin, unit: HZ */ #define EXYNOS_CCLKIN_MIN 50000000 From 915454a7b78aaba62b60ff87c8c236d3c284295d Mon Sep 17 00:00:00 2001 From: memeka Date: Mon, 28 Oct 2019 12:26:54 +1030 Subject: [PATCH 053/133] ODROID-XU4: config: add default config for odroid-xu4 Change-Id: If702a43a1cf8cdc1b322f925c8f8061ed106f1d2 --- arch/arm/configs/odroidxu4_defconfig | 5454 ++++++++++++++++++++++++++ 1 file changed, 5454 insertions(+) create mode 100644 arch/arm/configs/odroidxu4_defconfig diff --git a/arch/arm/configs/odroidxu4_defconfig b/arch/arm/configs/odroidxu4_defconfig new file mode 100644 index 00000000000000..118d87fb113353 --- /dev/null +++ b/arch/arm/configs/odroidxu4_defconfig @@ -0,0 +1,5454 @@ +# +# Compiler: gcc (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70400 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="odroid" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_DMA_USE_IOMMU=y +CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_PGTABLE_LEVELS=2 + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# end of Multiple platform selection + +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_ASPEED is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_DIGICOLOR is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_S5P_DEV_MFC=y +# CONFIG_ARCH_EXYNOS3 is not set +# CONFIG_ARCH_EXYNOS4 is not set +CONFIG_ARCH_EXYNOS5=y + +# +# EXYNOS SoCs +# +# CONFIG_SOC_EXYNOS5250 is not set +# CONFIG_SOC_EXYNOS5260 is not set +# CONFIG_SOC_EXYNOS5410 is not set +CONFIG_SOC_EXYNOS5420=y +CONFIG_SOC_EXYNOS5800=y +CONFIG_EXYNOS_MCPM=y +CONFIG_EXYNOS_CPU_SUSPEND=y +CONFIG_PLAT_SAMSUNG=y + +# +# Samsung Common options +# + +# +# Boot options +# + +# +# Power management +# +# end of Samsung Common options + +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MILBEAUT is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NPCM is not set + +# +# TI OMAP/AM/DM/DRA Family +# +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_DRA7XX is not set +# end of TI OMAP/AM/DM/DRA Family + +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_TANGO is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_SPECTRE=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_KUSER_HELPERS=y +# CONFIG_VDSO is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +# CONFIG_CACHE_L2X0_PMU is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_DEBUG_ALIGN_RODATA=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_ARM_ERRATA_643719=y +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_818325_852422 is not set +# CONFIG_ARM_ERRATA_821420 is not set +# CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_857271 is not set +# CONFIG_ARM_ERRATA_852421 is not set +# CONFIG_ARM_ERRATA_852423 is not set +# CONFIG_ARM_ERRATA_857272 is not set +# end of System Type + +# +# Bus support +# +# CONFIG_ARM_ERRATA_814220 is not set +# end of Bus support + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_MCPM=y +CONFIG_BIG_LITTLE=y +# CONFIG_BL_SWITCHER is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +CONFIG_ARM_PSCI=y +CONFIG_ARCH_NR_GPIO=512 +CONFIG_HZ_FIXED=0 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_200 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_ARM_PATCH_IDIV=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARM_MODULE_PLTS=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_SECCOMP=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_XEN is not set +# end of Kernel Features + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="s5p_mfc.mem=16M" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set +# end of Boot options + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_QORIQ_CPUFREQ is not set +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set + +# +# ARM CPU Idle Drivers +# +# CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARM_PSCI_CPUIDLE is not set +# CONFIG_ARM_BIG_LITTLE_CPUIDLE is not set +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_EXYNOS_CPUIDLE=y +# end of ARM CPU Idle Drivers + +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y +# end of CPU Idle +# end of CPU Power Management + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# end of Floating point emulation + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# end of Power management options + +# +# Firmware Drivers +# +# CONFIG_TRUSTED_FOUNDATIONS is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +# CONFIG_CRYPTO_SHA1_ARM_CE is not set +# CONFIG_CRYPTO_SHA2_ARM_CE is not set +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +# CONFIG_CRYPTO_AES_ARM is not set +CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_CRYPTO_AES_ARM_CE is not set +# CONFIG_CRYPTO_GHASH_ARM_CE is not set +# CONFIG_CRYPTO_CRC32_ARM_CE is not set +CONFIG_CRYPTO_CHACHA20_NEON=m +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +CONFIG_VIRTUALIZATION=y +CONFIG_VHOST_NET=m +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_REFCOUNT_FULL=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_ELF_FDPIC is not set +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_ZPOOL=m +CONFIG_ZBUD=m +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=m +CONFIG_PGTABLE_MAPPING=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FRAME_VECTOR=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +CONFIG_TCP_CONG_VENO=m +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=y +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +# CONFIG_NF_TABLES_INET is not set +# CONFIG_NF_TABLES_NETDEV is not set +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=y +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=y +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_FO is not set +# CONFIG_IP_VS_OVF is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_MH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_NFCT=y + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +# CONFIG_NF_TABLES_IPV4 is not set +# CONFIG_NF_TABLES_ARP is not set +CONFIG_NF_DUP_IPV4=m +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +# CONFIG_NF_TABLES_IPV6 is not set +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_TABLES_BRIDGE is not set +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_L2TP=m +# CONFIG_L2TP_DEBUGFS is not set +# CONFIG_L2TP_V3 is not set +CONFIG_STP=y +CONFIG_MRP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_MQPRIO=m +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +CONFIG_NET_CLS_FW=m +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_BATMAN_ADV_NC is not set +CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_DEBUGFS is not set +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV_SYSFS=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_MPLS_ROUTING is not set +CONFIG_NET_NSH=m +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_LEDS=y +CONFIG_BT_DEBUGFS=y + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_BT_MTKSDIO is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_STREAM_PARSER=y +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SOCK_MSG=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PORT_CTRL=y +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_SIMPLE_PM_BUS is not set +# CONFIG_VEXPRESS_CONFIG is not set +# end of Bus devices + +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_ZRAM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# end of Intel MIC & related support + +# CONFIG_ECHO is not set +# CONFIG_MISC_RTSX_USB is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_QORIQ is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=y +CONFIG_DM_PERSISTENT_DATA=y +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +CONFIG_DM_THIN_PROVISIONING=y +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +CONFIG_VXLAN=y +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_AURORA=y +# CONFIG_AURORA_NB8800 is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +# CONFIG_SYSTEMPORT is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CIRRUS=y +# CONFIG_CS89x0 is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_EZCHIP=y +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_FARADAY=y +# CONFIG_FTMAC100 is not set +# CONFIG_FTGMAC100 is not set +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HISI_FEMAC is not set +# CONFIG_HIP04_ETH is not set +# CONFIG_HNS is not set +# CONFIG_HNS_DSAF is not set +# CONFIG_HNS_ENET is not set +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +# CONFIG_ADIN_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=y +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=y +CONFIG_USB_NET_CDC_SUBSET=y +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=y +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_USB=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +CONFIG_INPUT_MATRIXKMAP=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +CONFIG_KEYBOARD_SAMSUNG=y +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +CONFIG_MOUSE_CYAPA=y +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +CONFIG_TOUCHSCREEN_MMS114=y +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set +CONFIG_INPUT_MAX77693_HAPTIC=y +CONFIG_INPUT_MAX8997_HAPTIC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS_4=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_HW_RANDOM_EXYNOS=y +# CONFIG_RAW_DRIVER is not set +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +# CONFIG_TCG_TIS is not set +# CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +CONFIG_TCG_TIS_I2C_INFINEON=y +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +# CONFIG_TCG_VTPM_PROXY is not set +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_EXYNOS5=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +CONFIG_HAVE_S3C2410_I2C=y +CONFIG_I2C_S3C2410=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MEM is not set + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +CONFIG_SPI_GPIO=y +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_ROCKCHIP is not set +CONFIG_SPI_S3C64XX=y +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_SAMSUNG=y +CONFIG_PINCTRL_EXYNOS=y +CONFIG_PINCTRL_EXYNOS_ARM=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set +CONFIG_GPIO_WM8994=y +# end of MFD GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_VERSATILE is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_LEGO_EV3 is not set +CONFIG_BATTERY_SBS=y +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +CONFIG_BATTERY_MAX17040=y +CONFIG_BATTERY_MAX17042=y +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +CONFIG_CHARGER_MAX14577=y +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +CONFIG_CHARGER_MAX77693=y +CONFIG_CHARGER_MAX8997=y +CONFIG_CHARGER_MAX8998=y +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_CHARGER_TPS65090=y +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +CONFIG_SENSORS_LM90=y +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +CONFIG_SENSORS_NTC_THERMISTOR=y +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +CONFIG_SENSORS_INA2XX=y +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +CONFIG_CPU_THERMAL=y +# CONFIG_CLOCK_THERMAL is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_THERMAL_EMULATION=y +# CONFIG_THERMAL_MMIO is not set +# CONFIG_QORIQ_THERMAL is not set + +# +# Samsung thermal drivers +# +CONFIG_EXYNOS_THERMAL=y +# end of Samsung thermal drivers + +# CONFIG_GENERIC_ADC_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_FTWDT010_WATCHDOG is not set +CONFIG_HAVE_S3C2410_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +CONFIG_MFD_MAX14577=y +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX77693=y +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +CONFIG_MFD_SEC_CORE=y +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +CONFIG_MFD_TPS65090=y +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=y +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +CONFIG_REGULATOR_MAX14577=y +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8952=y +# CONFIG_REGULATOR_MAX8973 is not set +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX8998=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_MAX77693=y +CONFIG_REGULATOR_MAX77802=y +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_S2MPA01=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_S5M8767=y +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65090=y +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VCTRL is not set +CONFIG_REGULATOR_WM8994=y +CONFIG_CEC_CORE=y +CONFIG_CEC_NOTIFIER=y +# CONFIG_RC_CORE is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_V4L2_MEM2MEM_DEV=y +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L2_FWNODE=m + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set + +# +# USB HDMI CEC adapters +# +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_ASPEED is not set +# CONFIG_VIDEO_MUX is not set +CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m +CONFIG_VIDEO_EXYNOS4_IS_COMMON=m +CONFIG_VIDEO_S5P_FIMC=m +CONFIG_VIDEO_S5P_MIPI_CSIS=m +CONFIG_VIDEO_EXYNOS4_FIMC_IS=m +CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y +# CONFIG_VIDEO_XILINX is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_SAMSUNG_S5P_G2D is not set +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=y +# CONFIG_VIDEO_SH_VEU is not set +CONFIG_V4L_TEST_DRIVERS=y +# CONFIG_VIDEO_VIMC is not set +# CONFIG_VIDEO_VIVID is not set +# CONFIG_VIDEO_VIM2M is not set +# CONFIG_VIDEO_VICODEC is not set +CONFIG_CEC_PLATFORM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_CEC=y + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=y + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y + +# +# I2C drivers hidden by 'Autoselect ancillary drivers' +# + +# +# Audio decoders, processors and mixers +# + +# +# RDS decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# Video encoders +# + +# +# Camera sensor devices +# + +# +# Lens drivers +# + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Audio/Video compression chips +# + +# +# SDR tuner chips +# + +# +# Miscellaneous helper chips +# + +# +# SPI drivers hidden by 'Autoselect ancillary drivers' +# + +# +# Media SPI Adapters +# +# end of Media SPI Adapters + +# +# DVB Frontend drivers hidden by 'Autoselect ancillary drivers' +# + +# +# Tools to develop new frontends +# + +# +# Graphics support +# +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +# +# ACP (Audio CoProcessor) Configuration +# +# end of ACP (Audio CoProcessor) Configuration + +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_EXYNOS=y + +# +# CRTCs +# +CONFIG_DRM_EXYNOS_FIMD=y +# CONFIG_DRM_EXYNOS5433_DECON is not set +# CONFIG_DRM_EXYNOS7_DECON is not set +CONFIG_DRM_EXYNOS_MIXER=y +# CONFIG_DRM_EXYNOS_VIDI is not set + +# +# Encoders and Bridges +# +CONFIG_DRM_EXYNOS_DPI=y +CONFIG_DRM_EXYNOS_DSI=y +CONFIG_DRM_EXYNOS_DP=y +CONFIG_DRM_EXYNOS_HDMI=y + +# +# Sub-drivers +# +# CONFIG_DRM_EXYNOS_G2D is not set +# CONFIG_DRM_EXYNOS_FIMC is not set +# CONFIG_DRM_EXYNOS_ROTATOR is not set +# CONFIG_DRM_EXYNOS_SCALER is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_ARMADA is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_OMAP is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_FSL_DCU is not set +# CONFIG_DRM_STM is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_LVDS is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +CONFIG_DRM_PANEL_SAMSUNG_LD9040=y +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_DUMB_VGA_DAC is not set +# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_NXP_PTN3460=y +CONFIG_DRM_PARADE_PS8622=y +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +CONFIG_DRM_SII9234=y +# CONFIG_DRM_THINE_THC63LVD1024 is not set +CONFIG_DRM_TOSHIBA_TC358764=y +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +CONFIG_DRM_ANALOGIX_DP=y +# CONFIG_DRM_I2C_ADV7511 is not set +# end of Display Interface Bridges + +# CONFIG_DRM_STI is not set +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_TVE200 is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_MCDE is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# ARM GPU Configuration +# +CONFIG_MALI_MIDGARD=y +# CONFIG_MALI_GATOR_SUPPORT is not set +# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set +CONFIG_MALI_DEVFREQ=y +CONFIG_MALI_DMA_FENCE=y +CONFIG_MALI_PLATFORM_NAME="devicetree" +CONFIG_MALI_EXPERT=y +# CONFIG_MALI_CORESTACK is not set +# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set +# CONFIG_MALI_DEBUG is not set +# CONFIG_MALI_FENCE_DEBUG is not set +# CONFIG_MALI_NO_MALI is not set +# CONFIG_MALI_TRACE_TIMELINE is not set +# CONFIG_MALI_SYSTEM_TRACE is not set +# CONFIG_MALI_2MB_ALLOC is not set +# CONFIG_MALI_PWRSOFT_765 is not set +# CONFIG_MALI_KUTF is not set +# end of ARM GPU Configuration + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# HD-Audio +# +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=64 +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SAMSUNG_PCM=y +# CONFIG_SND_SAMSUNG_SPDIF is not set +CONFIG_SND_SAMSUNG_I2S=y +CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=y +# CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF is not set +CONFIG_SND_SOC_SMDK_WM8994_PCM=y +CONFIG_SND_SOC_SNOW=y +CONFIG_SND_SOC_ODROID=y +# CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +CONFIG_SND_SOC_WM_HUBS=y +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +CONFIG_SND_SOC_MAX98090=y +CONFIG_SND_SOC_MAX98095=y +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +CONFIG_SND_SOC_WM8994=y +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +# CONFIG_SND_AUDIO_GRAPH_CARD is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_U2FZERO is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_EXYNOS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_EXYNOS=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_HSIC_USB3503=y +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +# CONFIG_USB_CONFIGFS is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +# CONFIG_PWRSEQ_SD8787 is not set +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=16 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PLTFM is not set +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +# CONFIG_MMC_SPI is not set +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_DW_BLUEFIELD is not set +CONFIG_MMC_DW_EXYNOS=y +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77693=y +CONFIG_LEDS_MAX8997=y +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_MAX8998=y +CONFIG_RTC_DRV_MAX8997=y +CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +CONFIG_RTC_DRV_S5M=y +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +CONFIG_HAVE_S3C_RTC=y +CONFIG_RTC_DRV_S3C=y +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +CONFIG_PL330_DMA=y +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_CLK_HSDK is not set +CONFIG_COMMON_CLK_MAX77686=y +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +CONFIG_COMMON_CLK_S2MPS11=y +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_SAMSUNG=y +CONFIG_EXYNOS_AUDSS_CLK_CON=y +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_CLKSRC_EXYNOS_MCT=y +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_OF_IOMMU=y +CONFIG_EXYNOS_IOMMU=y +# CONFIG_EXYNOS_IOMMU_DEBUG is not set +# CONFIG_ARM_SMMU is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +CONFIG_SOC_SAMSUNG=y +CONFIG_EXYNOS_ASV=y +CONFIG_EXYNOS_ASV_ARM=y +CONFIG_EXYNOS_CHIPID=y +CONFIG_EXYNOS_PMU=y +CONFIG_EXYNOS_PMU_ARM_DRIVERS=y +CONFIG_EXYNOS_PM_DOMAINS=y +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y +CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +CONFIG_EXTCON_MAX14577=y +# CONFIG_EXTCON_MAX3355 is not set +CONFIG_EXTCON_MAX77693=y +CONFIG_EXTCON_MAX8997=y +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_MEMORY=y +CONFIG_DDR=y +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_PL353_SMC=y +CONFIG_SAMSUNG_MC=y +CONFIG_EXYNOS5422_DMC=y +CONFIG_EXYNOS_SROM=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +# CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_KFIFO_BUF=y +# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_SW_DEVICE is not set +# CONFIG_IIO_SW_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7124 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_ENVELOPE_DETECTOR is not set +CONFIG_EXYNOS_ADC=y +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +# CONFIG_SD_ADC_MODULATOR is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set +# end of Analog to digital converters + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +# end of Amplifiers + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set +# CONFIG_VZ89X is not set +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +# end of Hid Sensor IIO Common + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# end of IIO dummy driver + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set +# end of Inertial measurement units + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM3605 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors + +# +# Magnetometer sensors +# +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +# CONFIG_IIO_MUX is not set +# end of Multiplexers + +# +# Inclinometer sensors +# +# end of Inclinometer sensors + +# +# Triggers - standalone +# +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Digital potentiometers +# +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set +# end of Digital potentiometers + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set +# end of Digital potentiostats + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +# CONFIG_DPS310 is not set +# CONFIG_HP03 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SAMSUNG=y + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_AL_FIC is not set +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_EXYNOS_DP_VIDEO=y +CONFIG_PHY_EXYNOS_MIPI_VIDEO=y +# CONFIG_PHY_EXYNOS_PCIE is not set +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_PHY_EXYNOS5250_USB2=y +CONFIG_PHY_EXYNOS5_USBDRD=y +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# end of Performance monitor support + +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MEMFD_CREATE=y +# CONFIG_CONFIGFS_FS is not set +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +CONFIG_HFSPLUS_FS=y +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +# CONFIG_CIFS_POSIX is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_ROOT is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_TRUSTED_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=m +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_SIMD=m + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECRDSA is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +CONFIG_CRYPTO_XTS=m +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=y + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_CHACHA20=m +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_LZO=m +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_LZ4=m +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_EXYNOS_RNG=y +CONFIG_CRYPTO_DEV_S5P=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +CONFIG_FONT_7x14=y +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_TER16x32 is not set +CONFIG_SG_POOL=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_DYNAMIC_DEBUG=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# end of Compile-time checks and compiler options + +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set + +# +# Debug Lockups and Hangs +# +# end of Debug Lockups and Hangs + +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +CONFIG_DEBUG_BUGVERBOSE=y + +# +# RCU Debugging +# +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# end of RCU Debugging + +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_PREEMPTIRQ_EVENTS is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITFIELD is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_MEMTEST is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UNWINDER_ARM=y +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_CORESIGHT is not set +# end of Kernel hacking From b6a3b5dac2ef8afb49d74fc723533d4f6efd52b9 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Mon, 2 Dec 2019 17:21:21 +0900 Subject: [PATCH 054/133] ODROID-XU4: ODROID-XU4: Replace defconfig with a ported one from 4.14.y Original config contents from @rooted. Signed-off-by: Yang Deokgyu Change-Id: Ic49dc77fbbeff490f4995a87d633d83374782447 --- arch/arm/configs/odroidxu4_defconfig | 2913 ++++++++++++++++++-------- 1 file changed, 2089 insertions(+), 824 deletions(-) diff --git a/arch/arm/configs/odroidxu4_defconfig b/arch/arm/configs/odroidxu4_defconfig index 118d87fb113353..59f40acfc2287d 100644 --- a/arch/arm/configs/odroidxu4_defconfig +++ b/arch/arm/configs/odroidxu4_defconfig @@ -1,8 +1,12 @@ +# Automatically generated file; DO NOT EDIT. +# Linux/arm 5.4.0 Kernel Configuration # -# Compiler: gcc (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1) 7.4.0 + +# +# Compiler: gcc (Debian 8.2.0-1) 8.2.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70400 +CONFIG_GCC_VERSION=80200 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y @@ -29,7 +33,7 @@ CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set -CONFIG_DEFAULT_HOSTNAME="odroid" +CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -37,8 +41,9 @@ CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set -# CONFIG_AUDIT is not set +CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y # # IRQ subsystem @@ -55,11 +60,12 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y @@ -76,19 +82,25 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem -CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -# CONFIG_TASKSTATS is not set +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y # CONFIG_PSI is not set # end of CPU/Task time and stats accounting @@ -97,10 +109,11 @@ CONFIG_CPU_ISOLATION=y # # RCU Subsystem # -CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -116,6 +129,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # +# CONFIG_UCLAMP_TASK is not set # end of Scheduler features CONFIG_CGROUPS=y @@ -130,8 +144,8 @@ CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_PIDS=y -# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_PIDS is not set +CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_PROC_PID_CPUSET=y @@ -149,9 +163,10 @@ CONFIG_NET_NS=y # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set -# CONFIG_RELAY is not set +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INITRAMFS_FORCE is not set CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y @@ -212,7 +227,7 @@ CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set CONFIG_SLUB_CPU_PARTIAL=y CONFIG_SYSTEM_DATA_VERIFICATION=y -# CONFIG_PROFILING is not set +CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup @@ -276,16 +291,19 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_DIGICOLOR is not set CONFIG_ARCH_EXYNOS=y CONFIG_S5P_DEV_MFC=y -# CONFIG_ARCH_EXYNOS3 is not set -# CONFIG_ARCH_EXYNOS4 is not set +CONFIG_ARCH_EXYNOS3=y +CONFIG_ARCH_EXYNOS4=y CONFIG_ARCH_EXYNOS5=y # # EXYNOS SoCs # -# CONFIG_SOC_EXYNOS5250 is not set -# CONFIG_SOC_EXYNOS5260 is not set -# CONFIG_SOC_EXYNOS5410 is not set +CONFIG_SOC_EXYNOS3250=y +CONFIG_CPU_EXYNOS4210=y +CONFIG_SOC_EXYNOS4412=y +CONFIG_SOC_EXYNOS5250=y +CONFIG_SOC_EXYNOS5260=y +CONFIG_SOC_EXYNOS5410=y CONFIG_SOC_EXYNOS5420=y CONFIG_SOC_EXYNOS5800=y CONFIG_EXYNOS_MCPM=y @@ -375,12 +393,12 @@ CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y # CONFIG_CPU_BIG_ENDIAN is not set # CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_CPU_SPECTRE=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_KUSER_HELPERS=y -# CONFIG_VDSO is not set +CONFIG_VDSO=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y @@ -427,7 +445,7 @@ CONFIG_HAVE_SMP=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_ARM_CPU_TOPOLOGY=y -# CONFIG_SCHED_MC is not set +CONFIG_SCHED_MC=y # CONFIG_SCHED_SMT is not set CONFIG_HAVE_ARM_SCU=y CONFIG_HAVE_ARM_ARCH_TIMER=y @@ -441,7 +459,7 @@ CONFIG_VMSPLIT_3G=y CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_NR_CPUS=8 CONFIG_HOTPLUG_CPU=y -CONFIG_ARM_PSCI=y +# CONFIG_ARM_PSCI is not set CONFIG_ARCH_NR_GPIO=512 CONFIG_HZ_FIXED=0 # CONFIG_HZ_100 is not set @@ -463,12 +481,12 @@ CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARM_MODULE_PLTS=y +# CONFIG_ARM_MODULE_PLTS is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set CONFIG_SECCOMP=y -CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set # end of Kernel Features @@ -483,14 +501,13 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y CONFIG_CMDLINE="s5p_mfc.mem=16M" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_CMDLINE_EXTEND=y # CONFIG_CMDLINE_FORCE is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y +# CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set @@ -514,11 +531,11 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers @@ -541,9 +558,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y # ARM CPU Idle Drivers # # CONFIG_ARM_CPUIDLE is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set # CONFIG_ARM_BIG_LITTLE_CPUIDLE is not set -# CONFIG_ARM_HIGHBANK_CPUIDLE is not set CONFIG_ARM_EXYNOS_CPUIDLE=y # end of ARM CPU Idle Drivers @@ -575,7 +590,10 @@ CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y -# CONFIG_PM_DEBUG is not set +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y # CONFIG_APM_EMULATION is not set CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y @@ -594,8 +612,6 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y # # CONFIG_TRUSTED_FOUNDATIONS is not set CONFIG_HAVE_ARM_SMCCC=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set # CONFIG_GOOGLE_FIRMWARE is not set # @@ -607,27 +623,24 @@ CONFIG_ARM_PSCI_FW=y CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m -# CONFIG_CRYPTO_SHA1_ARM_CE is not set -# CONFIG_CRYPTO_SHA2_ARM_CE is not set +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m CONFIG_CRYPTO_SHA256_ARM=m CONFIG_CRYPTO_SHA512_ARM=m -# CONFIG_CRYPTO_AES_ARM is not set +CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m -# CONFIG_CRYPTO_AES_ARM_CE is not set -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -# CONFIG_CRYPTO_CRC32_ARM_CE is not set +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m # CONFIG_CRYPTO_NHPOLY1305_NEON is not set -CONFIG_VIRTUALIZATION=y -CONFIG_VHOST_NET=m -CONFIG_VHOST=m -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +# CONFIG_VIRTUALIZATION is not set # # General architecture-dependent options # -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y +# CONFIG_OPROFILE is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set @@ -702,7 +715,7 @@ CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set @@ -714,16 +727,18 @@ CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_ZONED=y CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_DEV_THROTTLING_LOW=y # CONFIG_BLK_CMDLINE_PARSER is not set -# CONFIG_BLK_WBT is not set +CONFIG_BLK_WBT=y # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +CONFIG_BLK_WBT_MQ=y CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y # CONFIG_BLK_SED_OPAL is not set # @@ -763,12 +778,9 @@ CONFIG_BFQ_GROUP_IOSCHED=y # CONFIG_BFQ_CGROUP_DEBUG is not set # end of IO Schedulers +CONFIG_PADATA=y CONFIG_ASN1=y -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y @@ -786,7 +798,7 @@ CONFIG_BINFMT_SCRIPT=y CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats @@ -809,12 +821,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_CMA=y # CONFIG_CMA_DEBUGFS is not set CONFIG_CMA_AREAS=7 -CONFIG_ZPOOL=m -CONFIG_ZBUD=m -CONFIG_Z3FOLD=m -CONFIG_ZSMALLOC=m +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +CONFIG_ZSMALLOC=y CONFIG_PGTABLE_MAPPING=y -# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_STAT=y CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_FRAME_VECTOR=y @@ -824,36 +835,36 @@ CONFIG_FRAME_VECTOR=y CONFIG_NET=y CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_DIAG is not set +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y CONFIG_UNIX_SCM=y -CONFIG_UNIX_DIAG=y -CONFIG_TLS=y -CONFIG_TLS_DEVICE=y +CONFIG_UNIX_DIAG=m +# CONFIG_TLS is not set CONFIG_XFRM=y -CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y -# CONFIG_XFRM_USER is not set +CONFIG_XFRM_USER=m # CONFIG_XFRM_INTERFACE is not set -# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_MIGRATE=y -# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y -# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -861,28 +872,29 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IP_TUNNEL=m CONFIG_NET_IPGRE=m -# CONFIG_NET_IPGRE_BROADCAST is not set +CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -# CONFIG_IP_PIMSM_V1 is not set -# CONFIG_IP_PIMSM_V2 is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=m -CONFIG_NET_UDP_TUNNEL=y -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_ESP_OFFLOAD is not set +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_RAW_DIAG is not set CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=m @@ -890,44 +902,54 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m CONFIG_TCP_CONG_HSTCP=m -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_NV is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_LP is not set +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m CONFIG_TCP_CONG_VENO=m -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -# CONFIG_TCP_CONG_DCTCP is not set -# CONFIG_TCP_CONG_CDG is not set -# CONFIG_TCP_CONG_BBR is not set +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_IPV6_ILA is not set -# CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESP_OFFLOAD is not set +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_GRE is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m # # Core Netfilter Configuration @@ -940,7 +962,7 @@ CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m -CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_COMMON=m # CONFIG_NF_LOG_NETDEV is not set CONFIG_NETFILTER_CONNCOUNT=m @@ -952,50 +974,57 @@ CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_LABELS=y CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_FTP is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_IRC is not set -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_SNMP is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_SET=m +# CONFIG_NF_TABLES_SET is not set # CONFIG_NF_TABLES_INET is not set # CONFIG_NF_TABLES_NETDEV is not set CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_COUNTER=m -CONFIG_NFT_CONNLIMIT=m +# CONFIG_NFT_CONNLIMIT is not set CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m -CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_OBJREF is not set CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m -CONFIG_NFT_XFRM=m -CONFIG_NFT_SOCKET=m -CONFIG_NFT_OSF=m -CONFIG_NFT_TPROXY=m -CONFIG_NFT_SYNPROXY=m +# CONFIG_NFT_XFRM is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=y @@ -1009,6 +1038,7 @@ CONFIG_NETFILTER_XT_SET=m # # Xtables targets # +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m @@ -1076,7 +1106,7 @@ CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m @@ -1095,7 +1125,7 @@ CONFIG_IP_SET_HASH_IPMARK=m CONFIG_IP_SET_HASH_IPPORT=m CONFIG_IP_SET_HASH_IPPORTIP=m CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_IPMAC=m +# CONFIG_IP_SET_HASH_IPMAC is not set CONFIG_IP_SET_HASH_MAC=m CONFIG_IP_SET_HASH_NETPORTNET=m CONFIG_IP_SET_HASH_NET=m @@ -1103,9 +1133,9 @@ CONFIG_IP_SET_HASH_NETNET=m CONFIG_IP_SET_HASH_NETPORT=m CONFIG_IP_SET_HASH_NETIFACE=m CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=y -# CONFIG_IP_VS_IPV6 is not set -# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_TAB_BITS=12 # @@ -1113,26 +1143,27 @@ CONFIG_IP_VS_TAB_BITS=12 # CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y -# CONFIG_IP_VS_PROTO_ESP is not set -# CONFIG_IP_VS_PROTO_AH is not set -# CONFIG_IP_VS_PROTO_SCTP is not set +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y # # IPVS scheduler # -CONFIG_IP_VS_RR=y -# CONFIG_IP_VS_WRR is not set -# CONFIG_IP_VS_LC is not set -# CONFIG_IP_VS_WLC is not set -# CONFIG_IP_VS_FO is not set -# CONFIG_IP_VS_OVF is not set -# CONFIG_IP_VS_LBLC is not set -# CONFIG_IP_VS_LBLCR is not set -# CONFIG_IP_VS_DH is not set -# CONFIG_IP_VS_SH is not set +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m # CONFIG_IP_VS_MH is not set -# CONFIG_IP_VS_SED is not set -# CONFIG_IP_VS_NQ is not set +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m # # IPVS SH scheduler @@ -1147,21 +1178,26 @@ CONFIG_IP_VS_MH_TAB_INDEX=12 # # IPVS application helper # +CONFIG_IP_VS_FTP=m CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m # # IP: Netfilter Configuration # -CONFIG_NF_DEFRAG_IPV4=y -CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set CONFIG_NF_TPROXY_IPV4=m # CONFIG_NF_TABLES_IPV4 is not set # CONFIG_NF_TABLES_ARP is not set CONFIG_NF_DUP_IPV4=m -# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_ARP=m CONFIG_NF_LOG_IPV4=m CONFIG_NF_REJECT_IPV4=m -CONFIG_IP_NF_IPTABLES=y +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m @@ -1186,13 +1222,13 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # -CONFIG_NF_SOCKET_IPV6=m +# CONFIG_NF_SOCKET_IPV6 is not set CONFIG_NF_TPROXY_IPV6=m # CONFIG_NF_TABLES_IPV6 is not set CONFIG_NF_DUP_IPV6=m CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m -CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m @@ -1202,7 +1238,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m +# CONFIG_IP6_NF_MATCH_SRH is not set CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m @@ -1214,9 +1250,18 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m # end of IPv6: Netfilter Configuration -CONFIG_NF_DEFRAG_IPV6=y -# CONFIG_NF_TABLES_BRIDGE is not set -CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_NF_DEFRAG_IPV6=m + +# +# DECnet: Netfilter Configuration +# +# CONFIG_DECNET_NF_GRABULATOR is not set +# end of DECnet: Netfilter Configuration + +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NF_LOG_BRIDGE=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1240,85 +1285,169 @@ CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set # CONFIG_TIPC is not set -# CONFIG_ATM is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_CLIP_NO_ICMP=y +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_ATM_BR2684_IPFILTER=y CONFIG_L2TP=m -# CONFIG_L2TP_DEBUGFS is not set -# CONFIG_L2TP_V3 is not set -CONFIG_STP=y -CONFIG_MRP=y -CONFIG_BRIDGE=y +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=y -# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_ATALK is not set +CONFIG_DECNET=m +CONFIG_DECNET_ROUTER=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=m -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_RED=m -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m # CONFIG_NET_SCH_CBS is not set # CONFIG_NET_SCH_ETF is not set # CONFIG_NET_SCH_TAPRIO is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m CONFIG_NET_SCH_MQPRIO=m # CONFIG_NET_SCH_SKBPRIO is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_CODEL is not set -# CONFIG_NET_SCH_FQ_CODEL is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m # CONFIG_NET_SCH_CAKE is not set -# CONFIG_NET_SCH_FQ is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_PIE is not set -# CONFIG_NET_SCH_PLUG is not set -# CONFIG_NET_SCH_DEFAULT is not set +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_DEFAULT_FQ=y +# CONFIG_DEFAULT_CODEL is not set +# CONFIG_DEFAULT_FQ_CODEL is not set +# CONFIG_DEFAULT_SFQ is not set +# CONFIG_DEFAULT_PFIFO_FAST is not set +CONFIG_DEFAULT_NET_SCH="fq" # # Classification # CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_FW=m -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_CLS_CGROUP is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_MATCHALL is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +# CONFIG_NET_EMATCH_CANID is not set +CONFIG_NET_EMATCH_IPSET=m +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_SAMPLE is not set +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +# CONFIG_NET_ACT_CT is not set +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +# CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -1326,16 +1455,17 @@ CONFIG_BATMAN_ADV=m CONFIG_BATMAN_ADV_BATMAN_V=y CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y -# CONFIG_BATMAN_ADV_NC is not set +CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y -# CONFIG_BATMAN_ADV_DEBUGFS is not set +CONFIG_BATMAN_ADV_DEBUGFS=y # CONFIG_BATMAN_ADV_DEBUG is not set CONFIG_BATMAN_ADV_SYSFS=y # CONFIG_BATMAN_ADV_TRACING is not set CONFIG_OPENVSWITCH=m CONFIG_OPENVSWITCH_GRE=m CONFIG_OPENVSWITCH_VXLAN=m -# CONFIG_VSOCKETS is not set +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m CONFIG_NETLINK_DIAG=m CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m @@ -1343,7 +1473,7 @@ CONFIG_NET_MPLS_GSO=m CONFIG_NET_NSH=m # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set +CONFIG_NET_L3_MASTER_DEV=y # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -1359,13 +1489,66 @@ CONFIG_NET_FLOW_LIMIT=y # # Network testing # -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=m # end of Network testing # end of Networking options -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +# CONFIG_AX25 is not set +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +# CONFIG_CAN_J1939 is not set + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +# CONFIG_CAN_VXCAN is not set +CONFIG_CAN_SLCAN=m +CONFIG_CAN_DEV=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_TI_HECC is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_SOFTING is not set + +# +# CAN SPI interfaces +# +# CONFIG_CAN_HI311X is not set +CONFIG_CAN_MCP251X=m +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +# CONFIG_CAN_MCBA_USB is not set +CONFIG_CAN_PEAK_USB=m +# CONFIG_CAN_UCAN is not set +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set +# end of CAN Device Drivers + CONFIG_BT=m CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m @@ -1376,6 +1559,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_LE=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_DEBUGFS=y @@ -1402,19 +1586,21 @@ CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m +# CONFIG_BT_MRVL_SDIO is not set CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set -CONFIG_STREAM_PARSER=y CONFIG_FIB_RULES=y CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y -CONFIG_CFG80211=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y @@ -1423,30 +1609,53 @@ CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" -# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set +CONFIG_MAC80211_DEBUGFS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 # CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_GPIO is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +# CONFIG_NFC_NCI is not set +CONFIG_NFC_HCI=m +# CONFIG_NFC_SHDLC is not set + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +# CONFIG_NFC_SIM is not set +# CONFIG_NFC_PORT100 is not set +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +# CONFIG_NFC_PN533_I2C is not set +# CONFIG_NFC_ST95HF is not set +# end of Near Field Communication (NFC) devices + # CONFIG_PSAMPLE is not set -# CONFIG_NET_IFE is not set -# CONFIG_LWTUNNEL is not set +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y -CONFIG_SOCK_VALIDATE_XMIT=y -CONFIG_NET_SOCK_MSG=y # CONFIG_FAILOVER is not set CONFIG_HAVE_EBPF_JIT=y @@ -1461,7 +1670,8 @@ CONFIG_HAVE_PCI=y # # Generic Driver Options # -# CONFIG_UEVENT_HELPER is not set +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y @@ -1520,18 +1730,25 @@ CONFIG_OF_MDIO=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_PARPORT is not set +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_1284 is not set CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_ZRAM is not set -CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -CONFIG_BLK_DEV_CRYPTOLOOP=y -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set @@ -1540,6 +1757,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 # NVME Support # # CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set # end of NVME Support # @@ -1632,104 +1850,135 @@ CONFIG_EEPROM_93CX6=m # # SCSI device support # -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y +CONFIG_SCSI_MOD=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=m CONFIG_SCSI_DMA=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_BLK_DEV_SR is not set -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # end of SCSI device support -CONFIG_ATA=y -CONFIG_ATA_VERBOSE_ERROR=y -# CONFIG_SATA_PMP is not set - -# -# Controllers with non-SFF native interface -# -CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_AHCI_CEVA is not set -# CONFIG_AHCI_QORIQ is not set -# CONFIG_ATA_SFF is not set +# CONFIG_ATA is not set CONFIG_MD=y -# CONFIG_BLK_DEV_MD is not set -# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y # CONFIG_DM_DEBUG is not set -CONFIG_DM_BUFIO=y -# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set -CONFIG_DM_BIO_PRISON=y -CONFIG_DM_PERSISTENT_DATA=y +CONFIG_DM_BUFIO=m +CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y +CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m # CONFIG_DM_UNSTRIPED is not set -CONFIG_DM_CRYPT=y -# CONFIG_DM_SNAPSHOT is not set -CONFIG_DM_THIN_PROVISIONING=y -# CONFIG_DM_CACHE is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m # CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_ERA is not set +CONFIG_DM_ERA=m # CONFIG_DM_CLONE is not set -# CONFIG_DM_MIRROR is not set -# CONFIG_DM_RAID is not set -# CONFIG_DM_ZERO is not set -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_DELAY is not set +CONFIG_DM_MIRROR=m +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_DELAY=m # CONFIG_DM_DUST is not set # CONFIG_DM_INIT is not set -# CONFIG_DM_UEVENT is not set -# CONFIG_DM_FLAKEY is not set -# CONFIG_DM_VERITY is not set -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_INTEGRITY is not set -# CONFIG_TARGET_CORE is not set +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_ISCSI_TARGET=m CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_NET_CORE=y -# CONFIG_BONDING is not set -# CONFIG_DUMMY is not set +CONFIG_BONDING=m +CONFIG_DUMMY=m # CONFIG_EQUALIZER is not set -# CONFIG_NET_TEAM is not set -# CONFIG_MACVLAN is not set -# CONFIG_IPVLAN is not set -CONFIG_VXLAN=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +# CONFIG_IPVTAP is not set +CONFIG_VXLAN=m # CONFIG_GENEVE is not set # CONFIG_GTP is not set -# CONFIG_MACSEC is not set -# CONFIG_NETCONSOLE is not set -CONFIG_TUN=y +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +CONFIG_TAP=m # CONFIG_TUN_VNET_CROSS_LE is not set -CONFIG_VETH=y +CONFIG_VETH=m # CONFIG_NLMON is not set +# CONFIG_NET_VRF is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m # # CAIF transport drivers @@ -1745,67 +1994,40 @@ CONFIG_NET_VENDOR_ALACRITECH=y # CONFIG_ALTERA_TSE is not set CONFIG_NET_VENDOR_AMAZON=y CONFIG_NET_VENDOR_AQUANTIA=y -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_AURORA=y -# CONFIG_AURORA_NB8800 is not set -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set -# CONFIG_SYSTEMPORT is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_NET_VENDOR_CADENCE=y # CONFIG_MACB is not set CONFIG_NET_VENDOR_CAVIUM=y -CONFIG_NET_VENDOR_CIRRUS=y -# CONFIG_CS89x0 is not set +# CONFIG_NET_VENDOR_CIRRUS is not set CONFIG_NET_VENDOR_CORTINA=y # CONFIG_GEMINI_ETHERNET is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set -CONFIG_NET_VENDOR_EZCHIP=y -# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_FARADAY=y -# CONFIG_FTMAC100 is not set -# CONFIG_FTGMAC100 is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set CONFIG_NET_VENDOR_GOOGLE=y -CONFIG_NET_VENDOR_HISILICON=y -# CONFIG_HIX5HD2_GMAC is not set -# CONFIG_HISI_FEMAC is not set -# CONFIG_HIP04_ETH is not set -# CONFIG_HNS is not set -# CONFIG_HNS_DSAF is not set -# CONFIG_HNS_ENET is not set +# CONFIG_NET_VENDOR_HISILICON is not set CONFIG_NET_VENDOR_HUAWEI=y -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_NATSEMI=y -CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set CONFIG_NET_VENDOR_NI=y # CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_AX88796 is not set # CONFIG_ETHOC is not set CONFIG_NET_VENDOR_PENSANDO=y -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCA7000_SPI is not set -# CONFIG_QCOM_EMAC is not set -# CONFIG_RMNET is not set -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set CONFIG_NET_VENDOR_SEEQ=y CONFIG_NET_VENDOR_SOLARFLARE=y CONFIG_NET_VENDOR_SMSC=y @@ -1879,63 +2101,140 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set -# CONFIG_PPP is not set +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m # CONFIG_SLIP is not set +CONFIG_SLHC=m CONFIG_USB_NET_DRIVERS=y -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=y CONFIG_USB_LAN78XX=m CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_CDC_NCM=y -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -CONFIG_USB_NET_SMSC75XX=y -CONFIG_USB_NET_SMSC95XX=y -# CONFIG_USB_NET_GL620A is not set -CONFIG_USB_NET_NET1080=y -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m CONFIG_USB_NET_CDC_SUBSET_ENABLE=y CONFIG_USB_NET_CDC_SUBSET=y -# CONFIG_USB_ALI_M5632 is not set -# CONFIG_USB_AN2720 is not set +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y CONFIG_USB_BELKIN=y CONFIG_USB_ARMLINUX=y -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_KC2190 is not set -CONFIG_USB_NET_ZAURUS=y -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_VL600 is not set -# CONFIG_USB_NET_CH9200 is not set +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m # CONFIG_USB_NET_AQC111 is not set CONFIG_WLAN=y -# CONFIG_WLAN_VENDOR_ADMTEK is not set -# CONFIG_WLAN_VENDOR_ATH is not set -# CONFIG_WLAN_VENDOR_ATMEL is not set -# CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set -# CONFIG_WLAN_VENDOR_INTEL is not set -# CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH9K_RFKILL=y +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +# CONFIG_ATH9K_HWRNG is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +# CONFIG_ATH6KL is not set +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_BRCMUTIL=m +# CONFIG_BRCMSMAC is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +# CONFIG_BRCMFMAC_SDIO is not set +CONFIG_BRCMFMAC_USB=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +# CONFIG_LIBERTAS_SDIO is not set +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_MESH is not set +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +# CONFIG_MWIFIEX_SDIO is not set +CONFIG_MWIFIEX_USB=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +# CONFIG_MT76x0U is not set +# CONFIG_MT76x2U is not set CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_RT2X00=y +CONFIG_RT2X00=m CONFIG_RT2500USB=m CONFIG_RT73USB=m CONFIG_RT2800USB=m @@ -1951,6 +2250,7 @@ CONFIG_RT2X00_LIB=m CONFIG_RT2X00_LIB_FIRMWARE=y CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set # CONFIG_RT2X00_DEBUG is not set CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_RTL8187=m @@ -1959,24 +2259,55 @@ CONFIG_RTL_CARDS=m CONFIG_RTL8192CU=m CONFIG_RTLWIFI=m CONFIG_RTLWIFI_USB=m -# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_DEBUG=y CONFIG_RTL8192C_COMMON=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y -CONFIG_RTW88=m -# CONFIG_WLAN_VENDOR_RSI is not set -# CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -# CONFIG_WLAN_VENDOR_ZYDAS is not set -# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_RTW88 is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_MAC80211_HWSIM is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set +CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # -# CONFIG_WAN is not set +CONFIG_WAN=y +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m + +# +# X.25/LAPB support is disabled +# +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_IEEE802154_DRIVERS=m +# CONFIG_IEEE802154_FAKELB is not set +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +# CONFIG_IEEE802154_ADF7242 is not set +# CONFIG_IEEE802154_CA8210 is not set +# CONFIG_IEEE802154_MCR20A is not set +# CONFIG_IEEE802154_HWSIM is not set # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set @@ -1986,18 +2317,21 @@ CONFIG_RTW88=m # Input device support # CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y # # Userland interfaces # -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_EVBUG is not set # @@ -2007,13 +2341,13 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADC is not set # CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_ATKBD=m # CONFIG_KEYBOARD_QT1050 is not set # CONFIG_KEYBOARD_QT1070 is not set # CONFIG_KEYBOARD_QT2160 is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set # CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO=m # CONFIG_KEYBOARD_GPIO_POLLED is not set # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set @@ -2031,24 +2365,68 @@ CONFIG_KEYBOARD_SAMSUNG=y # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CROS_EC is not set # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_BCM is not set CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set # CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -CONFIG_MOUSE_CYAPA=y -# CONFIG_MOUSE_ELAN_I2C is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +# CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_FSIA6B is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +# CONFIG_TABLET_USB_PEGASUS is not set +# CONFIG_TABLET_SERIAL_WACOM4 is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_PROPERTIES=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set +CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_ADC is not set @@ -2064,48 +2442,66 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=y # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GOODIX is not set +CONFIG_TOUCHSCREEN_GOODIX=m # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_ILI210X is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_EKTF2127 is not set -# CONFIG_TOUCHSCREEN_ELAN is not set +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +CONFIG_TOUCHSCREEN_WACOM_I2C=m # CONFIG_TOUCHSCREEN_MAX11801 is not set # CONFIG_TOUCHSCREEN_MCS5000 is not set -CONFIG_TOUCHSCREEN_MMS114=y +CONFIG_TOUCHSCREEN_MMS114=m # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +CONFIG_TOUCHSCREEN_EDT_FT5X06=m # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_PIXCIR is not set -# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC_SERIO is not set # CONFIG_TOUCHSCREEN_TSC2004 is not set # CONFIG_TOUCHSCREEN_TSC2005 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_RM_TS is not set -# CONFIG_TOUCHSCREEN_SILEAD is not set -# CONFIG_TOUCHSCREEN_SIS_I2C is not set +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m # CONFIG_TOUCHSCREEN_ST1232 is not set # CONFIG_TOUCHSCREEN_STMFTS is not set # CONFIG_TOUCHSCREEN_SUR40 is not set -# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m # CONFIG_TOUCHSCREEN_SX8654 is not set # CONFIG_TOUCHSCREEN_TPS6507X is not set # CONFIG_TOUCHSCREEN_ZET6223 is not set @@ -2113,53 +2509,72 @@ CONFIG_TOUCHSCREEN_MMS114=y # CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set # CONFIG_TOUCHSCREEN_IQS5XX is not set CONFIG_INPUT_MISC=y -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -# CONFIG_INPUT_BMA150 is not set -# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_E3X0_BUTTON=m # CONFIG_INPUT_MSM_VIBRATOR is not set -CONFIG_INPUT_MAX77693_HAPTIC=y -CONFIG_INPUT_MAX8997_HAPTIC=y -# CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_GP2A is not set -# CONFIG_INPUT_GPIO_BEEPER is not set -# CONFIG_INPUT_GPIO_DECODER is not set +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_GP2A=m +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m # CONFIG_INPUT_GPIO_VIBRA is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_KXTJ9 is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -# CONFIG_INPUT_REGULATOR_HAPTIC is not set -# CONFIG_INPUT_UINPUT is not set -# CONFIG_INPUT_PCF8574 is not set -# CONFIG_INPUT_PWM_BEEPER is not set -# CONFIG_INPUT_PWM_VIBRA is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_IMS_PCU is not set -# CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_DRV260X_HAPTICS is not set -# CONFIG_INPUT_DRV2665_HAPTICS is not set -# CONFIG_INPUT_DRV2667_HAPTICS is not set -# CONFIG_RMI4_CORE is not set +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_KXTJ9_POLLED_MODE=y +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_RMI4_CORE=m +# CONFIG_RMI4_I2C is not set +# CONFIG_RMI4_SPI is not set +# CONFIG_RMI4_SMB is not set +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +# CONFIG_RMI4_F54 is not set +# CONFIG_RMI4_F55 is not set # # Hardware I/O ports # -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y +CONFIG_SERIO=m +CONFIG_SERIO_SERPORT=m +# CONFIG_SERIO_PARKBD is not set # CONFIG_SERIO_AMBAKMI is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set +CONFIG_SERIO_LIBPS2=m +CONFIG_SERIO_RAW=m # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_SERIO_PS2MULT is not set # CONFIG_SERIO_ARC_PS2 is not set # CONFIG_SERIO_APBPS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m # end of Hardware I/O ports # end of Input device support @@ -2182,7 +2597,7 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set +CONFIG_DEVKMEM=y # # Serial drivers @@ -2234,6 +2649,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_PRINTER is not set +# CONFIG_PPDEV is not set # CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y @@ -2308,6 +2725,7 @@ CONFIG_I2C_S3C2410=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set @@ -2316,6 +2734,7 @@ CONFIG_I2C_S3C2410=y # # Other I2C/SMBus bus drivers # +CONFIG_I2C_CROS_EC_TUNNEL=y # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2336,15 +2755,17 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_ALTERA is not set # CONFIG_SPI_AXI_SPI_ENGINE is not set CONFIG_SPI_BITBANG=y +# CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=y +# CONFIG_SPI_LM70_LLP is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_ROCKCHIP is not set -CONFIG_SPI_S3C64XX=y +CONFIG_SPI_S3C64XX=m # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set @@ -2355,22 +2776,31 @@ CONFIG_SPI_S3C64XX=y # # SPI Protocol Masters # -# CONFIG_SPI_SPIDEV is not set +CONFIG_SPI_SPIDEV=m # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPMI is not set # CONFIG_HSI is not set -# CONFIG_PPS is not set +CONFIG_PPS=y +CONFIG_PPS_DEBUG=y # -# PTP clock support +# PPS clients support # -# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PPS_CLIENT_KTIMER=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m # -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# PPS generators support +# + # +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2389,7 +2819,8 @@ CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y -# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_SYSFS=y # # Memory mapped GPIO drivers @@ -2429,7 +2860,7 @@ CONFIG_OF_GPIO=y # MFD GPIO expanders # # CONFIG_HTC_EGPIO is not set -CONFIG_GPIO_WM8994=y +# CONFIG_GPIO_WM8994 is not set # end of MFD GPIO expanders # @@ -2449,13 +2880,47 @@ CONFIG_GPIO_WM8994=y # end of USB GPIO expanders # CONFIG_GPIO_MOCKUP is not set -# CONFIG_W1 is not set +CONFIG_W1=m + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +# CONFIG_W1_SLAVE_DS2405 is not set +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +# CONFIG_W1_SLAVE_DS2805 is not set +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS250X is not set +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +# CONFIG_W1_SLAVE_DS28E17 is not set +# end of 1-wire Slaves + # CONFIG_POWER_AVS is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set # CONFIG_POWER_RESET_BRCMSTB is not set -# CONFIG_POWER_RESET_GPIO is not set -# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_VERSATILE is not set @@ -2470,6 +2935,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2480,25 +2946,22 @@ CONFIG_BATTERY_SBS=y # CONFIG_BATTERY_BQ27XXX is not set CONFIG_BATTERY_MAX17040=y CONFIG_BATTERY_MAX17042=y +# CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set -CONFIG_CHARGER_MAX14577=y # CONFIG_CHARGER_DETECTOR_MAX14656 is not set -CONFIG_CHARGER_MAX77693=y -CONFIG_CHARGER_MAX8997=y -CONFIG_CHARGER_MAX8998=y # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_SMB347 is not set -CONFIG_CHARGER_TPS65090=y # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_UCS1002 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2613,7 +3076,7 @@ CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set -CONFIG_SENSORS_INA2XX=y +# CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2638,7 +3101,7 @@ CONFIG_THERMAL=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -2713,6 +3176,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set +CONFIG_MFD_CROS_EC_DEV=y # CONFIG_MFD_MADERA is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set @@ -2733,16 +3197,16 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set -CONFIG_MFD_MAX14577=y +# CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set -CONFIG_MFD_MAX77686=y -CONFIG_MFD_MAX77693=y +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set -CONFIG_MFD_MAX8997=y -CONFIG_MFD_MAX8998=y +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_EZX_PCAP is not set @@ -2772,7 +3236,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65086 is not set -CONFIG_MFD_TPS65090=y +# CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_TPS65217 is not set # CONFIG_MFD_TI_LP873X is not set # CONFIG_MFD_TI_LP87565 is not set @@ -2798,7 +3262,7 @@ CONFIG_MFD_TPS65090=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set -CONFIG_MFD_WM8994=y +CONFIG_MFD_WM8994=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_STPMIC1 is not set @@ -2826,17 +3290,11 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LP8755 is not set # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set -CONFIG_REGULATOR_MAX14577=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set -CONFIG_REGULATOR_MAX8952=y +# CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set -CONFIG_REGULATOR_MAX8997=y -CONFIG_REGULATOR_MAX8998=y -CONFIG_REGULATOR_MAX77686=y -CONFIG_REGULATOR_MAX77693=y -CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PFUZE100 is not set @@ -2854,35 +3312,78 @@ CONFIG_REGULATOR_S5M8767=y # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set -CONFIG_REGULATOR_TPS65090=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set -CONFIG_REGULATOR_WM8994=y +# CONFIG_REGULATOR_WM8994 is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y -# CONFIG_RC_CORE is not set +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +# CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IMON=m +# CONFIG_IR_IMON_RAW is not set +CONFIG_IR_MCEUSB=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +# CONFIG_RC_LOOPBACK is not set +CONFIG_IR_GPIO_CIR=y +# CONFIG_IR_SERIAL is not set +# CONFIG_IR_SIR is not set +# CONFIG_RC_XBOX_DVD is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # CONFIG_MEDIA_CAMERA_SUPPORT=y -# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set -# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set -# CONFIG_MEDIA_RADIO_SUPPORT is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_MEDIA_CEC_RC is not set CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_CONTROLLER_DVB=y +# CONFIG_MEDIA_CONTROLLER_REQUEST_API is not set CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_V4L2=y CONFIG_VIDEO_V4L2_I2C=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m CONFIG_V4L2_MEM2MEM_DEV=y # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_DVB_CORE=y +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_TTPCI_EEPROM=m +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set # # Media drivers @@ -2892,20 +3393,162 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -# CONFIG_USB_GSPCA is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -# CONFIG_VIDEO_USBTV is not set +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m + +# +# Analog TV USB devices +# +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_CXUSB_ANALOG is not set +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +# CONFIG_DVB_USB_ZD1301 is not set +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_AS102=m # # Webcam, TV (analog/digital) USB devices # -# CONFIG_VIDEO_EM28XX is not set +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m # # USB HDMI CEC adapters @@ -2920,6 +3563,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m CONFIG_VIDEO_EXYNOS4_IS_COMMON=m CONFIG_VIDEO_S5P_FIMC=m CONFIG_VIDEO_S5P_MIPI_CSIS=m +CONFIG_VIDEO_EXYNOS_FIMC_LITE=m CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y # CONFIG_VIDEO_XILINX is not set @@ -2932,27 +3576,68 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=y # CONFIG_VIDEO_SH_VEU is not set CONFIG_V4L_TEST_DRIVERS=y # CONFIG_VIDEO_VIMC is not set -# CONFIG_VIDEO_VIVID is not set +CONFIG_VIDEO_VIVID=m +# CONFIG_VIDEO_VIVID_CEC is not set +CONFIG_VIDEO_VIVID_MAX_DEVS=64 # CONFIG_VIDEO_VIM2M is not set # CONFIG_VIDEO_VICODEC is not set +CONFIG_DVB_PLATFORM_DRIVERS=y +# CONFIG_DVB_C8SECTPFE is not set CONFIG_CEC_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CROS_EC_CEC is not set +# CONFIG_CEC_GPIO is not set CONFIG_VIDEO_SAMSUNG_S5P_CEC=y +# CONFIG_SDR_PLATFORM_DRIVERS is not set # # Supported MMC/SDIO adapters # -# CONFIG_CYPRESS_FIRMWARE is not set +# CONFIG_SMS_SDIO_DRV is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set + +# +# Texas Instruments WL128x FM driver (ST based) +# +# end of Texas Instruments WL128x FM driver (ST based) + +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_DMA_CONTIG=y -CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_VIDEO_V4L2_TPG=m # # Media ancillary drivers (tuners, sensors, i2c, spi, frontends) # CONFIG_MEDIA_SUBDRV_AUTOSELECT=y CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y +CONFIG_MEDIA_ATTACH=y +CONFIG_VIDEO_IR_I2C=y # # I2C drivers hidden by 'Autoselect ancillary drivers' @@ -2961,6 +3646,11 @@ CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y # # Audio decoders, processors and mixers # +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SONY_BTF_MPX=m # # RDS decoders @@ -2969,10 +3659,16 @@ CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y # # Video decoders # +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m # # Video and audio decoders # +CONFIG_VIDEO_CX25840=m # # Video encoders @@ -2981,6 +3677,9 @@ CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y # # Camera sensor devices # +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_MT9V011=m # # Lens drivers @@ -3013,12 +3712,178 @@ CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y # # Media SPI Adapters # +# CONFIG_CXD2880_SPI_DRV is not set # end of Media SPI Adapters +CONFIG_MEDIA_TUNER=y + +# +# Tuner drivers hidden by 'Autoselect ancillary drivers' +# +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m + # # DVB Frontend drivers hidden by 'Autoselect ancillary drivers' # +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_CX22702=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_GP8PSK_FE=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_SP2=m + # # Tools to develop new frontends # @@ -3035,7 +3900,7 @@ CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set # @@ -3067,7 +3932,7 @@ CONFIG_DRM_EXYNOS=y # # CRTCs # -CONFIG_DRM_EXYNOS_FIMD=y +# CONFIG_DRM_EXYNOS_FIMD is not set # CONFIG_DRM_EXYNOS5433_DECON is not set # CONFIG_DRM_EXYNOS7_DECON is not set CONFIG_DRM_EXYNOS_MIXER=y @@ -3076,17 +3941,15 @@ CONFIG_DRM_EXYNOS_MIXER=y # # Encoders and Bridges # -CONFIG_DRM_EXYNOS_DPI=y -CONFIG_DRM_EXYNOS_DSI=y -CONFIG_DRM_EXYNOS_DP=y CONFIG_DRM_EXYNOS_HDMI=y # # Sub-drivers # -# CONFIG_DRM_EXYNOS_G2D is not set -# CONFIG_DRM_EXYNOS_FIMC is not set -# CONFIG_DRM_EXYNOS_ROTATOR is not set +CONFIG_DRM_EXYNOS_G2D=y +CONFIG_DRM_EXYNOS_IPP=y +CONFIG_DRM_EXYNOS_FIMC=y +CONFIG_DRM_EXYNOS_ROTATOR=y # CONFIG_DRM_EXYNOS_SCALER is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_ARMADA is not set @@ -3126,7 +3989,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set -CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -3157,13 +4020,12 @@ CONFIG_DRM_NXP_PTN3460=y CONFIG_DRM_PARADE_PS8622=y # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set -CONFIG_DRM_SII9234=y +# CONFIG_DRM_SII9234 is not set # CONFIG_DRM_THINE_THC63LVD1024 is not set -CONFIG_DRM_TOSHIBA_TC358764=y +# CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set -CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_I2C_ADV7511 is not set # end of Display Interface Bridges @@ -3191,7 +4053,7 @@ CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # ARM GPU Configuration # CONFIG_MALI_MIDGARD=y -# CONFIG_MALI_GATOR_SUPPORT is not set +CONFIG_MALI_GATOR_SUPPORT=y # CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set CONFIG_MALI_DEVFREQ=y CONFIG_MALI_DMA_FENCE=y @@ -3206,7 +4068,7 @@ CONFIG_MALI_EXPERT=y # CONFIG_MALI_SYSTEM_TRACE is not set # CONFIG_MALI_2MB_ALLOC is not set # CONFIG_MALI_PWRSOFT_765 is not set -# CONFIG_MALI_KUTF is not set +CONFIG_MALI_KUTF=m # end of ARM GPU Configuration # @@ -3215,7 +4077,7 @@ CONFIG_MALI_EXPERT=y CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set +CONFIG_FIRMWARE_EDID=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -3225,7 +4087,8 @@ CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set # @@ -3246,7 +4109,7 @@ CONFIG_FB_DEFERRED_IO=y # # Backlight & LCD device support # -CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_L4F00242T03 is not set # CONFIG_LCD_LMS283GF05 is not set # CONFIG_LCD_LTV350QV is not set @@ -3254,7 +4117,7 @@ CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_ILI9320 is not set # CONFIG_LCD_TDO24M is not set # CONFIG_LCD_VGG2432A4 is not set -CONFIG_LCD_PLATFORM=y +CONFIG_LCD_PLATFORM=m # CONFIG_LCD_AMS369FG06 is not set # CONFIG_LCD_LMS501KF03 is not set # CONFIG_LCD_HX8357 is not set @@ -3283,38 +4146,60 @@ CONFIG_HDMI=y CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set # end of Console display driver support -# CONFIG_LOGO is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y CONFIG_SND_PCM_ELD=y CONFIG_SND_PCM_IEC958=y CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_PCM_TIMER=y -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set -# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_VIRMIDI=m CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set -# CONFIG_SND_ALOOP is not set +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m # CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set +# CONFIG_SND_PORTMAN2X4 is not set # # HD-Audio @@ -3326,16 +4211,19 @@ CONFIG_SND_ARM=y # CONFIG_SND_ARMAACI is not set CONFIG_SND_SPI=y CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_UA101 is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_USB_6FIRE is not set -# CONFIG_SND_USB_HIFACE is not set -# CONFIG_SND_BCD2000 is not set -# CONFIG_SND_USB_POD is not set -# CONFIG_SND_USB_PODHD is not set -# CONFIG_SND_USB_TONEPORT is not set -# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_AMD_ACP is not set @@ -3364,14 +4252,14 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_MTK_BTCVSD is not set CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SAMSUNG_PCM=y -# CONFIG_SND_SAMSUNG_SPDIF is not set +CONFIG_SND_SAMSUNG_SPDIF=m CONFIG_SND_SAMSUNG_I2S=y -CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=y -# CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF is not set -CONFIG_SND_SOC_SMDK_WM8994_PCM=y -CONFIG_SND_SOC_SNOW=y +CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=m +CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF=m +CONFIG_SND_SOC_SMDK_WM8994_PCM=m +CONFIG_SND_SOC_SNOW=m CONFIG_SND_SOC_ODROID=y -# CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631 is not set +CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631=m # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -3389,7 +4277,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # -CONFIG_SND_SOC_WM_HUBS=y +CONFIG_SND_SOC_WM_HUBS=m # CONFIG_SND_SOC_AC97_CODEC is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set @@ -3406,6 +4294,7 @@ CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CROS_EC_CODEC is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set @@ -3437,7 +4326,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=y -CONFIG_SND_SOC_MAX98095=y +CONFIG_SND_SOC_MAX98095=m # CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set @@ -3459,11 +4348,11 @@ CONFIG_SND_SOC_MAX98095=y # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set -# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5631=m # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -# CONFIG_SND_SOC_SPDIF is not set +CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set @@ -3511,7 +4400,7 @@ CONFIG_SND_SOC_MAX98095=y # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set -CONFIG_SND_SOC_WM8994=y +CONFIG_SND_SOC_WM8994=m # CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set @@ -3531,118 +4420,136 @@ CONFIG_SND_SIMPLE_CARD=y # HID support # CONFIG_HID=y -# CONFIG_HID_BATTERY_STRENGTH is not set -# CONFIG_HIDRAW is not set -# CONFIG_UHID is not set +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=y CONFIG_HID_GENERIC=y # # Special HID drivers # -CONFIG_HID_A4TECH=y -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set -CONFIG_HID_APPLE=y -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set -CONFIG_HID_BELKIN=y -# CONFIG_HID_BETOP_FF is not set +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m # CONFIG_HID_BIGBEN_FF is not set -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -# CONFIG_HID_CORSAIR is not set +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m # CONFIG_HID_COUGAR is not set # CONFIG_HID_MACALLY is not set -# CONFIG_HID_PRODIKEYS is not set -# CONFIG_HID_CMEDIA is not set +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CP2112=m # CONFIG_HID_CREATIVE_SB0540 is not set -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m # CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +# CONFIG_HID_GOOGLE_HAMMER is not set +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m # CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -CONFIG_HID_ITE=y +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m # CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set -CONFIG_HID_KENSINGTON=y -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set -CONFIG_HID_LOGITECH=y -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGIG940_FF is not set -# CONFIG_LOGIWHEELS_FF is not set -# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m # CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set +CONFIG_HID_MAYFLASH=m CONFIG_HID_REDRAGON=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set -# CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m # CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m # CONFIG_HID_U2FZERO is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m # end of Special HID drivers # # USB HID support # -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y # end of USB HID support # # I2C HID support # -# CONFIG_I2C_HID is not set +CONFIG_I2C_HID=m # end of I2C HID support # end of HID support @@ -3661,8 +4568,10 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set +CONFIG_USB_OTG=y # CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set @@ -3706,7 +4615,7 @@ CONFIG_USB_TMC=m # # also be needed; see USB_STORAGE Help for more info # -CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set CONFIG_USB_STORAGE_REALTEK=m CONFIG_REALTEK_AUTOPM=y @@ -3722,14 +4631,20 @@ CONFIG_USB_STORAGE_ONETOUCH=m CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_CYPRESS_ATACB=m CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=y +CONFIG_USB_UAS=m # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USBIP_CORE is not set +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y @@ -3758,7 +4673,63 @@ CONFIG_USB_DWC2_DUAL_ROLE=y # # USB port drivers # -# CONFIG_USB_SERIAL is not set +# CONFIG_USB_USS720 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers @@ -3782,12 +4753,13 @@ CONFIG_USB_DWC2_DUAL_ROLE=y # CONFIG_USB_EHSET_TEST_FIXTURE is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set +CONFIG_USB_EZUSB_FX2=m # CONFIG_USB_HUB_USB251XB is not set CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ATM is not set # # USB Physical Layer drivers @@ -3803,6 +4775,7 @@ CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_U_SERIAL_CONSOLE is not set # # USB Peripheral Controller @@ -3822,7 +4795,36 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_DUMMY_HCD is not set # end of USB Peripheral Controller +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m # CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_MASS_STORAGE=m +# CONFIG_USB_GADGET_TARGET is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set CONFIG_MMC=y @@ -3893,8 +4895,6 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set -CONFIG_LEDS_MAX77693=y -CONFIG_LEDS_MAX8997=y # CONFIG_LEDS_LM355x is not set # CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set @@ -3914,20 +4914,19 @@ CONFIG_LEDS_MAX8997=y # LED Triggers # CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_DISK is not set +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set -# CONFIG_LEDS_TRIGGER_GPIO is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # # iptables trigger is under Netfilter config (LED target) # -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +CONFIG_LEDS_TRIGGER_TRANSIENT=y # CONFIG_LEDS_TRIGGER_CAMERA is not set # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set @@ -3966,9 +4965,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set -CONFIG_RTC_DRV_MAX8998=y -CONFIG_RTC_DRV_MAX8997=y -CONFIG_RTC_DRV_MAX77686=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -4038,6 +5034,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_ZYNQMP is not set +# CONFIG_RTC_DRV_CROS_EC is not set # # on-CPU RTC drivers @@ -4054,6 +5051,7 @@ CONFIG_RTC_DRV_S3C=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4090,7 +5088,11 @@ CONFIG_SYNC_FILE=y # end of DMABUF options # CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set +# CONFIG_PANEL is not set +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +# CONFIG_UIO_PRUSS is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_MENU=y @@ -4102,10 +5104,156 @@ CONFIG_VIRTIO_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set -# CONFIG_STAGING is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +# CONFIG_COMEDI is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL8723BS is not set +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_88EU_AP_MODE=y +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# end of Speakup console speech + +CONFIG_STAGING_MEDIA=y + +# +# soc_camera sensor drivers +# + +# +# Android +# +# end of Android + +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +# CONFIG_FB_TFT_SH1106 is not set +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_FB_TFT_WATTEROTT=m +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +# CONFIG_MOST is not set +# CONFIG_KS7010 is not set +# CONFIG_PI433 is not set + +# +# Gasket devices +# +# end of Gasket devices + +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_UWB is not set +# CONFIG_EXFAT_FS is not set # CONFIG_GOLDFISH is not set -# CONFIG_MFD_CROS_EC is not set -# CONFIG_CHROME_PLATFORMS is not set +CONFIG_MFD_CROS_EC=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y +# CONFIG_CROS_EC_I2C is not set +# CONFIG_CROS_EC_SPI is not set +CONFIG_CROS_EC_PROTO=y +# CONFIG_CROS_EC_CHARDEV is not set +CONFIG_CROS_EC_LIGHTBAR=y +CONFIG_CROS_EC_VBC=y +CONFIG_CROS_EC_DEBUGFS=y +CONFIG_CROS_EC_SYSFS=y # CONFIG_MELLANOX_PLATFORM is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y @@ -4115,7 +5263,6 @@ CONFIG_COMMON_CLK=y # Common Clock Framework # # CONFIG_CLK_HSDK is not set -CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set @@ -4144,6 +5291,7 @@ CONFIG_TIMER_PROBE=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_CLKSRC_EXYNOS_MCT=y +CONFIG_CLKSRC_SAMSUNG_PWM=y # end of Clock Source drivers # CONFIG_MAILBOX is not set @@ -4153,9 +5301,7 @@ CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # end of Generic IOMMU Pagetable Support @@ -4238,8 +5384,8 @@ CONFIG_PM_DEVFREQ=y # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # @@ -4257,26 +5403,24 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_ADC_JACK is not set # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set -CONFIG_EXTCON_MAX14577=y # CONFIG_EXTCON_MAX3355 is not set -CONFIG_EXTCON_MAX77693=y -CONFIG_EXTCON_MAX8997=y # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set -# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USB_GPIO=m +# CONFIG_EXTCON_USBC_CROS_EC is not set CONFIG_MEMORY=y -CONFIG_DDR=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_PL353_SMC=y CONFIG_SAMSUNG_MC=y -CONFIG_EXYNOS5422_DMC=y +# CONFIG_EXYNOS5422_DMC is not set CONFIG_EXYNOS_SROM=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y # CONFIG_IIO_BUFFER_CB is not set # CONFIG_IIO_BUFFER_HW_CONSUMER is not set CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGERED_BUFFER=y # CONFIG_IIO_CONFIGFS is not set CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 @@ -4288,8 +5432,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_ADIS16201 is not set # CONFIG_ADIS16209 is not set -# CONFIG_ADXL345_I2C is not set -# CONFIG_ADXL345_SPI is not set # CONFIG_ADXL372_SPI is not set # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set @@ -4300,6 +5442,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_HID_SENSOR_ACCEL_3D is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4341,6 +5484,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_EXYNOS_ADC=y # CONFIG_HI8435 is not set # CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set # CONFIG_LTC2497 is not set @@ -4395,9 +5539,12 @@ CONFIG_EXYNOS_ADC=y # CONFIG_VZ89X is not set # end of Chemical Sensors +# CONFIG_IIO_CROS_EC_SENSORS_CORE is not set + # # Hid Sensor IIO Common # +# CONFIG_HID_SENSOR_IIO_COMMON is not set # end of Hid Sensor IIO Common # @@ -4477,6 +5624,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set # CONFIG_FXAS21002C is not set +# CONFIG_HID_SENSOR_GYRO_3D is not set # CONFIG_MPU3050_I2C is not set # CONFIG_IIO_ST_GYRO_3AXIS is not set # CONFIG_ITG3200 is not set @@ -4502,6 +5650,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set +# CONFIG_HID_SENSOR_HUMIDITY is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set @@ -4535,11 +5684,13 @@ CONFIG_EXYNOS_ADC=y # CONFIG_CM3232 is not set # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set -# CONFIG_CM36651 is not set +CONFIG_CM36651=y # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set +# CONFIG_HID_SENSOR_ALS is not set +# CONFIG_HID_SENSOR_PROX is not set # CONFIG_JSA1212 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set @@ -4571,11 +5722,12 @@ CONFIG_EXYNOS_ADC=y # Magnetometer sensors # # CONFIG_AK8974 is not set -# CONFIG_AK8975 is not set +CONFIG_AK8975=y # CONFIG_AK09911 is not set # CONFIG_BMC150_MAGN_I2C is not set # CONFIG_BMC150_MAGN_SPI is not set # CONFIG_MAG3110 is not set +# CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set # CONFIG_MMC35240 is not set # CONFIG_IIO_ST_MAGN_3AXIS is not set # CONFIG_SENSORS_HMC5843_I2C is not set @@ -4593,6 +5745,8 @@ CONFIG_EXYNOS_ADC=y # # Inclinometer sensors # +# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set +# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set # end of Inclinometer sensors # @@ -4629,6 +5783,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set # CONFIG_DPS310 is not set +# CONFIG_HID_SENSOR_PRESS is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set @@ -4671,6 +5826,7 @@ CONFIG_EXYNOS_ADC=y # Temperature sensors # # CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_HID_SENSOR_TEMP is not set # CONFIG_MLX90614 is not set # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set @@ -4682,6 +5838,7 @@ CONFIG_EXYNOS_ADC=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_CROS_EC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SAMSUNG=y @@ -4692,6 +5849,7 @@ CONFIG_PWM_SAMSUNG=y CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_GIC_NON_BANKED=y # CONFIG_AL_FIC is not set # end of IRQ chip support @@ -4716,8 +5874,11 @@ CONFIG_PHY_EXYNOS_DP_VIDEO=y CONFIG_PHY_EXYNOS_MIPI_VIDEO=y # CONFIG_PHY_EXYNOS_PCIE is not set CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_PHY_EXYNOS4210_USB2=y +CONFIG_PHY_EXYNOS4X12_USB2=y CONFIG_PHY_EXYNOS5250_USB2=y CONFIG_PHY_EXYNOS5_USBDRD=y +CONFIG_PHY_EXYNOS5250_SATA=y # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -4739,7 +5900,7 @@ CONFIG_ARM_PMU=y # CONFIG_ANDROID is not set # end of Android -# CONFIG_DAX is not set +CONFIG_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y @@ -4778,29 +5939,66 @@ CONFIG_EXT4_FS_SECURITY=y CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set -# CONFIG_BTRFS_FS is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set # CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_CHECK_FS=y +# CONFIG_F2FS_FAULT_INJECTION is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_EXPORTFS_BLOCK_OPS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set -# CONFIG_QUOTA is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y -# CONFIG_FUSE_FS is not set -CONFIG_OVERLAY_FS=y +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set +CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set @@ -4810,14 +6008,21 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # -# CONFIG_FSCACHE is not set +CONFIG_FSCACHE=m +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +# CONFIG_CACHEFILES is not set # end of Caches # # CD-ROM/DVD Filesystems # -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m # end of CD-ROM/DVD Filesystems # @@ -4828,8 +6033,8 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -CONFIG_NTFS_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=m # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y # end of DOS/FAT/NT Filesystems @@ -4847,7 +6052,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_MEMFD_CREATE=y -# CONFIG_CONFIGFS_FS is not set +CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y @@ -4855,18 +6060,32 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -CONFIG_HFSPLUS_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_CRAMFS=y CONFIG_CRAMFS_BLOCKDEV=y -# CONFIG_SQUASHFS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set +CONFIG_MINIX_FS=m # CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set +CONFIG_HPFS_FS=m # CONFIG_QNX4FS_FS is not set # CONFIG_QNX6FS_FS is not set CONFIG_ROMFS_FS=y @@ -4874,93 +6093,113 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y CONFIG_ROMFS_ON_BLOCK=y # CONFIG_PSTORE is not set # CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +CONFIG_UFS_FS=m +CONFIG_UFS_FS_WRITE=y +# CONFIG_UFS_DEBUG is not set # CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set -# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y -# CONFIG_NFSD is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set -CONFIG_CIFS=y +CONFIG_CIFS=m # CONFIG_CIFS_STATS2 is not set CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y -# CONFIG_CIFS_POSIX is not set -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -# CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_ROOT is not set +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set -CONFIG_NLS_UTF8=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set # CONFIG_UNICODE is not set # end of File systems @@ -4972,7 +6211,7 @@ CONFIG_KEYS=y # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set # CONFIG_TRUSTED_KEYS is not set -# CONFIG_ENCRYPTED_KEYS is not set +CONFIG_ENCRYPTED_KEYS=y # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set @@ -4998,6 +6237,12 @@ CONFIG_INIT_STACK_NONE=y # end of Kernel hardening options # end of Security options +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m CONFIG_CRYPTO=y # @@ -5023,12 +6268,12 @@ CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_PCRYPT=m CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_SIMD=m @@ -5044,9 +6289,9 @@ CONFIG_CRYPTO_ECDH=m # # Authenticated Encryption with Associated Data # -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_GCM=y -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m # CONFIG_CRYPTO_AEGIS128 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=m @@ -5057,89 +6302,92 @@ CONFIG_CRYPTO_ECHAINIV=m CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y -# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LRW=m # CONFIG_CRYPTO_OFB is not set -# CONFIG_CRYPTO_PCBC is not set -CONFIG_CRYPTO_XTS=m -# CONFIG_CRYPTO_KEYWRAP is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_KEYWRAP=m # CONFIG_CRYPTO_ADIANTUM is not set -CONFIG_CRYPTO_ESSIV=y +CONFIG_CRYPTO_ESSIV=m # # Hash modes # -CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m # # Digest # CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_CRC32=m # CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_CRCT10DIF is not set -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_POLY1305 is not set -CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m # # Ciphers # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_LIB_DES=m CONFIG_CRYPTO_DES=m -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_CHACHA20=m -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m # CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m # # Compression # -# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m -# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m -# CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_ZSTD is not set +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m # # Random Number Generation # -# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_HASH is not set @@ -5154,8 +6402,9 @@ CONFIG_CRYPTO_USER_API_AEAD=m # CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_DEV_EXYNOS_RNG=y +# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set CONFIG_CRYPTO_DEV_S5P=y +CONFIG_CRYPTO_DEV_EXYNOS_HASH=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_SAFEXCEL is not set @@ -5183,6 +6432,8 @@ CONFIG_BINARY_PRINTF=y # # Library routines # +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y @@ -5195,7 +6446,7 @@ CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set @@ -5203,17 +6454,25 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set -# CONFIG_CRC64 is not set +CONFIG_CRC64=m # CONFIG_CRC4 is not set # CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y +CONFIG_LIBCRC32C=m # CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y # CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=m +CONFIG_842_DECOMPRESS=m CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_COMPRESS=m CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=m +CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y @@ -5230,6 +6489,8 @@ CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC8=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m @@ -5261,6 +6522,7 @@ CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y @@ -5269,7 +6531,7 @@ CONFIG_OID_REGISTRY=y CONFIG_FONT_SUPPORT=y CONFIG_FONTS=y # CONFIG_FONT_8x8 is not set -# CONFIG_FONT_8x16 is not set +CONFIG_FONT_8x16=y # CONFIG_FONT_6x11 is not set CONFIG_FONT_7x14=y # CONFIG_FONT_PEARL_8x8 is not set @@ -5345,6 +6607,7 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_INFO=y # CONFIG_DEBUG_TIMEKEEPING is not set # @@ -5382,9 +6645,10 @@ CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_PREEMPTIRQ_EVENTS is not set # CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_HWLAT_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_ENABLE_DEFAULT_TRACERS=y # CONFIG_FTRACE_SYSCALLS is not set # CONFIG_TRACER_SNAPSHOT is not set CONFIG_BRANCH_PROFILE_NONE=y @@ -5407,6 +6671,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_SORT is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ASYNC_RAID6_TEST is not set # CONFIG_TEST_HEXDUMP is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set @@ -5446,7 +6711,7 @@ CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y -CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_USER is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # CONFIG_PID_IN_CONTEXTIDR is not set From 0fd8b85020fb87b87a645cdc9f330ffc258e993b Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Thu, 7 Nov 2019 10:58:33 +0900 Subject: [PATCH 055/133] ODROID-XU4: dts: Add i2c-1, i2c-5 nodes Signed-off-by: Yang Deokgyu Change-Id: Ibd89677ca9dcc165b305488b9c1e106f4e53eba6 --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 892d389d6d0918..220a84465ecadd 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -96,3 +96,16 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; + +/* i2c@12C70000 */ +&i2c_1 { + status = "okay"; + samsung,i2c-max-bus-freq = <400000>; +}; + +/* i2c@12cb0000 */ +&hsi2c_5 { + status = "okay"; + samsung,hs-mode; + clock-frequency = <400000>; +}; From 0c4fc21bc64bee1c8128d17c173ac130607bf632 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Thu, 14 Nov 2019 13:45:22 +0900 Subject: [PATCH 056/133] ODROID-XU4: Add support for SPI1 on the 40 pin header Signed-off-by: Yang Deokgyu Change-Id: I0b1d16b0f445838509eeb0cc8093239fa1805605 --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 20 ++++++++++++++++++++ drivers/spi/spidev.c | 2 ++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 220a84465ecadd..a2b9a892c7df97 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -11,6 +11,7 @@ /dts-v1/; #include #include "exynos5422-odroidxu3-common.dtsi" +#include / { model = "Hardkernel Odroid XU4"; @@ -109,3 +110,22 @@ samsung,hs-mode; clock-frequency = <400000>; }; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <2>; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>; + + spidev: spidev@0 { + status = "okay"; + reg = <0>; + compatible = "odroid,spidev"; + spi-max-frequency = <1000000>; + + controller-data { + cs-gpio = <&gpa2 5 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <0>; + }; + }; +}; diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 3ea9d8a3e6e896..22ce9f8c694697 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -668,6 +668,8 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "lwn,bk4" }, { .compatible = "dh,dhcom-board" }, { .compatible = "menlo,m53cpld" }, + /* ODROID Modification */ + { .compatible = "odroid,spidev" }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); From be24829a9d03e1bcb63af6ae760ce05895cc88a1 Mon Sep 17 00:00:00 2001 From: Brian Kim Date: Tue, 10 Jan 2017 11:31:52 +0900 Subject: [PATCH 057/133] ODROID-XU4: char: exynos: add /dev/gpiomem device for rootless user GPIO access Signed-off-by: memeka Signed-off-by: Yang Deokgyu Change-Id: Ia6b9596501223037ee3be3587d720f74a2494380 --- .../boot/dts/exynos5422-odroidxu3-common.dtsi | 7 + drivers/char/Kconfig | 9 + drivers/char/Makefile | 1 + drivers/char/exynos-gpiomem.c | 270 ++++++++++++++++++ 4 files changed, 287 insertions(+) create mode 100644 drivers/char/exynos-gpiomem.c diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 10129b44f88778..37c609c66c5450 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -34,6 +34,13 @@ }; }; + gpiomem { + compatible = "samsung,exynos-gpiomem"; + reg = <0x13400000 0x1000>, + <0x14010000 0x1000>; + status = "okay"; + }; + emmc_pwrseq: pwrseq { pinctrl-0 = <&emmc_nrst_pin>; pinctrl-names = "default"; diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index df0fc997dc3e30..6fbe5ce36a9c86 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -535,6 +535,15 @@ config ADI and SSM (Silicon Secured Memory). Intended consumers of this driver include crash and makedumpfile. +config EXYNOS_GPIOMEM + tristate "/dev/gpiomem rootless GPIO access via mmap() on the EXYNOS" + default m + help + Provides users with root-free access to the GPIO registers + on EXYNOS. Calling mmap(/dev/gpiomem) will map the GPIO register + page to the user's pointer. This drvier can allow to access gpio + memory area in user account. + endmenu config RANDOM_TRUST_CPU diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 7c5ea6f9df1455..6e3a5e4b6163ea 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -52,3 +52,4 @@ js-rtc-y = rtc.o obj-$(CONFIG_XILLYBUS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +obj-$(CONFIG_EXYNOS_GPIOMEM) += exynos-gpiomem.o diff --git a/drivers/char/exynos-gpiomem.c b/drivers/char/exynos-gpiomem.c new file mode 100644 index 00000000000000..5dd684d48ffcf8 --- /dev/null +++ b/drivers/char/exynos-gpiomem.c @@ -0,0 +1,270 @@ +/* + * linux/drivers/char/exynos-gpiomem.c + * + * GPIO memory device driver + * + * Creates a chardev /dev/gpiomem which will provide user access to + * the EXYNOS's GPIO registers when it is mmap()'d. + * No longer need root for user GPIO access, but without relaxing permissions + * on /dev/mem. + * + * Copyright (c) 2017 Hardkernel Co., Ltd. + * + * This driver is based on bcm2835-gpiomem.c in Raspberrypi's linux kernel 4.4: + * Written by Luke Wren + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2, as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_NAME "exynos-gpiomem" +#define DRIVER_NAME "gpiomem-exynos" +#define DEVICE_MINOR 0 + +struct exynos_gpiomem_instance { + unsigned long gpio_regs_phys[32]; + int gpio_area_count; + struct device *dev; +}; + +static struct cdev exynos_gpiomem_cdev; +static dev_t exynos_gpiomem_devid; +static struct class *exynos_gpiomem_class; +static struct device *exynos_gpiomem_dev; +static struct exynos_gpiomem_instance *inst; + +static int exynos_gpiomem_open(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + + dev_info(inst->dev, "gpiomem device opened."); + + if (dev != DEVICE_MINOR) { + dev_err(inst->dev, "Unknown minor device: %d", dev); + ret = -ENXIO; + } + return ret; +} + +static int exynos_gpiomem_release(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + int ret = 0; + + if (dev != DEVICE_MINOR) { + dev_err(inst->dev, "Unknown minor device %d", dev); + ret = -ENXIO; + } + return ret; +} + +static const struct vm_operations_struct exynos_gpiomem_vm_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys +#endif +}; + +static int exynos_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) +{ + int gpio_area = 0; + + while (gpio_area < inst->gpio_area_count) { + if ((inst->gpio_regs_phys[gpio_area] >> PAGE_SHIFT) == vma->vm_pgoff) + goto found; + + gpio_area++; + } + + return -EACCES; + +found: + vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff, + PAGE_SIZE, + vma->vm_page_prot); + + vma->vm_ops = &exynos_gpiomem_vm_ops; + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, + PAGE_SIZE, + vma->vm_page_prot)) { + return -EAGAIN; + } + + return 0; +} + +static const struct file_operations +exynos_gpiomem_fops = { + .owner = THIS_MODULE, + .open = exynos_gpiomem_open, + .release = exynos_gpiomem_release, + .mmap = exynos_gpiomem_mmap, +}; + +static int exynos_gpiomem_probe(struct platform_device *pdev) +{ + int err = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res = NULL; + int i = 0; + + /* Allocate buffers and instance data */ + inst = kzalloc(sizeof(struct exynos_gpiomem_instance), GFP_KERNEL); + + if (!inst) { + err = -ENOMEM; + goto failed_inst_alloc; + } + + inst->dev = dev; + + inst->gpio_area_count = of_property_count_elems_of_size(np, "reg", + sizeof(u32)) / 2; + + if (inst->gpio_area_count > 32 || inst->gpio_area_count <= 0) { + dev_err(inst->dev, "failed to get gpio register area."); + err = -EINVAL; + goto failed_inst_alloc; + } + + dev_info(inst->dev, "Initialised: GPIO register area is %d", + inst->gpio_area_count); + + for (i = 0; i < inst->gpio_area_count; ++i) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (res) { + inst->gpio_regs_phys[i] = res->start; + } else { + dev_err(inst->dev, "failed to get IO resource"); + err = -ENOENT; + goto failed_get_resource; + } + } + + /* Create character device entries */ + err = alloc_chrdev_region(&exynos_gpiomem_devid, + DEVICE_MINOR, 1, DEVICE_NAME); + if (err != 0) { + dev_err(inst->dev, "unable to allocate device number"); + goto failed_alloc_chrdev; + } + cdev_init(&exynos_gpiomem_cdev, &exynos_gpiomem_fops); + exynos_gpiomem_cdev.owner = THIS_MODULE; + err = cdev_add(&exynos_gpiomem_cdev, exynos_gpiomem_devid, 1); + if (err != 0) { + dev_err(inst->dev, "unable to register device"); + goto failed_cdev_add; + } + + /* Create sysfs entries */ + exynos_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME); + err = IS_ERR(exynos_gpiomem_class); + if (err) + goto failed_class_create; + + exynos_gpiomem_dev = device_create(exynos_gpiomem_class, NULL, + exynos_gpiomem_devid, NULL, + "gpiomem"); + err = IS_ERR(exynos_gpiomem_dev); + if (err) + goto failed_device_create; + + for (i = 0; i < inst->gpio_area_count; ++i) { + dev_info(inst->dev, "Initialised: Registers at 0x%08lx", + inst->gpio_regs_phys[i]); + } + + return 0; + +failed_device_create: + class_destroy(exynos_gpiomem_class); +failed_class_create: + cdev_del(&exynos_gpiomem_cdev); +failed_cdev_add: + unregister_chrdev_region(exynos_gpiomem_devid, 1); +failed_alloc_chrdev: +failed_get_resource: + kfree(inst); +failed_inst_alloc: + dev_err(inst->dev, "could not load exynos_gpiomem"); + return err; +} + +static int exynos_gpiomem_remove(struct platform_device *pdev) +{ + struct device *dev = inst->dev; + + kfree(inst); + device_destroy(exynos_gpiomem_class, exynos_gpiomem_devid); + class_destroy(exynos_gpiomem_class); + cdev_del(&exynos_gpiomem_cdev); + unregister_chrdev_region(exynos_gpiomem_devid, 1); + + dev_info(dev, "GPIO mem driver removed - OK"); + return 0; +} + +static const struct of_device_id exynos_gpiomem_of_match[] = { + {.compatible = "samsung,exynos-gpiomem",}, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_gpiomem_of_match); + +static struct platform_driver exynos_gpiomem_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = exynos_gpiomem_of_match, + }, + .probe = exynos_gpiomem_probe, + .remove = exynos_gpiomem_remove, +}; + +module_platform_driver(exynos_gpiomem_driver); + +MODULE_ALIAS("platform:gpiomem-exynos"); +MODULE_DESCRIPTION("EXYNOS gpiomem driver for accessing GPIO from userspace"); +MODULE_AUTHOR("Brian Kim "); +MODULE_LICENSE("GPL"); From 98c400019216d69cf7c056691f3a70a30f6c7c7b Mon Sep 17 00:00:00 2001 From: Brian Kim Date: Tue, 21 Nov 2017 18:44:03 +0900 Subject: [PATCH 058/133] ODROID-XU4: arm: Set the system revision information wiringPi library refers to this information in '/proc/cpuinfo' file. Signed-off-by: Yang Deokgyu Change-Id: I4a3368499cecf862eddb1430c6b436283f62d2c7 --- arch/arm/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d0a464e317eacf..7e66d1735a3c05 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -90,7 +90,7 @@ EXPORT_SYMBOL(cacheid); unsigned int __atags_pointer __initdata; -unsigned int system_rev; +unsigned int system_rev = 0x0100; EXPORT_SYMBOL(system_rev); const char *system_serial; From 03f95577a5d2b127471fa58f472f399f7709e5bc Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Wed, 4 Dec 2019 18:35:40 +0900 Subject: [PATCH 059/133] ODROID-XU4: defconfig: Enable CONFIG_EXYNOS_GPIOMEM Signed-off-by: Yang Deokgyu Change-Id: I506c7e34ba3be12b2934340667a7c6c42744c56c --- arch/arm/configs/odroidxu4_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/odroidxu4_defconfig b/arch/arm/configs/odroidxu4_defconfig index 59f40acfc2287d..66474ab9464031 100644 --- a/arch/arm/configs/odroidxu4_defconfig +++ b/arch/arm/configs/odroidxu4_defconfig @@ -2668,6 +2668,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_I2C is not set # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set +CONFIG_EXYNOS_GPIOMEM=m # end of Character devices # CONFIG_RANDOM_TRUST_BOOTLOADER is not set From c4c140584d9b32e3853d34f4842cf926b4dfc28d Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Thu, 9 Nov 2017 22:09:37 -0500 Subject: [PATCH 060/133] ODROID-XU4: ARM: exynos: add machine description for ODROID-XU3/4 Change-Id: Ice75e06366f107f761504512a84fb92affffb124 Signed-off-by: Dongjin Kim --- arch/arm/mach-exynos/exynos.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 9aa483366ebcbc..ab58f368b2d3c6 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -204,3 +204,31 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") .dt_compat = exynos_dt_compat, .dt_fixup = exynos_dt_fixup, MACHINE_END + +#define ODROID_MACHINE_START(name, compat) \ + DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name) \ + .l2c_aux_val = 0x3c400001, \ + .l2c_aux_mask = 0xc20fffff, \ + .smp = smp_ops(exynos_smp_ops), \ + .map_io = exynos_init_io, \ + .init_early = exynos_firmware_init, \ + .init_irq = exynos_init_irq, \ + .init_machine = exynos_dt_machine_init, \ + .init_late = exynos_init_late, \ + .dt_compat = compat, \ + .dt_fixup = exynos_dt_fixup, \ + MACHINE_END + +static char const *const exynos5422_odroidxu3_dt_compat[] __initconst = { + "hardkernel,odroid-xu3", + "hardkernel,odroid-xu3-lite", + NULL, +}; + +static char const *const exynos5422_odroidxu4_dt_compat[] __initconst = { + "hardkernel,odroid-xu4", + NULL, +}; + +ODROID_MACHINE_START(XU3, exynos5422_odroidxu3_dt_compat) +ODROID_MACHINE_START(XU4, exynos5422_odroidxu4_dt_compat) From 64e47077be4fb027a73ac6fd1d16126ffdf65ae0 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Thu, 5 Dec 2019 10:09:00 +0900 Subject: [PATCH 061/133] ODROID-XU4: arm/exynos: No need to use enynos_init_late Signed-off-by: Yang Deokgyu Change-Id: I7d141a655c23bf364753be9831b4428ee3aa6711 --- arch/arm/mach-exynos/exynos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index ab58f368b2d3c6..e65ef3ecddc7cd 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -214,7 +214,7 @@ MACHINE_END .init_early = exynos_firmware_init, \ .init_irq = exynos_init_irq, \ .init_machine = exynos_dt_machine_init, \ - .init_late = exynos_init_late, \ + .init_late = exynos_pm_init, \ .dt_compat = compat, \ .dt_fixup = exynos_dt_fixup, \ MACHINE_END From ea4fba70251d1c5bdf620ce39da1025711d34985 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Thu, 5 Dec 2019 10:13:54 +0900 Subject: [PATCH 062/133] ODROID-XU4: arm/exynos: Add vendor name Hardkernel to its H/W information Because the other devices we provided have vendor name in /proc/cpuinfo. Signed-off-by: Yang Deokgyu Change-Id: I81a553ea8f662016b702cbb5e543ba7a769e8d0f --- arch/arm/mach-exynos/exynos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index e65ef3ecddc7cd..87f452b38d5446 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -206,7 +206,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") MACHINE_END #define ODROID_MACHINE_START(name, compat) \ - DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name) \ + DT_MACHINE_START(EXYNOS5422_ODROID_##name, "Hardkernel ODROID-"#name) \ .l2c_aux_val = 0x3c400001, \ .l2c_aux_mask = 0xc20fffff, \ .smp = smp_ops(exynos_smp_ops), \ From 51c6103441a8422a706f8b7267dd5add3ef5e9a0 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Tue, 22 Oct 2019 15:17:19 +0900 Subject: [PATCH 063/133] ODROID-XU4: char/exynos-gpiomem: Remove unnecessary kernel logs noticed when every time it opens Change-Id: If35e49c6d96b960f0ff1a997b2126c2c6378fdad Signed-off-by: Yang Deokgyu --- drivers/char/exynos-gpiomem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/char/exynos-gpiomem.c b/drivers/char/exynos-gpiomem.c index 5dd684d48ffcf8..03ea4344346a4b 100644 --- a/drivers/char/exynos-gpiomem.c +++ b/drivers/char/exynos-gpiomem.c @@ -77,8 +77,6 @@ static int exynos_gpiomem_open(struct inode *inode, struct file *file) int dev = iminor(inode); int ret = 0; - dev_info(inst->dev, "gpiomem device opened."); - if (dev != DEVICE_MINOR) { dev_err(inst->dev, "Unknown minor device: %d", dev); ret = -ENXIO; From 9d4c597eabe92facb796e7572288af890aedd133 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Mon, 18 Nov 2019 12:10:34 +0900 Subject: [PATCH 064/133] ODROID-XU4: drivers/fbtft: Add fb_hktft35 module for Hardkernel 3.5 inch TFT LCD No longer use flexfb, fbtft_device that is deprecated since kernel 5.4. Signed-off-by: Yang Deokgyu Change-Id: Iae252c64b91b2eabe97eb3aace12d7c4b98801c5 --- drivers/staging/fbtft/Kconfig | 7 + drivers/staging/fbtft/Makefile | 1 + drivers/staging/fbtft/fb_hktft35.c | 300 +++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/staging/fbtft/fb_hktft35.c diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig index cb61c2a772bdd8..879b12b4259b80 100644 --- a/drivers/staging/fbtft/Kconfig +++ b/drivers/staging/fbtft/Kconfig @@ -199,3 +199,10 @@ config FB_TFT_WATTEROTT depends on FB_TFT help Generic Framebuffer support for WATTEROTT + +config FB_TFT_HKTFT35 + tristate "FB driver for the Hardkernel 3.5 inch TFT LCD" + depends on FB_TFT + help + Generic Framebuffer support for the Hardkernel 3.5 inch TFT LCD + that uses the ILI9488 LCD Controller diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile index 27af43f32f81e1..ac341fb9cb427b 100644 --- a/drivers/staging/fbtft/Makefile +++ b/drivers/staging/fbtft/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_FB_TFT_UC1611) += fb_uc1611.o obj-$(CONFIG_FB_TFT_UC1701) += fb_uc1701.o obj-$(CONFIG_FB_TFT_UPD161704) += fb_upd161704.o obj-$(CONFIG_FB_TFT_WATTEROTT) += fb_watterott.o +obj-$(CONFIG_FB_TFT_HKTFT35) += fb_hktft35.o diff --git a/drivers/staging/fbtft/fb_hktft35.c b/drivers/staging/fbtft/fb_hktft35.c new file mode 100644 index 00000000000000..2389343492d470 --- /dev/null +++ b/drivers/staging/fbtft/fb_hktft35.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * FB driver for the Hardkernel 3.5 inch TFT LCD + * that uses the ILI9488 LCD Controller + * + * Copyright (C) 2019 Yang Deokgyu + * + * Based on fb_ili9340.c by Noralf Tronnes + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "fbtft.h" + +#define DRVNAME "fb_hktft35" +#define WIDTH 320 +#define HEIGHT 480 + +#define ODROIDXU3_GPX1_REG 0x13400C24 +#define ODROIDXU3_GPX2_REG 0x13400C44 +#define ODROIDXU3_GPA2_REG 0x14010044 + +#define ODROID_TFT35_MACTL_MV 0x20 +#define ODROID_TFT35_MACTL_MX 0x40 +#define ODROID_TFT35_MACTL_MY 0x80 + +union reg_bitfield { + unsigned int wvalue; + struct { + unsigned int bit0 : 1; + unsigned int bit1 : 1; + unsigned int bit2 : 1; + unsigned int bit3 : 1; + unsigned int bit4 : 1; + unsigned int bit5 : 1; + unsigned int bit6 : 1; + unsigned int bit7 : 1; + unsigned int bit8_bit31 : 24; + } bits; +}; + +volatile void __iomem *reg_gpx1; +volatile void __iomem *reg_gpx2; +volatile void __iomem *reg_gpa2; + +/* this init sequence matches Hardkernel 3.5 inch TFT LCD */ +static const s16 default_init_sequence[] = { + -1, 0xB0,0x00, + -1, 0x11, + -2, 120, + -1, 0x3A,0x55, + -1, 0xC2,0x33, + -1, 0xC5,0x00,0x1E,0x80, + -1, 0x36,0x28, + -1, 0xB1,0xB0, + -1, 0xE0,0x00,0x04,0x0E,0x08,0x17,0x0A,0x40,0x79,0x4D,0x07,0x0E,0x0A,0x1A,0x1D,0x0F, + -1, 0xE1,0x00,0x1B,0x1F,0x02,0x10,0x05,0x32,0x34,0x43,0x02,0x0A,0x09,0x33,0x37,0x0F, + -1, 0x11, + -1, 0x29, + -3 +}; + +static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) +{ + fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, + "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye); + + /* Column address */ + write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); + + /* Row adress */ + write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); + + /* Memory write */ + write_reg(par, 0x2C); +} + +static int set_var(struct fbtft_par *par) +{ + u8 val; + + switch (par->info->var.rotate) { + case 270: + val = ODROID_TFT35_MACTL_MV; + break; + case 180: + val = ODROID_TFT35_MACTL_MY; + break; + case 90: + val = ODROID_TFT35_MACTL_MV | ODROID_TFT35_MACTL_MX | ODROID_TFT35_MACTL_MY; + break; + default: + val = ODROID_TFT35_MACTL_MX; + break; + } + /* Memory Access Control */ + write_reg(par, 0x36, val | (par->bgr << 3)); + return 0; +} + +static int fbtft_backlight_get_brightness(struct backlight_device *bd) +{ + return bd->props.brightness; +} + +static int fbtft_backlight_update_status(struct backlight_device *bd) +{ + struct fbtft_par *par = bl_get_data(bd); + bool polarity = par->polarity; + + fbtft_par_dbg(DEBUG_BACKLIGHT, par, + "%s: polarity=%d, power=%d, fb_blank=%d\n", + __func__, polarity, bd->props.power, bd->props.fb_blank); + + if ((bd->props.power == FB_BLANK_UNBLANK) && + (bd->props.fb_blank == FB_BLANK_UNBLANK)) + gpiod_set_value(par->gpio.led[0], polarity); + else + gpiod_set_value(par->gpio.led[0], !polarity); + + return 0; +} + +static const struct backlight_ops fbtft_bl_ops = { + .get_brightness = fbtft_backlight_get_brightness, + .update_status = fbtft_backlight_update_status, +}; + +static void register_backlight(struct fbtft_par *par) +{ + struct backlight_device *bd; + struct backlight_properties bl_props = { 0, }; + + if (!par->gpio.led[0]) { + fbtft_par_dbg(DEBUG_BACKLIGHT, par, + "%s(): led pin not set, exiting.\n", __func__); + return; + } + + bl_props.type = BACKLIGHT_RAW; + /* Assume backlight is off, get polarity from current state of pin */ + bl_props.power = FB_BLANK_POWERDOWN; + + /* Force polarity to true */ + par->polarity = true; + + bd = backlight_device_register(dev_driver_string(par->info->device), + par->info->device, par, + &fbtft_bl_ops, &bl_props); + if (IS_ERR(bd)) { + dev_err(par->info->device, + "cannot register backlight device (%ld)\n", + PTR_ERR(bd)); + return; + } + par->info->bl_dev = bd; + + if (!par->fbtftops.unregister_backlight) + par->fbtftops.unregister_backlight = fbtft_unregister_backlight; +} + +static void unregister_backlight(struct fbtft_par *par) +{ + if (par->info->bl_dev) { + par->info->bl_dev->props.power = FB_BLANK_POWERDOWN; + backlight_update_status(par->info->bl_dev); + backlight_device_unregister(par->info->bl_dev); + par->info->bl_dev = NULL; + } + + /* Just to hook the remove routine */ + if (reg_gpx1) iounmap(reg_gpx1); + if (reg_gpx2) iounmap(reg_gpx2); + if (reg_gpa2) iounmap(reg_gpa2); +} + +static int verify_gpios(struct fbtft_par *par) +{ + struct fbtft_platform_data *pdata = par->pdata; + int i; + + fbtft_par_dbg(DEBUG_VERIFY_GPIOS, par, "%s()\n", __func__); + + if (pdata->display.buswidth != 9 && par->startbyte == 0 && + !par->gpio.dc) { + dev_err(par->info->device, + "Missing info about 'dc' gpio. Aborting.\n"); + return -EINVAL; + } + + if (!par->pdev) + return 0; + + if (!par->gpio.wr) { + dev_err(par->info->device, "Missing 'wr' gpio. Aborting.\n"); + return -EINVAL; + } + for (i = 0; i < pdata->display.buswidth; i++) { + if (!par->gpio.db[i]) { + dev_err(par->info->device, + "Missing 'db%02d' gpio. Aborting.\n", i); + return -EINVAL; + } + } + + /* Just to hook the probe routine */ + reg_gpx1 = ioremap(ODROIDXU3_GPX1_REG, 4); + reg_gpx2 = ioremap(ODROIDXU3_GPX2_REG, 4); + reg_gpa2 = ioremap(ODROIDXU3_GPA2_REG, 4); + if ((reg_gpx1 == NULL) || (reg_gpx2 == NULL) || (reg_gpa2 == NULL)) { + pr_err("%s : ioremap gpio registers error!\n", __func__); + } else { + pr_info("%s : ioremap gpio registers success!\n", __func__); + } + + return 0; +} + +static void reset(struct fbtft_par *par) +{ + if (!par->gpio.reset) + return; + fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__); + gpiod_set_value_cansleep(par->gpio.reset, 0); + usleep_range(20, 40); + gpiod_set_value_cansleep(par->gpio.reset, 1); + msleep(120); +} + +static int write(struct fbtft_par *par, void *buf, size_t len) +{ + u8 data; + union reg_bitfield gpx1, gpx2, gpa2; + + if ((reg_gpx1 == NULL) || (reg_gpx2 == NULL) || (reg_gpa2 == NULL)) { + pr_err("%s : ioremap gpio register fail!\n", __func__); + return 0; + } + + fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, + "%s(len=%zu): ", __func__, len); + + gpx1.wvalue = ioread32(reg_gpx1); + gpx2.wvalue = ioread32(reg_gpx2); + gpa2.wvalue = ioread32(reg_gpa2); + + while (len--) { + data = *(u8 *) buf; + gpx1.bits.bit7 = (data & 0x01) ? 1 : 0; + gpx2.bits.bit0 = (data & 0x02) ? 1 : 0; + gpx1.bits.bit3 = (data & 0x04) ? 1 : 0; + gpa2.bits.bit4 = (data & 0x08) ? 1 : 0; + gpa2.bits.bit6 = (data & 0x10) ? 1 : 0; + gpa2.bits.bit7 = (data & 0x20) ? 1 : 0; + gpx1.bits.bit6 = (data & 0x40) ? 1 : 0; + gpx1.bits.bit5 = (data & 0x80) ? 1 : 0; + /* Start writing by pulling down /WR */ + gpa2.bits.bit5 = 0; + iowrite32(gpx1.wvalue, reg_gpx1); + iowrite32(gpx2.wvalue, reg_gpx2); + iowrite32(gpa2.wvalue, reg_gpa2); + gpa2.bits.bit5 = 1; + iowrite32(gpa2.wvalue, reg_gpa2); + + buf++; + } + + return 0; +} + +static struct fbtft_display display = { + .regwidth = 8, + .buswidth = 8, + .width = WIDTH, + .height = HEIGHT, + .init_sequence = default_init_sequence, + .fbtftops = { + .set_addr_win = set_addr_win, + .set_var = set_var, + .verify_gpios = verify_gpios, + .register_backlight = register_backlight, + .unregister_backlight = unregister_backlight, + .reset = reset, + .write = write, + }, +}; +FBTFT_REGISTER_DRIVER(DRVNAME, "odroid,hktft35", &display); + +MODULE_ALIAS("platform:" DRVNAME); +MODULE_ALIAS("platform:hktft35"); + +MODULE_DESCRIPTION("FB driver for the Hardkernel 3.5 inch TFT LCD uses the ILI9488 LCD Controller"); +MODULE_AUTHOR("Yang Deokgyu"); +MODULE_LICENSE("GPL"); From d4c18c1d3e6775a22680073ec7370c9590a80931 Mon Sep 17 00:00:00 2001 From: Yang Deokgyu Date: Thu, 21 Nov 2019 15:17:36 +0900 Subject: [PATCH 065/133] ODROID-XU4: drivers/fbtft: Add fb_hktft32 module for Hardkernel 3.2 inch TFT LCD No longer use flexfb, fbtft_device that is deprecated since kernel 5.4. Signed-off-by: Yang Deokgyu Change-Id: Iebd014360f90eab5210722102d54c6169be5e28e --- drivers/staging/fbtft/Kconfig | 7 ++ drivers/staging/fbtft/Makefile | 1 + drivers/staging/fbtft/fb_hktft32.c | 156 +++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 drivers/staging/fbtft/fb_hktft32.c diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig index 879b12b4259b80..9ae059f138c651 100644 --- a/drivers/staging/fbtft/Kconfig +++ b/drivers/staging/fbtft/Kconfig @@ -206,3 +206,10 @@ config FB_TFT_HKTFT35 help Generic Framebuffer support for the Hardkernel 3.5 inch TFT LCD that uses the ILI9488 LCD Controller + +config FB_TFT_HKTFT32 + tristate "FB driver for the Hardkernel 3.2 inch TFT LCD" + depends on FB_TFT + help + Generic Framebuffer support for the Hardkernel 3.2 inch TFT LCD + that uses the ILI9340 LCD Controller diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile index ac341fb9cb427b..4b1c434d619090 100644 --- a/drivers/staging/fbtft/Makefile +++ b/drivers/staging/fbtft/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_FB_TFT_UC1701) += fb_uc1701.o obj-$(CONFIG_FB_TFT_UPD161704) += fb_upd161704.o obj-$(CONFIG_FB_TFT_WATTEROTT) += fb_watterott.o obj-$(CONFIG_FB_TFT_HKTFT35) += fb_hktft35.o +obj-$(CONFIG_FB_TFT_HKTFT32) += fb_hktft32.o diff --git a/drivers/staging/fbtft/fb_hktft32.c b/drivers/staging/fbtft/fb_hktft32.c new file mode 100644 index 00000000000000..33ac19603cadea --- /dev/null +++ b/drivers/staging/fbtft/fb_hktft32.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * FB driver for the Hardkernel 3.2 inch TFT LCD + * that uses the ILI9340 LCD Controller + * + * Copyright (C) 2019 Yang Deokgyu + * + * Based on fb_ili9340.c by Noralf Tronnes + */ + +#include +#include +#include +#include +#include +#include