Merge pull request #1924 from Gelbpunkt/aarch64_be

feat: aarch64_be support

Author: mkroening

.github/workflows/ci.yml

@@ -38,6 +38,12 @@ jobs:
           cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64-unknown-none-softfloat --exclude-features dhcpv4,dns,gem-net,net,rtl8139,virtio-net --features pci
           cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64-unknown-none-softfloat --exclude-features gem-net,rtl8139 --features tcp,virtio-net
           cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64-unknown-none-softfloat --exclude-features gem-net,rtl8139 --features pci,tcp,virtio-net
+      - name: cargo hack check (aarch64_be)
+        run: |
+          cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64_be-unknown-none-softfloat -Zbuild-std=core,alloc --exclude-features dhcpv4,dns,gem-net,net,rtl8139,virtio-net
+          cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64_be-unknown-none-softfloat -Zbuild-std=core,alloc --exclude-features dhcpv4,dns,gem-net,net,rtl8139,virtio-net --features pci
+          cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64_be-unknown-none-softfloat -Zbuild-std=core,alloc --exclude-features gem-net,rtl8139 --features tcp,virtio-net
+          cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target aarch64_be-unknown-none-softfloat -Zbuild-std=core,alloc --exclude-features gem-net,rtl8139 --features pci,tcp,virtio-net
       - name: cargo hack check (riscv64)
         run: |
           cargo hack check --package hermit-kernel --each-feature --no-dev-deps --target riscv64gc-unknown-none-elf --exclude-features dhcpv4,dns,gem-net,net,rtl8139,virtio-net
@@ -92,6 +98,7 @@ jobs:
         run: |
           cargo xtask build --arch x86_64 --no-default-features
           cargo xtask build --arch aarch64 --no-default-features
+          cargo xtask build --arch aarch64_be --no-default-features
 
   test:
     name: Test
@@ -119,15 +126,15 @@ jobs:
 
   run-hermit:
     name: Run
-    runs-on: ${{ matrix.arch == 'aarch64' && 'ubuntu-24.04-arm' || 'ubuntu-24.04' }}
+    runs-on: ${{ (matrix.arch == 'aarch64' || matrix.arch == 'aarch64_be') && 'ubuntu-24.04-arm' || 'ubuntu-24.04' }}
     env:
       HERMIT_CAREFUL: ${{ matrix.hermit-careful }}
     defaults:
       run:
         working-directory: kernel
     strategy:
       matrix:
-        arch: [x86_64, aarch64, riscv64]
+        arch: [x86_64, aarch64, aarch64_be, riscv64]
         profile: [dev, release]
         include:
           - profile: dev
@@ -137,6 +144,8 @@ jobs:
             flags: --accel --sudo
           - arch: aarch64
             packages: qemu-system-aarch64 ipxe-qemu
+          - arch: aarch64_be
+            packages: qemu-system-aarch64 ipxe-qemu
           - arch: riscv64
             packages: qemu-system-misc
 

Cargo.lock

@@ -216,3 +216,4 @@ exclude = [
 x86_64 = { git = "https://github.com/rust-osdev/x86_64.git" }
 # FIXME: remove once merged: https://github.com/rcore-os/trapframe-rs/pull/16
 trapframe = { git = "https://github.com/hermit-os/trapframe-rs", branch = "global_asm" }
+safe-mmio = { git = "https://github.com/hermit-os/safe-mmio", branch = "be" }

Cargo.toml

@@ -118,6 +118,49 @@ const fn mair(attr: u64, mt: u64) -> u64 {
 #[cfg(feature = "smp")]
 pub(crate) static TTBR0: AtomicPtr<u8> = AtomicPtr::new(core::ptr::null_mut());
 
+// Prepare system control register (SCTRL)
+//
+// UCI     [26] Enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
+//              DC CVAC and IC IVAU instructions
+// EE      [25] Explicit data accesses at EL1 and Stage 1 translation
+//              table walks at EL1 & EL0 are little-endian
+// EOE     [24] Explicit data accesses at EL0 are little-endian
+// WXN     [19] Regions with write permission are not forced to XN
+// nTWE    [18] WFE instructions are executed as normal
+// nTWI    [16] WFI instructions are executed as normal
+// UCT     [15] Enables EL0 access in AArch64 to the CTR_EL0 register
+// DZE     [14] Execution of the DC ZVA instruction is allowed at EL0
+// I       [12] Instruction caches enabled at EL0 and EL1
+// UMA     [9]  Disable access to the interrupt masks from EL0
+// SED     [8]  The SETEND instruction is available
+// ITD     [7]  The IT instruction functionality is available
+// THEE    [6]  ThumbEE is disabled
+// CP15BEN [5]  CP15 barrier operations disabled
+// SA0     [4]  Stack Alignment check for EL0 enabled
+// SA      [3]  Stack Alignment check enabled
+// C       [2]  Data and unified enabled
+// A       [1]  Alignment fault checking disabled
+// M       [0]  MMU enable
+#[cfg(all(feature = "smp", target_endian = "little"))]
+static SCTLR_EL1: u64 = 0b100_0000_0101_1101_0000_0001_1101;
+// The same, but EE and EOE are set to 1 for big endian.
+#[cfg(all(feature = "smp", target_endian = "big"))]
+static SCTLR_EL1: u64 = 0b111_0000_0101_1101_0000_0001_1101;
+
+#[cfg(all(feature = "smp", target_endian = "little"))]
+macro_rules! configure_endianness {
+	() => {
+		"bic x2, x2, #(1 << 24 | 1 << 25)"
+	};
+}
+
+#[cfg(all(feature = "smp", target_endian = "big"))]
+macro_rules! configure_endianness {
+	() => {
+		"orr x2, x2, #(1 << 24 | 1 << 25)"
+	};
+}
+
 #[cfg(feature = "smp")]
 #[unsafe(naked)]
 pub(crate) unsafe extern "C" fn smp_start() -> ! {
@@ -132,10 +175,12 @@ pub(crate) unsafe extern "C" fn smp_start() -> ! {
 		"msr tpidr_el0, xzr",
 		"msr tpidr_el1, xzr",
 
-		// Disable the MMU
+		// Disable the MMU and set the correct endianness
+		// by either clearing or setting bits 25 and 24 (EE and EOE)
 		"dsb sy",
 		"mrs x2, sctlr_el1",
 		"bic x2, x2, #0x1",
+		configure_endianness!(),
 		"msr sctlr_el1, x2",
 		"isb",
 
@@ -189,31 +234,8 @@ pub(crate) unsafe extern "C" fn smp_start() -> ! {
 		"ldr x5, [x8, #:lo12:{ttbr0}]",
 		"msr ttbr0_el1, x5",
 
-		// Prepare system control register (SCTRL)
-		//
-		// UCI     [26] Enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
-		//				DC CVAC and IC IVAU instructions
-		// EE      [25] Explicit data accesses at EL1 and Stage 1 translation
-		//				table walks at EL1 & EL0 are little-endian
-		// EOE     [24] Explicit data accesses at EL0 are little-endian
-		// WXN     [19] Regions with write permission are not forced to XN
-		// nTWE    [18] WFE instructions are executed as normal
-		// nTWI    [16] WFI instructions are executed as normal
-		// UCT     [15] Enables EL0 access in AArch64 to the CTR_EL0 register
-		// DZE     [14] Execution of the DC ZVA instruction is allowed at EL0
-		// I       [12] Instruction caches enabled at EL0 and EL1
-		// UMA     [9]  Disable access to the interrupt masks from EL0
-		// SED     [8]  The SETEND instruction is available
-		// ITD     [7]  The IT instruction functionality is available
-		// THEE    [6]  ThumbEE is disabled
-		// CP15BEN [5]  CP15 barrier operations disabled
-		// SA0     [4]  Stack Alignment check for EL0 enabled
-		// SA      [3]  Stack Alignment check enabled
-		// C       [2]  Data and unified enabled
-		// A       [1]  Alignment fault checking disabled
-		// M       [0]  MMU enable
-		"ldr x0, =0x405d01d",
-		  "msr sctlr_el1, x0",
+		"ldr x0, ={sctlr_el1}",
+		"msr sctlr_el1, x0",
 
 		// initialize argument for pre_init
 		"mov x0, xzr",
@@ -227,6 +249,7 @@ pub(crate) unsafe extern "C" fn smp_start() -> ! {
 		tcr_bits = const tcr_size(VA_BITS) | TCR_TG1_4K | TCR_FLAGS,
 		stack_top_offset = const KERNEL_STACK_SIZE - TaskStacks::MARKER_SIZE,
 		current_stack_address = sym super::CURRENT_STACK_ADDRESS,
+		sctlr_el1 = const SCTLR_EL1,
 		ttbr0 = sym TTBR0,
 		pre_init = sym pre_init,
 	)

src/arch/aarch64/kernel/start.rs

@@ -11,6 +11,8 @@ pub enum Arch {
 	X86_64,
 	/// AArch64
 	Aarch64,
+	/// AArch64, big-endian
+	Aarch64Be,
 	/// 64-bit RISC-V
 	Riscv64,
 }
@@ -21,6 +23,10 @@ impl Arch {
 	}
 
 	pub fn install(&self) -> Result<()> {
+		if self.tier() > 2 {
+			return Ok(());
+		}
+
 		let mut rustup = crate::rustup();
 		rustup.args(["target", "add", self.triple()]);
 
@@ -42,14 +48,23 @@ impl Arch {
 		match self {
 			Self::X86_64 => "x86_64",
 			Self::Aarch64 => "aarch64",
+			Self::Aarch64Be => "aarch64_be",
 			Self::Riscv64 => "riscv64",
 		}
 	}
 
+	pub fn tier(&self) -> u8 {
+		match self {
+			Self::Aarch64Be => 3,
+			_ => 2,
+		}
+	}
+
 	pub fn triple(&self) -> &'static str {
 		match self {
 			Self::X86_64 => "x86_64-unknown-none",
 			Self::Aarch64 => "aarch64-unknown-none-softfloat",
+			Self::Aarch64Be => "aarch64_be-unknown-none-softfloat",
 			Self::Riscv64 => "riscv64gc-unknown-none-elf",
 		}
 	}
@@ -58,6 +73,7 @@ impl Arch {
 		match self {
 			Self::X86_64 => "x86_64-unknown-hermit",
 			Self::Aarch64 => "aarch64-unknown-hermit",
+			Self::Aarch64Be => "aarch64_be-unknown-hermit",
 			Self::Riscv64 => "riscv64gc-unknown-hermit",
 		}
 	}
@@ -74,6 +90,11 @@ impl Arch {
 				"-Zbuild-std=core",
 				"-Zbuild-std-features=compiler-builtins-mem",
 			],
+			Self::Aarch64Be => &[
+				"--target=aarch64_be-unknown-hermit",
+				"-Zbuild-std=core",
+				"-Zbuild-std-features=compiler-builtins-mem",
+			],
 			Arch::Riscv64 => &[
 				"--target=riscv64gc-unknown-hermit",
 				"-Zbuild-std=core",
@@ -92,6 +113,13 @@ impl Arch {
 				"-Zbuild-std=core,alloc",
 				"-Zbuild-std-features=compiler-builtins-mem",
 			],
+			Self::Aarch64Be => &[
+				"--target=aarch64_be-unknown-none-softfloat",
+				// We can't use prebuilt std here because it is built with
+				// relocation-model=static and we need relocation-model=pic
+				"-Zbuild-std=core,alloc",
+				"-Zbuild-std-features=compiler-builtins-mem",
+			],
 			Self::Riscv64 => &[
 				"--target=riscv64gc-unknown-none-elf",
 				// We can't use prebuilt std here because it is built with
@@ -112,6 +140,10 @@ impl Arch {
 				"--target=aarch64-unknown-hermit",
 				"-Zbuild-std=std,panic_abort",
 			],
+			Self::Aarch64Be => &[
+				"--target=aarch64_be-unknown-hermit",
+				"-Zbuild-std=std,panic_abort",
+			],
 			Arch::Riscv64 => &[
 				"--target=riscv64gc-unknown-hermit",
 				"-Zbuild-std=std,panic_abort",
@@ -122,10 +154,18 @@ impl Arch {
 	pub fn rustflags(&self) -> &'static [&'static str] {
 		match self {
 			Self::X86_64 => &[],
-			Self::Aarch64 => &["-Crelocation-model=pic"],
+			Self::Aarch64 | Self::Aarch64Be => &["-Crelocation-model=pic"],
 			Self::Riscv64 => &["-Cno-redzone", "-Crelocation-model=pic"],
 		}
 	}
+
+	pub fn qemu(&self) -> &'static str {
+		match self {
+			Self::X86_64 => "x86_64",
+			Self::Aarch64 | Self::Aarch64Be => "aarch64",
+			Self::Riscv64 => "riscv64",
+		}
+	}
 }
 
 impl fmt::Display for Arch {

xtask/src/arch.rs

@@ -88,7 +88,7 @@ impl Qemu {
 			sh.create_dir("shared/tracedir")?;
 		}
 
-		let qemu = env::var("QEMU").unwrap_or_else(|_| format!("qemu-system-{arch}"));
+		let qemu = env::var("QEMU").unwrap_or_else(|_| format!("qemu-system-{}", arch.qemu()));
 		let program = if self.sudo { "sudo" } else { qemu.as_str() };
 		let arg = self.sudo.then_some(qemu.as_str());
 		let memory = self.memory(image_name, arch, small);
@@ -208,7 +208,7 @@ impl Qemu {
 					image_args.push("-initrd".to_string());
 					image_args.push(image.to_str().unwrap().to_string());
 				}
-				Arch::Aarch64 => {
+				Arch::Aarch64 | Arch::Aarch64Be => {
 					image_args.push("-device".to_string());
 					image_args.push(format!(
 						"guest-loader,addr=0x48000000,initrd={}",
@@ -233,7 +233,7 @@ impl Qemu {
 				"-nodefaults".to_string(),
 				"-no-user-config".to_string(),
 			]
-		} else if arch == Arch::Aarch64 {
+		} else if arch == Arch::Aarch64 || arch == Arch::Aarch64Be {
 			vec!["-machine".to_string(), "virt,gic-version=3".to_string()]
 		} else if arch == Arch::Riscv64 {
 			// CadenceGem requires sifive_u
@@ -273,7 +273,7 @@ impl Qemu {
 				cpu_args.push("isa-debug-exit,iobase=0xf4,iosize=0x04".to_string());
 				cpu_args
 			}
-			Arch::Aarch64 => {
+			Arch::Aarch64 | Arch::Aarch64Be => {
 				let mut cpu_args = if self.accel {
 					todo!()
 				} else {
@@ -306,7 +306,7 @@ impl Qemu {
 						32
 					}
 				}
-				Arch::Aarch64 => 144,
+				Arch::Aarch64 | Arch::Aarch64Be => 144,
 				Arch::Riscv64 => 40,
 			};
 		}

xtask/src/ci/qemu.rs

@@ -38,7 +38,7 @@ impl Clippy {
 				Arch::X86_64 => {
 					clippy().arg("--features=shell").run()?;
 				}
-				Arch::Aarch64 => {}
+				Arch::Aarch64 | Arch::Aarch64Be => {}
 				Arch::Riscv64 => {
 					clippy()
 						.arg("--no-default-features")