@@ -31,4 +31,34 @@ def ConvertOneDNNGraphToLinalg : Pass<"convert-onednn-graph-to-linalg"> {
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];
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}
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+ def LowerToTileVector : Pass<"lower-to-tile-vector"> {
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+ let summary = "Lower tensor to tile vector.";
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+ let description = [{
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+ Lower tensor to tile vector form.
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+ }];
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+ let dependentDialects = [
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+ "::mlir::func::FuncDialect",
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+ "::mlir::math::MathDialect",
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+ "::mlir::arith::ArithDialect",
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+ "::mlir::tensor::TensorDialect",
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+ "::mlir::linalg::LinalgDialect",
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+ "::mlir::vector::VectorDialect",
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+ ];
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+ }
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+
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+ def CPUPhysicalRegisterPass : Pass<"CPU-physical-register-pass", "func::FuncOp"> {
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+ let summary = "Lower operation to cpu pysical register size.";
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+ let description = [{
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+ Physical register size lowering pass.
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+ }];
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+ let dependentDialects = [
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+ "::mlir::func::FuncDialect",
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+ "::mlir::math::MathDialect",
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+ "::mlir::arith::ArithDialect",
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+ "::mlir::tensor::TensorDialect",
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+ "::mlir::vector::VectorDialect",
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+ "::mlir::scf::SCFDialect",
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+ ];
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+ }
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+
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#endif // GC_DIALECT_GC_PASSES
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